mtk_eth.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2018 MediaTek Inc.
  4. *
  5. * Author: Weijie Gao <weijie.gao@mediatek.com>
  6. * Author: Mark Lee <mark-mc.lee@mediatek.com>
  7. */
  8. #ifndef _MTK_ETH_H_
  9. #define _MTK_ETH_H_
  10. /* Frame Engine Register Bases */
  11. #include <linux/bitops.h>
  12. #define PDMA_BASE 0x0800
  13. #define GDMA1_BASE 0x0500
  14. #define GDMA2_BASE 0x1500
  15. #define GMAC_BASE 0x10000
  16. /* Ethernet subsystem registers */
  17. #define ETHSYS_SYSCFG0_REG 0x14
  18. #define SYSCFG0_GE_MODE_S(n) (12 + ((n) * 2))
  19. #define SYSCFG0_GE_MODE_M 0x3
  20. #define SYSCFG0_SGMII_SEL_M (0x3 << 8)
  21. #define SYSCFG0_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8))
  22. #define ETHSYS_CLKCFG0_REG 0x2c
  23. #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
  24. /* SYSCFG0_GE_MODE: GE Modes */
  25. #define GE_MODE_RGMII 0
  26. #define GE_MODE_MII 1
  27. #define GE_MODE_MII_PHY 2
  28. #define GE_MODE_RMII 3
  29. /* SGMII subsystem config registers */
  30. #define SGMSYS_PCS_CONTROL_1 0x0
  31. #define SGMII_LINK_STATUS BIT(18)
  32. #define SGMII_AN_ENABLE BIT(12)
  33. #define SGMII_AN_RESTART BIT(9)
  34. #define SGMSYS_SGMII_MODE 0x20
  35. #define SGMII_FORCE_MODE 0x31120019
  36. #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
  37. #define SGMII_PHYA_PWD BIT(4)
  38. #define SGMSYS_GEN2_SPEED 0x2028
  39. #define SGMSYS_GEN2_SPEED_V2 0x128
  40. #define SGMSYS_SPEED_2500 BIT(2)
  41. /* Frame Engine Registers */
  42. /* PDMA */
  43. #define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10)
  44. #define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10)
  45. #define TX_CTX_IDX_REG(n) (0x008 + (n) * 0x10)
  46. #define TX_DTX_IDX_REG(n) (0x00c + (n) * 0x10)
  47. #define RX_BASE_PTR_REG(n) (0x100 + (n) * 0x10)
  48. #define RX_MAX_CNT_REG(n) (0x104 + (n) * 0x10)
  49. #define RX_CRX_IDX_REG(n) (0x108 + (n) * 0x10)
  50. #define RX_DRX_IDX_REG(n) (0x10c + (n) * 0x10)
  51. #define PDMA_GLO_CFG_REG 0x204
  52. #define TX_WB_DDONE BIT(6)
  53. #define RX_DMA_BUSY BIT(3)
  54. #define RX_DMA_EN BIT(2)
  55. #define TX_DMA_BUSY BIT(1)
  56. #define TX_DMA_EN BIT(0)
  57. #define PDMA_RST_IDX_REG 0x208
  58. #define RST_DRX_IDX0 BIT(16)
  59. #define RST_DTX_IDX0 BIT(0)
  60. /* GDMA */
  61. #define GDMA_IG_CTRL_REG 0x000
  62. #define GDM_ICS_EN BIT(22)
  63. #define GDM_TCS_EN BIT(21)
  64. #define GDM_UCS_EN BIT(20)
  65. #define STRP_CRC BIT(16)
  66. #define MYMAC_DP_S 12
  67. #define MYMAC_DP_M 0xf000
  68. #define BC_DP_S 8
  69. #define BC_DP_M 0xf00
  70. #define MC_DP_S 4
  71. #define MC_DP_M 0xf0
  72. #define UN_DP_S 0
  73. #define UN_DP_M 0x0f
  74. #define GDMA_MAC_LSB_REG 0x008
  75. #define GDMA_MAC_MSB_REG 0x00c
  76. /* MYMAC_DP/BC_DP/MC_DP/UN_DP: Destination ports */
  77. #define DP_PDMA 0
  78. #define DP_GDMA1 1
  79. #define DP_GDMA2 2
  80. #define DP_PPE 4
  81. #define DP_QDMA 5
  82. #define DP_DISCARD 7
  83. /* GMAC Registers */
  84. #define GMAC_PIAC_REG 0x0004
  85. #define PHY_ACS_ST BIT(31)
  86. #define MDIO_REG_ADDR_S 25
  87. #define MDIO_REG_ADDR_M 0x3e000000
  88. #define MDIO_PHY_ADDR_S 20
  89. #define MDIO_PHY_ADDR_M 0x1f00000
  90. #define MDIO_CMD_S 18
  91. #define MDIO_CMD_M 0xc0000
  92. #define MDIO_ST_S 16
  93. #define MDIO_ST_M 0x30000
  94. #define MDIO_RW_DATA_S 0
  95. #define MDIO_RW_DATA_M 0xffff
  96. /* MDIO_CMD: MDIO commands */
  97. #define MDIO_CMD_ADDR 0
  98. #define MDIO_CMD_WRITE 1
  99. #define MDIO_CMD_READ 2
  100. #define MDIO_CMD_READ_C45 3
  101. /* MDIO_ST: MDIO start field */
  102. #define MDIO_ST_C45 0
  103. #define MDIO_ST_C22 1
  104. #define GMAC_PORT_MCR(p) (0x0100 + (p) * 0x100)
  105. #define MAC_RX_PKT_LEN_S 24
  106. #define MAC_RX_PKT_LEN_M 0x3000000
  107. #define IPG_CFG_S 18
  108. #define IPG_CFG_M 0xc0000
  109. #define MAC_MODE BIT(16)
  110. #define FORCE_MODE BIT(15)
  111. #define MAC_TX_EN BIT(14)
  112. #define MAC_RX_EN BIT(13)
  113. #define BKOFF_EN BIT(9)
  114. #define BACKPR_EN BIT(8)
  115. #define FORCE_RX_FC BIT(5)
  116. #define FORCE_TX_FC BIT(4)
  117. #define FORCE_SPD_S 2
  118. #define FORCE_SPD_M 0x0c
  119. #define FORCE_DPX BIT(1)
  120. #define FORCE_LINK BIT(0)
  121. /* Values of IPG_CFG */
  122. #define IPG_96BIT 0
  123. #define IPG_96BIT_WITH_SHORT_IPG 1
  124. #define IPG_64BIT 2
  125. /* MAC_RX_PKT_LEN: Max RX packet length */
  126. #define MAC_RX_PKT_LEN_1518 0
  127. #define MAC_RX_PKT_LEN_1536 1
  128. #define MAC_RX_PKT_LEN_1552 2
  129. #define MAC_RX_PKT_LEN_JUMBO 3
  130. /* FORCE_SPD: Forced link speed */
  131. #define SPEED_10M 0
  132. #define SPEED_100M 1
  133. #define SPEED_1000M 2
  134. #define GMAC_TRGMII_RCK_CTRL 0x300
  135. #define RX_RST BIT(31)
  136. #define RXC_DQSISEL BIT(30)
  137. #define GMAC_TRGMII_TD_ODT(n) (0x354 + (n) * 8)
  138. #define TD_DM_DRVN_S 4
  139. #define TD_DM_DRVN_M 0xf0
  140. #define TD_DM_DRVP_S 0
  141. #define TD_DM_DRVP_M 0x0f
  142. /* MT7530 Registers */
  143. #define PCR_REG(p) (0x2004 + (p) * 0x100)
  144. #define PORT_MATRIX_S 16
  145. #define PORT_MATRIX_M 0xff0000
  146. #define PVC_REG(p) (0x2010 + (p) * 0x100)
  147. #define STAG_VPID_S 16
  148. #define STAG_VPID_M 0xffff0000
  149. #define VLAN_ATTR_S 6
  150. #define VLAN_ATTR_M 0xc0
  151. /* VLAN_ATTR: VLAN attributes */
  152. #define VLAN_ATTR_USER 0
  153. #define VLAN_ATTR_STACK 1
  154. #define VLAN_ATTR_TRANSLATION 2
  155. #define VLAN_ATTR_TRANSPARENT 3
  156. #define PMCR_REG(p) (0x3000 + (p) * 0x100)
  157. /* XXX: all fields of MT7530 are defined under GMAC_PORT_MCR
  158. * MT7531 specific fields are defined below
  159. */
  160. #define FORCE_MODE_EEE1G BIT(25)
  161. #define FORCE_MODE_EEE100 BIT(26)
  162. #define FORCE_MODE_TX_FC BIT(27)
  163. #define FORCE_MODE_RX_FC BIT(28)
  164. #define FORCE_MODE_DPX BIT(29)
  165. #define FORCE_MODE_SPD BIT(30)
  166. #define FORCE_MODE_LNK BIT(31)
  167. #define MT7531_FORCE_MODE FORCE_MODE_EEE1G | FORCE_MODE_EEE100 |\
  168. FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
  169. FORCE_MODE_DPX | FORCE_MODE_SPD | \
  170. FORCE_MODE_LNK
  171. /* MT7531 SGMII Registers */
  172. #define MT7531_SGMII_REG_BASE 0x5000
  173. #define MT7531_SGMII_REG_PORT_BASE 0x1000
  174. #define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
  175. (p) * MT7531_SGMII_REG_PORT_BASE + (r))
  176. #define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(((p) - 5), 0x00)
  177. #define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(((p) - 5), 0x20)
  178. #define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(((p) - 5), 0xe8)
  179. #define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(((p) - 5), 0x128)
  180. /* XXX: all fields of MT7531 SGMII are defined under SGMSYS */
  181. /* MT753x System Control Register */
  182. #define SYS_CTRL_REG 0x7000
  183. #define SW_PHY_RST BIT(2)
  184. #define SW_SYS_RST BIT(1)
  185. #define SW_REG_RST BIT(0)
  186. /* MT7531 */
  187. #define MT7531_PHY_IAC 0x701c
  188. /* XXX: all fields are defined under GMAC_PIAC_REG */
  189. #define MT7531_CLKGEN_CTRL 0x7500
  190. #define CLK_SKEW_OUT_S 8
  191. #define CLK_SKEW_OUT_M 0x300
  192. #define CLK_SKEW_IN_S 6
  193. #define CLK_SKEW_IN_M 0xc0
  194. #define RXCLK_NO_DELAY BIT(5)
  195. #define TXCLK_NO_REVERSE BIT(4)
  196. #define GP_MODE_S 1
  197. #define GP_MODE_M 0x06
  198. #define GP_CLK_EN BIT(0)
  199. /* Values of GP_MODE */
  200. #define GP_MODE_RGMII 0
  201. #define GP_MODE_MII 1
  202. #define GP_MODE_REV_MII 2
  203. /* Values of CLK_SKEW_IN */
  204. #define CLK_SKEW_IN_NO_CHANGE 0
  205. #define CLK_SKEW_IN_DELAY_100PPS 1
  206. #define CLK_SKEW_IN_DELAY_200PPS 2
  207. #define CLK_SKEW_IN_REVERSE 3
  208. /* Values of CLK_SKEW_OUT */
  209. #define CLK_SKEW_OUT_NO_CHANGE 0
  210. #define CLK_SKEW_OUT_DELAY_100PPS 1
  211. #define CLK_SKEW_OUT_DELAY_200PPS 2
  212. #define CLK_SKEW_OUT_REVERSE 3
  213. #define HWTRAP_REG 0x7800
  214. /* MT7530 Modified Hardware Trap Status Registers */
  215. #define MHWTRAP_REG 0x7804
  216. #define CHG_TRAP BIT(16)
  217. #define LOOPDET_DIS BIT(14)
  218. #define P5_INTF_SEL_S 13
  219. #define P5_INTF_SEL_M 0x2000
  220. #define SMI_ADDR_S 11
  221. #define SMI_ADDR_M 0x1800
  222. #define XTAL_FSEL_S 9
  223. #define XTAL_FSEL_M 0x600
  224. #define P6_INTF_DIS BIT(8)
  225. #define P5_INTF_MODE_S 7
  226. #define P5_INTF_MODE_M 0x80
  227. #define P5_INTF_DIS BIT(6)
  228. #define C_MDIO_BPS BIT(5)
  229. #define CHIP_MODE_S 0
  230. #define CHIP_MODE_M 0x0f
  231. /* P5_INTF_SEL: Interface type of Port5 */
  232. #define P5_INTF_SEL_GPHY 0
  233. #define P5_INTF_SEL_GMAC5 1
  234. /* P5_INTF_MODE: Interface mode of Port5 */
  235. #define P5_INTF_MODE_GMII_MII 0
  236. #define P5_INTF_MODE_RGMII 1
  237. #define MT7530_P6ECR 0x7830
  238. #define P6_INTF_MODE_M 0x3
  239. #define P6_INTF_MODE_S 0
  240. /* P6_INTF_MODE: Interface mode of Port6 */
  241. #define P6_INTF_MODE_RGMII 0
  242. #define P6_INTF_MODE_TRGMII 1
  243. #define NUM_TRGMII_CTRL 5
  244. #define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8)
  245. #define RD_TAP_S 0
  246. #define RD_TAP_M 0x7f
  247. #define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8)
  248. /* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */
  249. /* TOP Signals Status Register */
  250. #define MT7531_TOP_SIG_SR 0x780c
  251. #define PAD_MCM_SMI_EN BIT(0)
  252. #define PAD_DUAL_SGMII_EN BIT(1)
  253. /* MT7531 PLLGP Registers */
  254. #define MT7531_PLLGP_EN 0x7820
  255. #define EN_COREPLL BIT(2)
  256. #define SW_CLKSW BIT(1)
  257. #define SW_PLLGP BIT(0)
  258. #define MT7531_PLLGP_CR0 0x78a8
  259. #define RG_COREPLL_EN BIT(22)
  260. #define RG_COREPLL_POSDIV_S 23
  261. #define RG_COREPLL_POSDIV_M 0x3800000
  262. #define RG_COREPLL_SDM_PCW_S 1
  263. #define RG_COREPLL_SDM_PCW_M 0x3ffffe
  264. #define RG_COREPLL_SDM_PCW_CHG BIT(0)
  265. /* MT7531 RGMII and SGMII PLL clock */
  266. #define MT7531_ANA_PLLGP_CR2 0x78b0
  267. #define MT7531_ANA_PLLGP_CR5 0x78bc
  268. /* MT7531 GPIO GROUP IOLB SMT0 Control */
  269. #define MT7531_SMT0_IOLB 0x7f04
  270. #define SMT_IOLB_5_SMI_MDC_EN BIT(5)
  271. /* MT7530 GPHY MDIO Indirect Access Registers */
  272. #define MII_MMD_ACC_CTL_REG 0x0d
  273. #define MMD_CMD_S 14
  274. #define MMD_CMD_M 0xc000
  275. #define MMD_DEVAD_S 0
  276. #define MMD_DEVAD_M 0x1f
  277. /* MMD_CMD: MMD commands */
  278. #define MMD_ADDR 0
  279. #define MMD_DATA 1
  280. #define MMD_DATA_RW_POST_INC 2
  281. #define MMD_DATA_W_POST_INC 3
  282. #define MII_MMD_ADDR_DATA_REG 0x0e
  283. /* MT7530 GPHY MDIO MMD Registers */
  284. #define CORE_PLL_GROUP2 0x401
  285. #define RG_SYSPLL_EN_NORMAL BIT(15)
  286. #define RG_SYSPLL_VODEN BIT(14)
  287. #define RG_SYSPLL_POSDIV_S 5
  288. #define RG_SYSPLL_POSDIV_M 0x60
  289. #define CORE_PLL_GROUP4 0x403
  290. #define MT7531_BYPASS_MODE BIT(4)
  291. #define MT7531_POWER_ON_OFF BIT(5)
  292. #define RG_SYSPLL_DDSFBK_EN BIT(12)
  293. #define RG_SYSPLL_BIAS_EN BIT(11)
  294. #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
  295. #define CORE_PLL_GROUP5 0x404
  296. #define RG_LCDDS_PCW_NCPO1_S 0
  297. #define RG_LCDDS_PCW_NCPO1_M 0xffff
  298. #define CORE_PLL_GROUP6 0x405
  299. #define RG_LCDDS_PCW_NCPO0_S 0
  300. #define RG_LCDDS_PCW_NCPO0_M 0xffff
  301. #define CORE_PLL_GROUP7 0x406
  302. #define RG_LCDDS_PWDB BIT(15)
  303. #define RG_LCDDS_ISO_EN BIT(13)
  304. #define RG_LCCDS_C_S 4
  305. #define RG_LCCDS_C_M 0x70
  306. #define RG_LCDDS_PCW_NCPO_CHG BIT(3)
  307. #define CORE_PLL_GROUP10 0x409
  308. #define RG_LCDDS_SSC_DELTA_S 0
  309. #define RG_LCDDS_SSC_DELTA_M 0xfff
  310. #define CORE_PLL_GROUP11 0x40a
  311. #define RG_LCDDS_SSC_DELTA1_S 0
  312. #define RG_LCDDS_SSC_DELTA1_M 0xfff
  313. #define CORE_GSWPLL_GRP1 0x40d
  314. #define RG_GSWPLL_POSDIV_200M_S 12
  315. #define RG_GSWPLL_POSDIV_200M_M 0x3000
  316. #define RG_GSWPLL_EN_PRE BIT(11)
  317. #define RG_GSWPLL_FBKDIV_200M_S 0
  318. #define RG_GSWPLL_FBKDIV_200M_M 0xff
  319. #define CORE_GSWPLL_GRP2 0x40e
  320. #define RG_GSWPLL_POSDIV_500M_S 8
  321. #define RG_GSWPLL_POSDIV_500M_M 0x300
  322. #define RG_GSWPLL_FBKDIV_500M_S 0
  323. #define RG_GSWPLL_FBKDIV_500M_M 0xff
  324. #define CORE_TRGMII_GSW_CLK_CG 0x410
  325. #define REG_GSWCK_EN BIT(0)
  326. #define REG_TRGMIICK_EN BIT(1)
  327. /* Extend PHY Control Register 3 */
  328. #define PHY_EXT_REG_14 0x14
  329. /* Fields of PHY_EXT_REG_14 */
  330. #define PHY_EN_DOWN_SHFIT BIT(4)
  331. /* Extend PHY Control Register 4 */
  332. #define PHY_EXT_REG_17 0x17
  333. /* Fields of PHY_EXT_REG_17 */
  334. #define PHY_LINKDOWN_POWER_SAVING_EN BIT(4)
  335. /* PHY RXADC Control Register 7 */
  336. #define PHY_DEV1E_REG_0C6 0x0c6
  337. /* Fields of PHY_DEV1E_REG_0C6 */
  338. #define PHY_POWER_SAVING_S 8
  339. #define PHY_POWER_SAVING_M 0x300
  340. #define PHY_POWER_SAVING_TX 0x0
  341. #endif /* _MTK_ETH_H_ */