mt7628-eth.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * MediaTek ethernet IP driver for U-Boot
  4. *
  5. * Copyright (C) 2018 Stefan Roese <sr@denx.de>
  6. *
  7. * This code is mostly based on the code extracted from this MediaTek
  8. * github repository:
  9. *
  10. * https://github.com/MediaTek-Labs/linkit-smart-uboot.git
  11. *
  12. * I was not able to find a specific license or other developers
  13. * copyrights here, so I can't add them here.
  14. */
  15. #include <common.h>
  16. #include <cpu_func.h>
  17. #include <dm.h>
  18. #include <log.h>
  19. #include <malloc.h>
  20. #include <miiphy.h>
  21. #include <net.h>
  22. #include <reset.h>
  23. #include <wait_bit.h>
  24. #include <asm/cache.h>
  25. #include <asm/io.h>
  26. #include <linux/bitfield.h>
  27. #include <linux/bitops.h>
  28. #include <linux/delay.h>
  29. #include <linux/err.h>
  30. /* Ethernet frame engine register */
  31. #define PDMA_RELATED 0x0800
  32. #define TX_BASE_PTR0 (PDMA_RELATED + 0x000)
  33. #define TX_MAX_CNT0 (PDMA_RELATED + 0x004)
  34. #define TX_CTX_IDX0 (PDMA_RELATED + 0x008)
  35. #define TX_DTX_IDX0 (PDMA_RELATED + 0x00c)
  36. #define RX_BASE_PTR0 (PDMA_RELATED + 0x100)
  37. #define RX_MAX_CNT0 (PDMA_RELATED + 0x104)
  38. #define RX_CALC_IDX0 (PDMA_RELATED + 0x108)
  39. #define PDMA_GLO_CFG (PDMA_RELATED + 0x204)
  40. #define PDMA_RST_IDX (PDMA_RELATED + 0x208)
  41. #define DLY_INT_CFG (PDMA_RELATED + 0x20c)
  42. #define SDM_RELATED 0x0c00
  43. #define SDM_MAC_ADRL (SDM_RELATED + 0x0c) /* MAC address LSB */
  44. #define SDM_MAC_ADRH (SDM_RELATED + 0x10) /* MAC Address MSB */
  45. #define RST_DTX_IDX0 BIT(0)
  46. #define RST_DRX_IDX0 BIT(16)
  47. #define TX_DMA_EN BIT(0)
  48. #define TX_DMA_BUSY BIT(1)
  49. #define RX_DMA_EN BIT(2)
  50. #define RX_DMA_BUSY BIT(3)
  51. #define TX_WB_DDONE BIT(6)
  52. /* Ethernet switch register */
  53. #define MT7628_SWITCH_FCT0 0x0008
  54. #define MT7628_SWITCH_PFC1 0x0014
  55. #define MT7628_SWITCH_PVIDC0 0x0040
  56. #define MT7628_SWITCH_PVIDC1 0x0044
  57. #define MT7628_SWITCH_PVIDC2 0x0048
  58. #define MT7628_SWITCH_PVIDC3 0x004c
  59. #define MT7628_SWITCH_VMSC0 0x0070
  60. #define MT7628_SWITCH_FPA 0x0084
  61. #define MT7628_SWITCH_SOCPC 0x008c
  62. #define MT7628_SWITCH_POC0 0x0090
  63. #define MT7628_SWITCH_POC2 0x0098
  64. #define MT7628_SWITCH_SGC 0x009c
  65. #define MT7628_SWITCH_PCR0 0x00c0
  66. #define PCR0_PHY_ADDR GENMASK(4, 0)
  67. #define PCR0_PHY_REG GENMASK(12, 8)
  68. #define PCR0_WT_PHY_CMD BIT(13)
  69. #define PCR0_RD_PHY_CMD BIT(14)
  70. #define PCR0_WT_DATA GENMASK(31, 16)
  71. #define MT7628_SWITCH_PCR1 0x00c4
  72. #define PCR1_WT_DONE BIT(0)
  73. #define PCR1_RD_RDY BIT(1)
  74. #define PCR1_RD_DATA GENMASK(31, 16)
  75. #define MT7628_SWITCH_FPA1 0x00c8
  76. #define MT7628_SWITCH_FCT2 0x00cc
  77. #define MT7628_SWITCH_SGC2 0x00e4
  78. #define MT7628_SWITCH_BMU_CTRL 0x0110
  79. /* rxd2 */
  80. #define RX_DMA_DONE BIT(31)
  81. #define RX_DMA_LSO BIT(30)
  82. #define RX_DMA_PLEN0 GENMASK(29, 16)
  83. #define RX_DMA_TAG BIT(15)
  84. struct fe_rx_dma {
  85. unsigned int rxd1;
  86. unsigned int rxd2;
  87. unsigned int rxd3;
  88. unsigned int rxd4;
  89. } __packed __aligned(4);
  90. #define TX_DMA_PLEN0 GENMASK(29, 16)
  91. #define TX_DMA_LS1 BIT(14)
  92. #define TX_DMA_LS0 BIT(30)
  93. #define TX_DMA_DONE BIT(31)
  94. #define TX_DMA_INS_VLAN_MT7621 BIT(16)
  95. #define TX_DMA_INS_VLAN BIT(7)
  96. #define TX_DMA_INS_PPPOE BIT(12)
  97. #define TX_DMA_PN GENMASK(26, 24)
  98. struct fe_tx_dma {
  99. unsigned int txd1;
  100. unsigned int txd2;
  101. unsigned int txd3;
  102. unsigned int txd4;
  103. } __packed __aligned(4);
  104. #define NUM_RX_DESC 256
  105. #define NUM_TX_DESC 4
  106. #define NUM_PHYS 5
  107. #define PADDING_LENGTH 60
  108. #define MTK_QDMA_PAGE_SIZE 2048
  109. #define CONFIG_MDIO_TIMEOUT 100
  110. #define CONFIG_DMA_STOP_TIMEOUT 100
  111. #define CONFIG_TX_DMA_TIMEOUT 100
  112. struct mt7628_eth_dev {
  113. void __iomem *base; /* frame engine base address */
  114. void __iomem *eth_sw_base; /* switch base address */
  115. struct mii_dev *bus;
  116. struct fe_tx_dma *tx_ring;
  117. struct fe_rx_dma *rx_ring;
  118. u8 *rx_buf[NUM_RX_DESC];
  119. /* Point to the next RXD DMA wants to use in RXD Ring0 */
  120. int rx_dma_idx;
  121. /* Point to the next TXD in TXD Ring0 CPU wants to use */
  122. int tx_dma_idx;
  123. struct reset_ctl rst_ephy;
  124. struct phy_device *phy;
  125. int wan_port;
  126. };
  127. static int mt7628_eth_free_pkt(struct udevice *dev, uchar *packet, int length);
  128. static int mdio_wait_read(struct mt7628_eth_dev *priv, u32 mask, bool mask_set)
  129. {
  130. void __iomem *base = priv->eth_sw_base;
  131. int ret;
  132. ret = wait_for_bit_le32(base + MT7628_SWITCH_PCR1, mask, mask_set,
  133. CONFIG_MDIO_TIMEOUT, false);
  134. if (ret) {
  135. printf("MDIO operation timeout!\n");
  136. return -ETIMEDOUT;
  137. }
  138. return 0;
  139. }
  140. static int mii_mgr_read(struct mt7628_eth_dev *priv,
  141. u32 phy_addr, u32 phy_register, u32 *read_data)
  142. {
  143. void __iomem *base = priv->eth_sw_base;
  144. u32 status = 0;
  145. u32 ret;
  146. *read_data = 0xffff;
  147. /* Make sure previous read operation is complete */
  148. ret = mdio_wait_read(priv, PCR1_RD_RDY, false);
  149. if (ret)
  150. return ret;
  151. writel(PCR0_RD_PHY_CMD |
  152. FIELD_PREP(PCR0_PHY_REG, phy_register) |
  153. FIELD_PREP(PCR0_PHY_ADDR, phy_addr),
  154. base + MT7628_SWITCH_PCR0);
  155. /* Make sure previous read operation is complete */
  156. ret = mdio_wait_read(priv, PCR1_RD_RDY, true);
  157. if (ret)
  158. return ret;
  159. status = readl(base + MT7628_SWITCH_PCR1);
  160. *read_data = FIELD_GET(PCR1_RD_DATA, status);
  161. return 0;
  162. }
  163. static int mii_mgr_write(struct mt7628_eth_dev *priv,
  164. u32 phy_addr, u32 phy_register, u32 write_data)
  165. {
  166. void __iomem *base = priv->eth_sw_base;
  167. u32 data;
  168. int ret;
  169. /* Make sure previous write operation is complete */
  170. ret = mdio_wait_read(priv, PCR1_WT_DONE, false);
  171. if (ret)
  172. return ret;
  173. data = FIELD_PREP(PCR0_WT_DATA, write_data) |
  174. FIELD_PREP(PCR0_PHY_REG, phy_register) |
  175. FIELD_PREP(PCR0_PHY_ADDR, phy_addr) |
  176. PCR0_WT_PHY_CMD;
  177. writel(data, base + MT7628_SWITCH_PCR0);
  178. return mdio_wait_read(priv, PCR1_WT_DONE, true);
  179. }
  180. static int mt7628_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  181. {
  182. u32 val;
  183. int ret;
  184. ret = mii_mgr_read(bus->priv, addr, reg, &val);
  185. if (ret)
  186. return ret;
  187. return val;
  188. }
  189. static int mt7628_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  190. u16 value)
  191. {
  192. return mii_mgr_write(bus->priv, addr, reg, value);
  193. }
  194. static void mt7628_ephy_init(struct mt7628_eth_dev *priv)
  195. {
  196. int i;
  197. mii_mgr_write(priv, 0, 31, 0x2000); /* change G2 page */
  198. mii_mgr_write(priv, 0, 26, 0x0000);
  199. for (i = 0; i < 5; i++) {
  200. mii_mgr_write(priv, i, 31, 0x8000); /* change L0 page */
  201. mii_mgr_write(priv, i, 0, 0x3100);
  202. /* EEE disable */
  203. mii_mgr_write(priv, i, 30, 0xa000);
  204. mii_mgr_write(priv, i, 31, 0xa000); /* change L2 page */
  205. mii_mgr_write(priv, i, 16, 0x0606);
  206. mii_mgr_write(priv, i, 23, 0x0f0e);
  207. mii_mgr_write(priv, i, 24, 0x1610);
  208. mii_mgr_write(priv, i, 30, 0x1f15);
  209. mii_mgr_write(priv, i, 28, 0x6111);
  210. }
  211. /* 100Base AOI setting */
  212. mii_mgr_write(priv, 0, 31, 0x5000); /* change G5 page */
  213. mii_mgr_write(priv, 0, 19, 0x004a);
  214. mii_mgr_write(priv, 0, 20, 0x015a);
  215. mii_mgr_write(priv, 0, 21, 0x00ee);
  216. mii_mgr_write(priv, 0, 22, 0x0033);
  217. mii_mgr_write(priv, 0, 23, 0x020a);
  218. mii_mgr_write(priv, 0, 24, 0x0000);
  219. mii_mgr_write(priv, 0, 25, 0x024a);
  220. mii_mgr_write(priv, 0, 26, 0x035a);
  221. mii_mgr_write(priv, 0, 27, 0x02ee);
  222. mii_mgr_write(priv, 0, 28, 0x0233);
  223. mii_mgr_write(priv, 0, 29, 0x000a);
  224. mii_mgr_write(priv, 0, 30, 0x0000);
  225. /* Fix EPHY idle state abnormal behavior */
  226. mii_mgr_write(priv, 0, 31, 0x4000); /* change G4 page */
  227. mii_mgr_write(priv, 0, 29, 0x000d);
  228. mii_mgr_write(priv, 0, 30, 0x0500);
  229. }
  230. static void rt305x_esw_init(struct mt7628_eth_dev *priv)
  231. {
  232. void __iomem *base = priv->eth_sw_base;
  233. void __iomem *reg;
  234. u32 val = 0, pvid;
  235. int i;
  236. /*
  237. * FC_RLS_TH=200, FC_SET_TH=160
  238. * DROP_RLS=120, DROP_SET_TH=80
  239. */
  240. writel(0xc8a07850, base + MT7628_SWITCH_FCT0);
  241. writel(0x00000000, base + MT7628_SWITCH_SGC2);
  242. writel(0x00405555, base + MT7628_SWITCH_PFC1);
  243. writel(0x00007f7f, base + MT7628_SWITCH_POC0);
  244. writel(0x00007f7f, base + MT7628_SWITCH_POC2); /* disable VLAN */
  245. writel(0x0002500c, base + MT7628_SWITCH_FCT2);
  246. /* hashing algorithm=XOR48, aging interval=300sec */
  247. writel(0x0008a301, base + MT7628_SWITCH_SGC);
  248. writel(0x02404040, base + MT7628_SWITCH_SOCPC);
  249. /* Ext PHY Addr=0x1f */
  250. writel(0x3f502b28, base + MT7628_SWITCH_FPA1);
  251. writel(0x00000000, base + MT7628_SWITCH_FPA);
  252. /* 1us cycle number=125 (FE's clock=125Mhz) */
  253. writel(0x7d000000, base + MT7628_SWITCH_BMU_CTRL);
  254. /* LAN/WAN partition, WAN port will be unusable in u-boot network */
  255. if (priv->wan_port >= 0 && priv->wan_port < 6) {
  256. for (i = 0; i < 8; i++) {
  257. pvid = i == priv->wan_port ? 2 : 1;
  258. reg = base + MT7628_SWITCH_PVIDC0 + (i / 2) * 4;
  259. if (i % 2 == 0) {
  260. val = pvid;
  261. } else {
  262. val |= (pvid << 12);
  263. writel(val, reg);
  264. }
  265. }
  266. val = 0xffff407f;
  267. val |= 1 << (8 + priv->wan_port);
  268. val &= ~(1 << priv->wan_port);
  269. writel(val, base + MT7628_SWITCH_VMSC0);
  270. }
  271. /* Reset PHY */
  272. reset_assert(&priv->rst_ephy);
  273. reset_deassert(&priv->rst_ephy);
  274. mdelay(10);
  275. mt7628_ephy_init(priv);
  276. }
  277. static void eth_dma_start(struct mt7628_eth_dev *priv)
  278. {
  279. void __iomem *base = priv->base;
  280. setbits_le32(base + PDMA_GLO_CFG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
  281. }
  282. static void eth_dma_stop(struct mt7628_eth_dev *priv)
  283. {
  284. void __iomem *base = priv->base;
  285. int ret;
  286. clrbits_le32(base + PDMA_GLO_CFG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
  287. /* Wait for DMA to stop */
  288. ret = wait_for_bit_le32(base + PDMA_GLO_CFG,
  289. RX_DMA_BUSY | TX_DMA_BUSY, false,
  290. CONFIG_DMA_STOP_TIMEOUT, false);
  291. if (ret)
  292. printf("DMA stop timeout error!\n");
  293. }
  294. static int mt7628_eth_write_hwaddr(struct udevice *dev)
  295. {
  296. struct mt7628_eth_dev *priv = dev_get_priv(dev);
  297. void __iomem *base = priv->base;
  298. u8 *addr = ((struct eth_pdata *)dev_get_plat(dev))->enetaddr;
  299. u32 val;
  300. /* Set MAC address. */
  301. val = addr[0];
  302. val = (val << 8) | addr[1];
  303. writel(val, base + SDM_MAC_ADRH);
  304. val = addr[2];
  305. val = (val << 8) | addr[3];
  306. val = (val << 8) | addr[4];
  307. val = (val << 8) | addr[5];
  308. writel(val, base + SDM_MAC_ADRL);
  309. return 0;
  310. }
  311. static int mt7628_eth_send(struct udevice *dev, void *packet, int length)
  312. {
  313. struct mt7628_eth_dev *priv = dev_get_priv(dev);
  314. void __iomem *base = priv->base;
  315. int ret;
  316. int idx;
  317. int i;
  318. idx = priv->tx_dma_idx;
  319. /* Pad message to a minimum length */
  320. if (length < PADDING_LENGTH) {
  321. char *p = (char *)packet;
  322. for (i = 0; i < PADDING_LENGTH - length; i++)
  323. p[length + i] = 0;
  324. length = PADDING_LENGTH;
  325. }
  326. /* Check if buffer is ready for next TX DMA */
  327. ret = wait_for_bit_le32(&priv->tx_ring[idx].txd2, TX_DMA_DONE, true,
  328. CONFIG_TX_DMA_TIMEOUT, false);
  329. if (ret) {
  330. printf("TX: DMA still busy on buffer %d\n", idx);
  331. return ret;
  332. }
  333. flush_dcache_range((u32)packet, (u32)packet + length);
  334. priv->tx_ring[idx].txd1 = CPHYSADDR(packet);
  335. priv->tx_ring[idx].txd2 &= ~TX_DMA_PLEN0;
  336. priv->tx_ring[idx].txd2 |= FIELD_PREP(TX_DMA_PLEN0, length);
  337. priv->tx_ring[idx].txd2 &= ~TX_DMA_DONE;
  338. idx = (idx + 1) % NUM_TX_DESC;
  339. /* Make sure the writes executed at this place */
  340. wmb();
  341. writel(idx, base + TX_CTX_IDX0);
  342. priv->tx_dma_idx = idx;
  343. return 0;
  344. }
  345. static int mt7628_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  346. {
  347. struct mt7628_eth_dev *priv = dev_get_priv(dev);
  348. u32 rxd_info;
  349. int length;
  350. int idx;
  351. idx = priv->rx_dma_idx;
  352. rxd_info = priv->rx_ring[idx].rxd2;
  353. if ((rxd_info & RX_DMA_DONE) == 0)
  354. return -EAGAIN;
  355. length = FIELD_GET(RX_DMA_PLEN0, priv->rx_ring[idx].rxd2);
  356. if (length == 0 || length > MTK_QDMA_PAGE_SIZE) {
  357. printf("%s: invalid length (%d bytes)\n", __func__, length);
  358. mt7628_eth_free_pkt(dev, NULL, 0);
  359. return -EIO;
  360. }
  361. *packetp = priv->rx_buf[idx];
  362. invalidate_dcache_range((u32)*packetp, (u32)*packetp + length);
  363. priv->rx_ring[idx].rxd4 = 0;
  364. priv->rx_ring[idx].rxd2 = RX_DMA_LSO;
  365. /* Make sure the writes executed at this place */
  366. wmb();
  367. return length;
  368. }
  369. static int mt7628_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
  370. {
  371. struct mt7628_eth_dev *priv = dev_get_priv(dev);
  372. void __iomem *base = priv->base;
  373. int idx;
  374. idx = priv->rx_dma_idx;
  375. /* Move point to next RXD which wants to alloc */
  376. writel(idx, base + RX_CALC_IDX0);
  377. /* Update to Next packet point that was received */
  378. idx = (idx + 1) % NUM_RX_DESC;
  379. priv->rx_dma_idx = idx;
  380. return 0;
  381. }
  382. static int mt7628_eth_start(struct udevice *dev)
  383. {
  384. struct mt7628_eth_dev *priv = dev_get_priv(dev);
  385. void __iomem *base = priv->base;
  386. uchar packet[MTK_QDMA_PAGE_SIZE];
  387. uchar *packetp;
  388. int ret;
  389. int i;
  390. for (i = 0; i < NUM_RX_DESC; i++) {
  391. memset((void *)&priv->rx_ring[i], 0, sizeof(priv->rx_ring[0]));
  392. priv->rx_ring[i].rxd2 |= RX_DMA_LSO;
  393. priv->rx_ring[i].rxd1 = CPHYSADDR(priv->rx_buf[i]);
  394. }
  395. for (i = 0; i < NUM_TX_DESC; i++) {
  396. memset((void *)&priv->tx_ring[i], 0, sizeof(priv->tx_ring[0]));
  397. priv->tx_ring[i].txd2 = TX_DMA_LS0 | TX_DMA_DONE;
  398. priv->tx_ring[i].txd4 = FIELD_PREP(TX_DMA_PN, 1);
  399. }
  400. priv->rx_dma_idx = 0;
  401. priv->tx_dma_idx = 0;
  402. /* Make sure the writes executed at this place */
  403. wmb();
  404. /* disable delay interrupt */
  405. writel(0, base + DLY_INT_CFG);
  406. clrbits_le32(base + PDMA_GLO_CFG, 0xffff0000);
  407. /* Tell the adapter where the TX/RX rings are located. */
  408. writel(CPHYSADDR(&priv->rx_ring[0]), base + RX_BASE_PTR0);
  409. writel(CPHYSADDR((u32)&priv->tx_ring[0]), base + TX_BASE_PTR0);
  410. writel(NUM_RX_DESC, base + RX_MAX_CNT0);
  411. writel(NUM_TX_DESC, base + TX_MAX_CNT0);
  412. writel(priv->tx_dma_idx, base + TX_CTX_IDX0);
  413. writel(RST_DTX_IDX0, base + PDMA_RST_IDX);
  414. writel(NUM_RX_DESC - 1, base + RX_CALC_IDX0);
  415. writel(RST_DRX_IDX0, base + PDMA_RST_IDX);
  416. /* Make sure the writes executed at this place */
  417. wmb();
  418. eth_dma_start(priv);
  419. if (priv->phy) {
  420. ret = phy_startup(priv->phy);
  421. if (ret)
  422. return ret;
  423. if (!priv->phy->link)
  424. return -EAGAIN;
  425. }
  426. /*
  427. * The integrated switch seems to queue some received ethernet
  428. * packets in some FIFO. Lets read the already queued packets
  429. * out by using the receive routine, so that these old messages
  430. * are dropped before the new xfer starts.
  431. */
  432. packetp = &packet[0];
  433. while (mt7628_eth_recv(dev, 0, &packetp) != -EAGAIN)
  434. mt7628_eth_free_pkt(dev, packetp, 0);
  435. return 0;
  436. }
  437. static void mt7628_eth_stop(struct udevice *dev)
  438. {
  439. struct mt7628_eth_dev *priv = dev_get_priv(dev);
  440. eth_dma_stop(priv);
  441. }
  442. static int mt7628_eth_probe(struct udevice *dev)
  443. {
  444. struct mt7628_eth_dev *priv = dev_get_priv(dev);
  445. struct mii_dev *bus;
  446. int poll_link_phy;
  447. int ret;
  448. int i;
  449. /* Save frame-engine base address for later use */
  450. priv->base = dev_remap_addr_index(dev, 0);
  451. if (IS_ERR(priv->base))
  452. return PTR_ERR(priv->base);
  453. /* Save switch base address for later use */
  454. priv->eth_sw_base = dev_remap_addr_index(dev, 1);
  455. if (IS_ERR(priv->eth_sw_base))
  456. return PTR_ERR(priv->eth_sw_base);
  457. /* Reset controller */
  458. ret = reset_get_by_name(dev, "ephy", &priv->rst_ephy);
  459. if (ret) {
  460. pr_err("unable to find reset controller for ethernet PHYs\n");
  461. return ret;
  462. }
  463. /* WAN port will be isolated from LAN ports */
  464. priv->wan_port = dev_read_u32_default(dev, "mediatek,wan-port", -1);
  465. /* Put rx and tx rings into KSEG1 area (uncached) */
  466. priv->tx_ring = (struct fe_tx_dma *)
  467. KSEG1ADDR(memalign(ARCH_DMA_MINALIGN,
  468. sizeof(*priv->tx_ring) * NUM_TX_DESC));
  469. priv->rx_ring = (struct fe_rx_dma *)
  470. KSEG1ADDR(memalign(ARCH_DMA_MINALIGN,
  471. sizeof(*priv->rx_ring) * NUM_RX_DESC));
  472. for (i = 0; i < NUM_RX_DESC; i++)
  473. priv->rx_buf[i] = memalign(PKTALIGN, MTK_QDMA_PAGE_SIZE);
  474. bus = mdio_alloc();
  475. if (!bus) {
  476. printf("Failed to allocate MDIO bus\n");
  477. return -ENOMEM;
  478. }
  479. bus->read = mt7628_mdio_read;
  480. bus->write = mt7628_mdio_write;
  481. snprintf(bus->name, sizeof(bus->name), dev->name);
  482. bus->priv = (void *)priv;
  483. ret = mdio_register(bus);
  484. if (ret)
  485. return ret;
  486. poll_link_phy = dev_read_u32_default(dev, "mediatek,poll-link-phy", -1);
  487. if (poll_link_phy >= 0) {
  488. if (poll_link_phy >= NUM_PHYS) {
  489. pr_err("invalid phy %d for poll-link-phy\n",
  490. poll_link_phy);
  491. return ret;
  492. }
  493. priv->phy = phy_connect(bus, poll_link_phy, dev,
  494. PHY_INTERFACE_MODE_MII);
  495. if (!priv->phy) {
  496. pr_err("failed to probe phy %d\n", poll_link_phy);
  497. return -ENODEV;
  498. }
  499. priv->phy->advertising = priv->phy->supported;
  500. phy_config(priv->phy);
  501. }
  502. /* Switch configuration */
  503. rt305x_esw_init(priv);
  504. return 0;
  505. }
  506. static const struct eth_ops mt7628_eth_ops = {
  507. .start = mt7628_eth_start,
  508. .send = mt7628_eth_send,
  509. .recv = mt7628_eth_recv,
  510. .free_pkt = mt7628_eth_free_pkt,
  511. .stop = mt7628_eth_stop,
  512. .write_hwaddr = mt7628_eth_write_hwaddr,
  513. };
  514. static const struct udevice_id mt7628_eth_ids[] = {
  515. { .compatible = "mediatek,mt7628-eth" },
  516. { }
  517. };
  518. U_BOOT_DRIVER(mt7628_eth) = {
  519. .name = "mt7628_eth",
  520. .id = UCLASS_ETH,
  521. .of_match = mt7628_eth_ids,
  522. .probe = mt7628_eth_probe,
  523. .ops = &mt7628_eth_ops,
  524. .priv_auto = sizeof(struct mt7628_eth_dev),
  525. .plat_auto = sizeof(struct eth_pdata),
  526. };