mcfmii.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  4. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  5. */
  6. #include <common.h>
  7. #include <config.h>
  8. #include <net.h>
  9. #include <netdev.h>
  10. #include <asm/global_data.h>
  11. #include <linux/delay.h>
  12. #include <asm/fec.h>
  13. #include <asm/immap.h>
  14. #include <linux/mii.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. #if defined(CONFIG_CMD_NET)
  17. #undef MII_DEBUG
  18. #undef ET_DEBUG
  19. /*extern int fecpin_setclear(struct eth_device *dev, int setclear);*/
  20. #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
  21. #include <miiphy.h>
  22. /* Make MII read/write commands for the FEC. */
  23. #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
  24. (REG & 0x1f) << 18))
  25. #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
  26. (REG & 0x1f) << 18) | (VAL & 0xffff))
  27. #ifndef CONFIG_SYS_UNSPEC_PHYID
  28. # define CONFIG_SYS_UNSPEC_PHYID 0
  29. #endif
  30. #ifndef CONFIG_SYS_UNSPEC_STRID
  31. # define CONFIG_SYS_UNSPEC_STRID 0
  32. #endif
  33. typedef struct phy_info_struct {
  34. u32 phyid;
  35. char *strid;
  36. } phy_info_t;
  37. phy_info_t phyinfo[] = {
  38. {0x0022561B, "AMD79C784VC"}, /* AMD 79C784VC */
  39. {0x00406322, "BCM5222"}, /* Broadcom 5222 */
  40. {0x02a80150, "Intel82555"}, /* Intel 82555 */
  41. {0x0016f870, "LSI80225"}, /* LSI 80225 */
  42. {0x0016f880, "LSI80225/B"}, /* LSI 80225/B */
  43. {0x78100000, "LXT970"}, /* LXT970 */
  44. {0x001378e0, "LXT971"}, /* LXT971 and 972 */
  45. {0x00221619, "KS8721BL"}, /* Micrel KS8721BL/SL */
  46. {0x00221512, "KSZ8041NL"}, /* Micrel KSZ8041NL */
  47. {0x20005CE1, "N83640"}, /* National 83640 */
  48. {0x20005C90, "N83848"}, /* National 83848 */
  49. {0x20005CA2, "N83849"}, /* National 83849 */
  50. {0x01814400, "QS6612"}, /* QS6612 */
  51. #if defined(CONFIG_SYS_UNSPEC_PHYID) && defined(CONFIG_SYS_UNSPEC_STRID)
  52. {CONFIG_SYS_UNSPEC_PHYID, CONFIG_SYS_UNSPEC_STRID},
  53. #endif
  54. {0, 0}
  55. };
  56. /*
  57. * mii_init -- Initialize the MII for MII command without ethernet
  58. * This function is a subset of eth_init
  59. */
  60. void mii_reset(fec_info_t *info)
  61. {
  62. volatile FEC_T *fecp = (FEC_T *) (info->miibase);
  63. int i;
  64. fecp->ecr = FEC_ECR_RESET;
  65. for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
  66. udelay(1);
  67. }
  68. if (i == FEC_RESET_DELAY)
  69. printf("FEC_RESET_DELAY timeout\n");
  70. }
  71. /* send command to phy using mii, wait for result */
  72. uint mii_send(uint mii_cmd)
  73. {
  74. #ifdef CONFIG_DM_ETH
  75. struct udevice *dev;
  76. #else
  77. struct eth_device *dev;
  78. #endif
  79. fec_info_t *info;
  80. volatile FEC_T *ep;
  81. uint mii_reply;
  82. int j = 0;
  83. /* retrieve from register structure */
  84. dev = eth_get_dev();
  85. #ifdef CONFIG_DM_ETH
  86. info = dev_get_priv(dev);
  87. #else
  88. info = dev->priv;
  89. #endif
  90. ep = (FEC_T *) info->miibase;
  91. ep->mmfr = mii_cmd; /* command to phy */
  92. /* wait for mii complete */
  93. while (!(ep->eir & FEC_EIR_MII) && (j < info->to_loop)) {
  94. udelay(1);
  95. j++;
  96. }
  97. if (j >= info->to_loop) {
  98. printf("MII not complete\n");
  99. return -1;
  100. }
  101. mii_reply = ep->mmfr; /* result from phy */
  102. ep->eir = FEC_EIR_MII; /* clear MII complete */
  103. #ifdef ET_DEBUG
  104. printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
  105. __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
  106. #endif
  107. return (mii_reply & 0xffff); /* data read from phy */
  108. }
  109. #endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
  110. #if defined(CONFIG_SYS_DISCOVER_PHY)
  111. int mii_discover_phy(fec_info_t *info)
  112. {
  113. #define MAX_PHY_PASSES 11
  114. int phyaddr, pass;
  115. uint phyno, phytype;
  116. int i, found = 0;
  117. if (info->phyname_init)
  118. return info->phy_addr;
  119. phyaddr = -1; /* didn't find a PHY yet */
  120. for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
  121. if (pass > 1) {
  122. /* PHY may need more time to recover from reset.
  123. * The LXT970 needs 50ms typical, no maximum is
  124. * specified, so wait 10ms before try again.
  125. * With 11 passes this gives it 100ms to wake up.
  126. */
  127. udelay(10000); /* wait 10ms */
  128. }
  129. for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
  130. phytype = mii_send(mk_mii_read(phyno, MII_PHYSID1));
  131. #ifdef ET_DEBUG
  132. printf("PHY type 0x%x pass %d\n", phytype, pass);
  133. #endif
  134. if (phytype == 0xffff)
  135. continue;
  136. phyaddr = phyno;
  137. phytype <<= 16;
  138. phytype |=
  139. mii_send(mk_mii_read(phyno, MII_PHYSID2));
  140. #ifdef ET_DEBUG
  141. printf("PHY @ 0x%x pass %d\n", phyno, pass);
  142. #endif
  143. for (i = 0; (i < ARRAY_SIZE(phyinfo))
  144. && (phyinfo[i].phyid != 0); i++) {
  145. if (phyinfo[i].phyid == phytype) {
  146. #ifdef ET_DEBUG
  147. printf("phyid %x - %s\n",
  148. phyinfo[i].phyid,
  149. phyinfo[i].strid);
  150. #endif
  151. strcpy(info->phy_name, phyinfo[i].strid);
  152. info->phyname_init = 1;
  153. found = 1;
  154. break;
  155. }
  156. }
  157. if (!found) {
  158. #ifdef ET_DEBUG
  159. printf("0x%08x\n", phytype);
  160. #endif
  161. strcpy(info->phy_name, "unknown");
  162. info->phyname_init = 1;
  163. break;
  164. }
  165. }
  166. }
  167. if (phyaddr < 0)
  168. printf("No PHY device found.\n");
  169. return phyaddr;
  170. }
  171. #endif /* CONFIG_SYS_DISCOVER_PHY */
  172. void mii_init(void) __attribute__((weak,alias("__mii_init")));
  173. void __mii_init(void)
  174. {
  175. #ifdef CONFIG_DM_ETH
  176. struct udevice *dev;
  177. #else
  178. struct eth_device *dev;
  179. #endif
  180. fec_info_t *info;
  181. volatile FEC_T *fecp;
  182. int miispd = 0, i = 0;
  183. u16 status = 0;
  184. u16 linkgood = 0;
  185. /* retrieve from register structure */
  186. dev = eth_get_dev();
  187. #ifdef CONFIG_DM_ETH
  188. info = dev_get_priv(dev);
  189. #else
  190. info = dev->priv;
  191. #endif
  192. fecp = (FEC_T *) info->miibase;
  193. fecpin_setclear(info, 1);
  194. mii_reset(info);
  195. /* We use strictly polling mode only */
  196. fecp->eimr = 0;
  197. /* Clear any pending interrupt */
  198. fecp->eir = 0xffffffff;
  199. /* Set MII speed */
  200. miispd = (gd->bus_clk / 1000000) / 5;
  201. fecp->mscr = miispd << 1;
  202. #ifdef CONFIG_SYS_DISCOVER_PHY
  203. info->phy_addr = mii_discover_phy(info);
  204. #endif
  205. if (info->phy_addr == -1)
  206. return;
  207. while (i < info->to_loop) {
  208. status = 0;
  209. i++;
  210. /* Read PHY control register */
  211. miiphy_read(dev->name, info->phy_addr, MII_BMCR, &status);
  212. /* If phy set to autonegotiate, wait for autonegotiation done,
  213. * if phy is not autonegotiating, just wait for link up.
  214. */
  215. if ((status & BMCR_ANENABLE) == BMCR_ANENABLE) {
  216. linkgood = (BMSR_ANEGCOMPLETE | BMSR_LSTATUS);
  217. } else {
  218. linkgood = BMSR_LSTATUS;
  219. }
  220. /* Read PHY status register */
  221. miiphy_read(dev->name, info->phy_addr, MII_BMSR, &status);
  222. if ((status & linkgood) == linkgood)
  223. break;
  224. udelay(1);
  225. }
  226. if (i >= info->to_loop)
  227. printf("Link UP timeout\n");
  228. /* adapt to the duplex and speed settings of the phy */
  229. info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
  230. info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
  231. }
  232. /*
  233. * Read and write a MII PHY register, routines used by MII Utilities
  234. *
  235. * FIXME: These routines are expected to return 0 on success, but mii_send
  236. * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
  237. * no PHY connected...
  238. * For now always return 0.
  239. * FIXME: These routines only work after calling eth_init() at least once!
  240. * Otherwise they hang in mii_send() !!! Sorry!
  241. */
  242. int mcffec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
  243. {
  244. short rdreg; /* register working value */
  245. #ifdef MII_DEBUG
  246. printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
  247. #endif
  248. rdreg = mii_send(mk_mii_read(addr, reg));
  249. #ifdef MII_DEBUG
  250. printf("0x%04x\n", rdreg);
  251. #endif
  252. return rdreg;
  253. }
  254. int mcffec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
  255. u16 value)
  256. {
  257. #ifdef MII_DEBUG
  258. printf("miiphy_write(0x%x) @ 0x%x = 0x%04x\n", reg, addr, value);
  259. #endif
  260. mii_send(mk_mii_write(addr, reg, value));
  261. return 0;
  262. }
  263. #endif /* CONFIG_CMD_NET */