macb.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2005-2006 Atmel Corporation
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <log.h>
  10. #include <asm/global_data.h>
  11. #include <linux/delay.h>
  12. /*
  13. * The u-boot networking stack is a little weird. It seems like the
  14. * networking core allocates receive buffers up front without any
  15. * regard to the hardware that's supposed to actually receive those
  16. * packets.
  17. *
  18. * The MACB receives packets into 128-byte receive buffers, so the
  19. * buffers allocated by the core isn't very practical to use. We'll
  20. * allocate our own, but we need one such buffer in case a packet
  21. * wraps around the DMA ring so that we have to copy it.
  22. *
  23. * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
  24. * configuration header. This way, the core allocates one RX buffer
  25. * and one TX buffer, each of which can hold a ethernet packet of
  26. * maximum size.
  27. *
  28. * For some reason, the networking core unconditionally specifies a
  29. * 32-byte packet "alignment" (which really should be called
  30. * "padding"). MACB shouldn't need that, but we'll refrain from any
  31. * core modifications here...
  32. */
  33. #include <net.h>
  34. #ifndef CONFIG_DM_ETH
  35. #include <netdev.h>
  36. #endif
  37. #include <malloc.h>
  38. #include <miiphy.h>
  39. #include <linux/mii.h>
  40. #include <asm/io.h>
  41. #include <linux/dma-mapping.h>
  42. #include <asm/arch/clk.h>
  43. #include <linux/errno.h>
  44. #include "macb.h"
  45. DECLARE_GLOBAL_DATA_PTR;
  46. /*
  47. * These buffer sizes must be power of 2 and divisible
  48. * by RX_BUFFER_MULTIPLE
  49. */
  50. #define MACB_RX_BUFFER_SIZE 128
  51. #define GEM_RX_BUFFER_SIZE 2048
  52. #define RX_BUFFER_MULTIPLE 64
  53. #define MACB_RX_RING_SIZE 32
  54. #define MACB_TX_RING_SIZE 16
  55. #define MACB_TX_TIMEOUT 1000
  56. #define MACB_AUTONEG_TIMEOUT 5000000
  57. #ifdef CONFIG_MACB_ZYNQ
  58. /* INCR4 AHB bursts */
  59. #define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004
  60. /* Use full configured addressable space (8 Kb) */
  61. #define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300
  62. /* Use full configured addressable space (4 Kb) */
  63. #define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400
  64. /* Set RXBUF with use of 128 byte */
  65. #define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000
  66. #define MACB_ZYNQ_GEM_DMACR_INIT \
  67. (MACB_ZYNQ_GEM_DMACR_BLENGTH | \
  68. MACB_ZYNQ_GEM_DMACR_RXSIZE | \
  69. MACB_ZYNQ_GEM_DMACR_TXSIZE | \
  70. MACB_ZYNQ_GEM_DMACR_RXBUF)
  71. #endif
  72. struct macb_dma_desc {
  73. u32 addr;
  74. u32 ctrl;
  75. };
  76. struct macb_dma_desc_64 {
  77. u32 addrh;
  78. u32 unused;
  79. };
  80. #define HW_DMA_CAP_32B 0
  81. #define HW_DMA_CAP_64B 1
  82. #define DMA_DESC_SIZE 16
  83. #define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
  84. #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
  85. #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
  86. #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
  87. #define RXBUF_FRMLEN_MASK 0x00000fff
  88. #define TXBUF_FRMLEN_MASK 0x000007ff
  89. struct macb_device {
  90. void *regs;
  91. bool is_big_endian;
  92. const struct macb_config *config;
  93. unsigned int rx_tail;
  94. unsigned int tx_head;
  95. unsigned int tx_tail;
  96. unsigned int next_rx_tail;
  97. bool wrapped;
  98. void *rx_buffer;
  99. void *tx_buffer;
  100. struct macb_dma_desc *rx_ring;
  101. struct macb_dma_desc *tx_ring;
  102. size_t rx_buffer_size;
  103. unsigned long rx_buffer_dma;
  104. unsigned long rx_ring_dma;
  105. unsigned long tx_ring_dma;
  106. struct macb_dma_desc *dummy_desc;
  107. unsigned long dummy_desc_dma;
  108. const struct device *dev;
  109. #ifndef CONFIG_DM_ETH
  110. struct eth_device netdev;
  111. #endif
  112. unsigned short phy_addr;
  113. struct mii_dev *bus;
  114. #ifdef CONFIG_PHYLIB
  115. struct phy_device *phydev;
  116. #endif
  117. #ifdef CONFIG_DM_ETH
  118. #ifdef CONFIG_CLK
  119. unsigned long pclk_rate;
  120. #endif
  121. phy_interface_t phy_interface;
  122. #endif
  123. };
  124. struct macb_usrio_cfg {
  125. unsigned int mii;
  126. unsigned int rmii;
  127. unsigned int rgmii;
  128. unsigned int clken;
  129. };
  130. struct macb_config {
  131. unsigned int dma_burst_length;
  132. unsigned int hw_dma_cap;
  133. unsigned int caps;
  134. int (*clk_init)(struct udevice *dev, ulong rate);
  135. const struct macb_usrio_cfg *usrio;
  136. };
  137. #ifndef CONFIG_DM_ETH
  138. #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
  139. #endif
  140. static int macb_is_gem(struct macb_device *macb)
  141. {
  142. return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
  143. }
  144. #ifndef cpu_is_sama5d2
  145. #define cpu_is_sama5d2() 0
  146. #endif
  147. #ifndef cpu_is_sama5d4
  148. #define cpu_is_sama5d4() 0
  149. #endif
  150. static int gem_is_gigabit_capable(struct macb_device *macb)
  151. {
  152. /*
  153. * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
  154. * configured to support only 10/100.
  155. */
  156. return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
  157. }
  158. static void macb_mdio_write(struct macb_device *macb, u8 phy_adr, u8 reg,
  159. u16 value)
  160. {
  161. unsigned long netctl;
  162. unsigned long netstat;
  163. unsigned long frame;
  164. netctl = macb_readl(macb, NCR);
  165. netctl |= MACB_BIT(MPE);
  166. macb_writel(macb, NCR, netctl);
  167. frame = (MACB_BF(SOF, 1)
  168. | MACB_BF(RW, 1)
  169. | MACB_BF(PHYA, phy_adr)
  170. | MACB_BF(REGA, reg)
  171. | MACB_BF(CODE, 2)
  172. | MACB_BF(DATA, value));
  173. macb_writel(macb, MAN, frame);
  174. do {
  175. netstat = macb_readl(macb, NSR);
  176. } while (!(netstat & MACB_BIT(IDLE)));
  177. netctl = macb_readl(macb, NCR);
  178. netctl &= ~MACB_BIT(MPE);
  179. macb_writel(macb, NCR, netctl);
  180. }
  181. static u16 macb_mdio_read(struct macb_device *macb, u8 phy_adr, u8 reg)
  182. {
  183. unsigned long netctl;
  184. unsigned long netstat;
  185. unsigned long frame;
  186. netctl = macb_readl(macb, NCR);
  187. netctl |= MACB_BIT(MPE);
  188. macb_writel(macb, NCR, netctl);
  189. frame = (MACB_BF(SOF, 1)
  190. | MACB_BF(RW, 2)
  191. | MACB_BF(PHYA, phy_adr)
  192. | MACB_BF(REGA, reg)
  193. | MACB_BF(CODE, 2));
  194. macb_writel(macb, MAN, frame);
  195. do {
  196. netstat = macb_readl(macb, NSR);
  197. } while (!(netstat & MACB_BIT(IDLE)));
  198. frame = macb_readl(macb, MAN);
  199. netctl = macb_readl(macb, NCR);
  200. netctl &= ~MACB_BIT(MPE);
  201. macb_writel(macb, NCR, netctl);
  202. return MACB_BFEXT(DATA, frame);
  203. }
  204. void __weak arch_get_mdio_control(const char *name)
  205. {
  206. return;
  207. }
  208. #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
  209. int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
  210. {
  211. u16 value = 0;
  212. #ifdef CONFIG_DM_ETH
  213. struct udevice *dev = eth_get_dev_by_name(bus->name);
  214. struct macb_device *macb = dev_get_priv(dev);
  215. #else
  216. struct eth_device *dev = eth_get_dev_by_name(bus->name);
  217. struct macb_device *macb = to_macb(dev);
  218. #endif
  219. arch_get_mdio_control(bus->name);
  220. value = macb_mdio_read(macb, phy_adr, reg);
  221. return value;
  222. }
  223. int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
  224. u16 value)
  225. {
  226. #ifdef CONFIG_DM_ETH
  227. struct udevice *dev = eth_get_dev_by_name(bus->name);
  228. struct macb_device *macb = dev_get_priv(dev);
  229. #else
  230. struct eth_device *dev = eth_get_dev_by_name(bus->name);
  231. struct macb_device *macb = to_macb(dev);
  232. #endif
  233. arch_get_mdio_control(bus->name);
  234. macb_mdio_write(macb, phy_adr, reg, value);
  235. return 0;
  236. }
  237. #endif
  238. #define RX 1
  239. #define TX 0
  240. static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
  241. {
  242. if (rx)
  243. invalidate_dcache_range(macb->rx_ring_dma,
  244. ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
  245. PKTALIGN));
  246. else
  247. invalidate_dcache_range(macb->tx_ring_dma,
  248. ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
  249. PKTALIGN));
  250. }
  251. static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
  252. {
  253. if (rx)
  254. flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
  255. ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
  256. else
  257. flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
  258. ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
  259. }
  260. static inline void macb_flush_rx_buffer(struct macb_device *macb)
  261. {
  262. flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
  263. ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
  264. PKTALIGN));
  265. }
  266. static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
  267. {
  268. invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
  269. ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
  270. PKTALIGN));
  271. }
  272. #if defined(CONFIG_CMD_NET)
  273. static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc *desc)
  274. {
  275. return (struct macb_dma_desc_64 *)((void *)desc
  276. + sizeof(struct macb_dma_desc));
  277. }
  278. static void macb_set_addr(struct macb_device *macb, struct macb_dma_desc *desc,
  279. ulong addr)
  280. {
  281. struct macb_dma_desc_64 *desc_64;
  282. if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
  283. desc_64 = macb_64b_desc(desc);
  284. desc_64->addrh = upper_32_bits(addr);
  285. }
  286. desc->addr = lower_32_bits(addr);
  287. }
  288. static int _macb_send(struct macb_device *macb, const char *name, void *packet,
  289. int length)
  290. {
  291. unsigned long paddr, ctrl;
  292. unsigned int tx_head = macb->tx_head;
  293. int i;
  294. paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
  295. ctrl = length & TXBUF_FRMLEN_MASK;
  296. ctrl |= MACB_BIT(TX_LAST);
  297. if (tx_head == (MACB_TX_RING_SIZE - 1)) {
  298. ctrl |= MACB_BIT(TX_WRAP);
  299. macb->tx_head = 0;
  300. } else {
  301. macb->tx_head++;
  302. }
  303. if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
  304. tx_head = tx_head * 2;
  305. macb->tx_ring[tx_head].ctrl = ctrl;
  306. macb_set_addr(macb, &macb->tx_ring[tx_head], paddr);
  307. barrier();
  308. macb_flush_ring_desc(macb, TX);
  309. macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
  310. /*
  311. * I guess this is necessary because the networking core may
  312. * re-use the transmit buffer as soon as we return...
  313. */
  314. for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
  315. barrier();
  316. macb_invalidate_ring_desc(macb, TX);
  317. ctrl = macb->tx_ring[tx_head].ctrl;
  318. if (ctrl & MACB_BIT(TX_USED))
  319. break;
  320. udelay(1);
  321. }
  322. dma_unmap_single(paddr, length, DMA_TO_DEVICE);
  323. if (i <= MACB_TX_TIMEOUT) {
  324. if (ctrl & MACB_BIT(TX_UNDERRUN))
  325. printf("%s: TX underrun\n", name);
  326. if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
  327. printf("%s: TX buffers exhausted in mid frame\n", name);
  328. } else {
  329. printf("%s: TX timeout\n", name);
  330. }
  331. /* No one cares anyway */
  332. return 0;
  333. }
  334. static void reclaim_rx_buffers(struct macb_device *macb,
  335. unsigned int new_tail)
  336. {
  337. unsigned int i;
  338. unsigned int count;
  339. i = macb->rx_tail;
  340. macb_invalidate_ring_desc(macb, RX);
  341. while (i > new_tail) {
  342. if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
  343. count = i * 2;
  344. else
  345. count = i;
  346. macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
  347. i++;
  348. if (i > MACB_RX_RING_SIZE)
  349. i = 0;
  350. }
  351. while (i < new_tail) {
  352. if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
  353. count = i * 2;
  354. else
  355. count = i;
  356. macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
  357. i++;
  358. }
  359. barrier();
  360. macb_flush_ring_desc(macb, RX);
  361. macb->rx_tail = new_tail;
  362. }
  363. static int _macb_recv(struct macb_device *macb, uchar **packetp)
  364. {
  365. unsigned int next_rx_tail = macb->next_rx_tail;
  366. void *buffer;
  367. int length;
  368. u32 status;
  369. u8 flag = false;
  370. macb->wrapped = false;
  371. for (;;) {
  372. macb_invalidate_ring_desc(macb, RX);
  373. if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
  374. next_rx_tail = next_rx_tail * 2;
  375. if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
  376. return -EAGAIN;
  377. status = macb->rx_ring[next_rx_tail].ctrl;
  378. if (status & MACB_BIT(RX_SOF)) {
  379. if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
  380. next_rx_tail = next_rx_tail / 2;
  381. flag = true;
  382. }
  383. if (next_rx_tail != macb->rx_tail)
  384. reclaim_rx_buffers(macb, next_rx_tail);
  385. macb->wrapped = false;
  386. }
  387. if (status & MACB_BIT(RX_EOF)) {
  388. buffer = macb->rx_buffer +
  389. macb->rx_buffer_size * macb->rx_tail;
  390. length = status & RXBUF_FRMLEN_MASK;
  391. macb_invalidate_rx_buffer(macb);
  392. if (macb->wrapped) {
  393. unsigned int headlen, taillen;
  394. headlen = macb->rx_buffer_size *
  395. (MACB_RX_RING_SIZE - macb->rx_tail);
  396. taillen = length - headlen;
  397. memcpy((void *)net_rx_packets[0],
  398. buffer, headlen);
  399. memcpy((void *)net_rx_packets[0] + headlen,
  400. macb->rx_buffer, taillen);
  401. *packetp = (void *)net_rx_packets[0];
  402. } else {
  403. *packetp = buffer;
  404. }
  405. if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
  406. if (!flag)
  407. next_rx_tail = next_rx_tail / 2;
  408. }
  409. if (++next_rx_tail >= MACB_RX_RING_SIZE)
  410. next_rx_tail = 0;
  411. macb->next_rx_tail = next_rx_tail;
  412. return length;
  413. } else {
  414. if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
  415. if (!flag)
  416. next_rx_tail = next_rx_tail / 2;
  417. flag = false;
  418. }
  419. if (++next_rx_tail >= MACB_RX_RING_SIZE) {
  420. macb->wrapped = true;
  421. next_rx_tail = 0;
  422. }
  423. }
  424. barrier();
  425. }
  426. }
  427. static void macb_phy_reset(struct macb_device *macb, const char *name)
  428. {
  429. int i;
  430. u16 status, adv;
  431. adv = ADVERTISE_CSMA | ADVERTISE_ALL;
  432. macb_mdio_write(macb, macb->phy_addr, MII_ADVERTISE, adv);
  433. printf("%s: Starting autonegotiation...\n", name);
  434. macb_mdio_write(macb, macb->phy_addr, MII_BMCR, (BMCR_ANENABLE
  435. | BMCR_ANRESTART));
  436. for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
  437. status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
  438. if (status & BMSR_ANEGCOMPLETE)
  439. break;
  440. udelay(100);
  441. }
  442. if (status & BMSR_ANEGCOMPLETE)
  443. printf("%s: Autonegotiation complete\n", name);
  444. else
  445. printf("%s: Autonegotiation timed out (status=0x%04x)\n",
  446. name, status);
  447. }
  448. static int macb_phy_find(struct macb_device *macb, const char *name)
  449. {
  450. int i;
  451. u16 phy_id;
  452. phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
  453. if (phy_id != 0xffff) {
  454. printf("%s: PHY present at %d\n", name, macb->phy_addr);
  455. return 0;
  456. }
  457. /* Search for PHY... */
  458. for (i = 0; i < 32; i++) {
  459. macb->phy_addr = i;
  460. phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
  461. if (phy_id != 0xffff) {
  462. printf("%s: PHY present at %d\n", name, i);
  463. return 0;
  464. }
  465. }
  466. /* PHY isn't up to snuff */
  467. printf("%s: PHY not found\n", name);
  468. return -ENODEV;
  469. }
  470. /**
  471. * macb_linkspd_cb - Linkspeed change callback function
  472. * @dev/@regs: MACB udevice (DM version) or
  473. * Base Register of MACB devices (non-DM version)
  474. * @speed: Linkspeed
  475. * Returns 0 when operation success and negative errno number
  476. * when operation failed.
  477. */
  478. #ifdef CONFIG_DM_ETH
  479. static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
  480. {
  481. fdt_addr_t addr;
  482. void *gemgxl_regs;
  483. addr = dev_read_addr_index(dev, 1);
  484. if (addr == FDT_ADDR_T_NONE)
  485. return -ENODEV;
  486. gemgxl_regs = (void __iomem *)addr;
  487. if (!gemgxl_regs)
  488. return -ENODEV;
  489. /*
  490. * SiFive GEMGXL TX clock operation mode:
  491. *
  492. * 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
  493. * and output clock on GMII output signal GTX_CLK
  494. * 1 = MII mode. Use MII input signal TX_CLK in TX logic
  495. */
  496. writel(rate != 125000000, gemgxl_regs);
  497. return 0;
  498. }
  499. static int macb_sama7g5_clk_init(struct udevice *dev, ulong rate)
  500. {
  501. struct clk clk;
  502. int ret;
  503. ret = clk_get_by_name(dev, "tx_clk", &clk);
  504. if (ret)
  505. return ret;
  506. /*
  507. * This is for using GCK. Clock rate is addressed via assigned-clock
  508. * property, so only clock enable is needed here. The switching to
  509. * proper clock rate depending on link speed is managed by IP logic.
  510. */
  511. return clk_enable(&clk);
  512. }
  513. int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
  514. {
  515. #ifdef CONFIG_CLK
  516. struct macb_device *macb = dev_get_priv(dev);
  517. struct clk tx_clk;
  518. ulong rate;
  519. int ret;
  520. switch (speed) {
  521. case _10BASET:
  522. rate = 2500000; /* 2.5 MHz */
  523. break;
  524. case _100BASET:
  525. rate = 25000000; /* 25 MHz */
  526. break;
  527. case _1000BASET:
  528. rate = 125000000; /* 125 MHz */
  529. break;
  530. default:
  531. /* does not change anything */
  532. return 0;
  533. }
  534. if (macb->config->clk_init)
  535. return macb->config->clk_init(dev, rate);
  536. /*
  537. * "tx_clk" is an optional clock source for MACB.
  538. * Ignore if it does not exist in DT.
  539. */
  540. ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
  541. if (ret)
  542. return 0;
  543. if (tx_clk.dev) {
  544. ret = clk_set_rate(&tx_clk, rate);
  545. if (ret < 0)
  546. return ret;
  547. }
  548. #endif
  549. return 0;
  550. }
  551. #else
  552. int __weak macb_linkspd_cb(void *regs, unsigned int speed)
  553. {
  554. return 0;
  555. }
  556. #endif
  557. #ifdef CONFIG_DM_ETH
  558. static int macb_phy_init(struct udevice *dev, const char *name)
  559. #else
  560. static int macb_phy_init(struct macb_device *macb, const char *name)
  561. #endif
  562. {
  563. #ifdef CONFIG_DM_ETH
  564. struct macb_device *macb = dev_get_priv(dev);
  565. #endif
  566. u32 ncfgr;
  567. u16 phy_id, status, adv, lpa;
  568. int media, speed, duplex;
  569. int ret;
  570. int i;
  571. arch_get_mdio_control(name);
  572. /* Auto-detect phy_addr */
  573. ret = macb_phy_find(macb, name);
  574. if (ret)
  575. return ret;
  576. /* Check if the PHY is up to snuff... */
  577. phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
  578. if (phy_id == 0xffff) {
  579. printf("%s: No PHY present\n", name);
  580. return -ENODEV;
  581. }
  582. #ifdef CONFIG_PHYLIB
  583. #ifdef CONFIG_DM_ETH
  584. macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev,
  585. macb->phy_interface);
  586. #else
  587. /* need to consider other phy interface mode */
  588. macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
  589. PHY_INTERFACE_MODE_RGMII);
  590. #endif
  591. if (!macb->phydev) {
  592. printf("phy_connect failed\n");
  593. return -ENODEV;
  594. }
  595. phy_config(macb->phydev);
  596. #endif
  597. status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
  598. if (!(status & BMSR_LSTATUS)) {
  599. /* Try to re-negotiate if we don't have link already. */
  600. macb_phy_reset(macb, name);
  601. for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
  602. status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
  603. if (status & BMSR_LSTATUS) {
  604. /*
  605. * Delay a bit after the link is established,
  606. * so that the next xfer does not fail
  607. */
  608. mdelay(10);
  609. break;
  610. }
  611. udelay(100);
  612. }
  613. }
  614. if (!(status & BMSR_LSTATUS)) {
  615. printf("%s: link down (status: 0x%04x)\n",
  616. name, status);
  617. return -ENETDOWN;
  618. }
  619. /* First check for GMAC and that it is GiB capable */
  620. if (gem_is_gigabit_capable(macb)) {
  621. lpa = macb_mdio_read(macb, macb->phy_addr, MII_STAT1000);
  622. if (lpa & (LPA_1000FULL | LPA_1000HALF | LPA_1000XFULL |
  623. LPA_1000XHALF)) {
  624. duplex = ((lpa & (LPA_1000FULL | LPA_1000XFULL)) ?
  625. 1 : 0);
  626. printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
  627. name,
  628. duplex ? "full" : "half",
  629. lpa);
  630. ncfgr = macb_readl(macb, NCFGR);
  631. ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
  632. ncfgr |= GEM_BIT(GBE);
  633. if (duplex)
  634. ncfgr |= MACB_BIT(FD);
  635. macb_writel(macb, NCFGR, ncfgr);
  636. #ifdef CONFIG_DM_ETH
  637. ret = macb_linkspd_cb(dev, _1000BASET);
  638. #else
  639. ret = macb_linkspd_cb(macb->regs, _1000BASET);
  640. #endif
  641. if (ret)
  642. return ret;
  643. return 0;
  644. }
  645. }
  646. /* fall back for EMAC checking */
  647. adv = macb_mdio_read(macb, macb->phy_addr, MII_ADVERTISE);
  648. lpa = macb_mdio_read(macb, macb->phy_addr, MII_LPA);
  649. media = mii_nway_result(lpa & adv);
  650. speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
  651. ? 1 : 0);
  652. duplex = (media & ADVERTISE_FULL) ? 1 : 0;
  653. printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
  654. name,
  655. speed ? "100" : "10",
  656. duplex ? "full" : "half",
  657. lpa);
  658. ncfgr = macb_readl(macb, NCFGR);
  659. ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
  660. if (speed) {
  661. ncfgr |= MACB_BIT(SPD);
  662. #ifdef CONFIG_DM_ETH
  663. ret = macb_linkspd_cb(dev, _100BASET);
  664. #else
  665. ret = macb_linkspd_cb(macb->regs, _100BASET);
  666. #endif
  667. } else {
  668. #ifdef CONFIG_DM_ETH
  669. ret = macb_linkspd_cb(dev, _10BASET);
  670. #else
  671. ret = macb_linkspd_cb(macb->regs, _10BASET);
  672. #endif
  673. }
  674. if (ret)
  675. return ret;
  676. if (duplex)
  677. ncfgr |= MACB_BIT(FD);
  678. macb_writel(macb, NCFGR, ncfgr);
  679. return 0;
  680. }
  681. static int gmac_init_multi_queues(struct macb_device *macb)
  682. {
  683. int i, num_queues = 1;
  684. u32 queue_mask;
  685. unsigned long paddr;
  686. /* bit 0 is never set but queue 0 always exists */
  687. queue_mask = gem_readl(macb, DCFG6) & 0xff;
  688. queue_mask |= 0x1;
  689. for (i = 1; i < MACB_MAX_QUEUES; i++)
  690. if (queue_mask & (1 << i))
  691. num_queues++;
  692. macb->dummy_desc->ctrl = MACB_BIT(TX_USED);
  693. macb->dummy_desc->addr = 0;
  694. flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
  695. ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
  696. paddr = macb->dummy_desc_dma;
  697. for (i = 1; i < num_queues; i++) {
  698. gem_writel_queue_TBQP(macb, lower_32_bits(paddr), i - 1);
  699. gem_writel_queue_RBQP(macb, lower_32_bits(paddr), i - 1);
  700. if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
  701. gem_writel_queue_TBQPH(macb, upper_32_bits(paddr),
  702. i - 1);
  703. gem_writel_queue_RBQPH(macb, upper_32_bits(paddr),
  704. i - 1);
  705. }
  706. }
  707. return 0;
  708. }
  709. static void gmac_configure_dma(struct macb_device *macb)
  710. {
  711. u32 buffer_size;
  712. u32 dmacfg;
  713. buffer_size = macb->rx_buffer_size / RX_BUFFER_MULTIPLE;
  714. dmacfg = gem_readl(macb, DMACFG) & ~GEM_BF(RXBS, -1L);
  715. dmacfg |= GEM_BF(RXBS, buffer_size);
  716. if (macb->config->dma_burst_length)
  717. dmacfg = GEM_BFINS(FBLDO,
  718. macb->config->dma_burst_length, dmacfg);
  719. dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
  720. dmacfg &= ~GEM_BIT(ENDIA_PKT);
  721. if (macb->is_big_endian)
  722. dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
  723. else
  724. dmacfg &= ~GEM_BIT(ENDIA_DESC);
  725. dmacfg &= ~GEM_BIT(ADDR64);
  726. if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
  727. dmacfg |= GEM_BIT(ADDR64);
  728. gem_writel(macb, DMACFG, dmacfg);
  729. }
  730. #ifdef CONFIG_DM_ETH
  731. static int _macb_init(struct udevice *dev, const char *name)
  732. #else
  733. static int _macb_init(struct macb_device *macb, const char *name)
  734. #endif
  735. {
  736. #ifdef CONFIG_DM_ETH
  737. struct macb_device *macb = dev_get_priv(dev);
  738. unsigned int val = 0;
  739. #endif
  740. unsigned long paddr;
  741. int ret;
  742. int i;
  743. int count;
  744. /*
  745. * macb_halt should have been called at some point before now,
  746. * so we'll assume the controller is idle.
  747. */
  748. /* initialize DMA descriptors */
  749. paddr = macb->rx_buffer_dma;
  750. for (i = 0; i < MACB_RX_RING_SIZE; i++) {
  751. if (i == (MACB_RX_RING_SIZE - 1))
  752. paddr |= MACB_BIT(RX_WRAP);
  753. if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
  754. count = i * 2;
  755. else
  756. count = i;
  757. macb->rx_ring[count].ctrl = 0;
  758. macb_set_addr(macb, &macb->rx_ring[count], paddr);
  759. paddr += macb->rx_buffer_size;
  760. }
  761. macb_flush_ring_desc(macb, RX);
  762. macb_flush_rx_buffer(macb);
  763. for (i = 0; i < MACB_TX_RING_SIZE; i++) {
  764. if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
  765. count = i * 2;
  766. else
  767. count = i;
  768. macb_set_addr(macb, &macb->tx_ring[count], 0);
  769. if (i == (MACB_TX_RING_SIZE - 1))
  770. macb->tx_ring[count].ctrl = MACB_BIT(TX_USED) |
  771. MACB_BIT(TX_WRAP);
  772. else
  773. macb->tx_ring[count].ctrl = MACB_BIT(TX_USED);
  774. }
  775. macb_flush_ring_desc(macb, TX);
  776. macb->rx_tail = 0;
  777. macb->tx_head = 0;
  778. macb->tx_tail = 0;
  779. macb->next_rx_tail = 0;
  780. #ifdef CONFIG_MACB_ZYNQ
  781. gem_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
  782. #endif
  783. macb_writel(macb, RBQP, lower_32_bits(macb->rx_ring_dma));
  784. macb_writel(macb, TBQP, lower_32_bits(macb->tx_ring_dma));
  785. if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
  786. macb_writel(macb, RBQPH, upper_32_bits(macb->rx_ring_dma));
  787. macb_writel(macb, TBQPH, upper_32_bits(macb->tx_ring_dma));
  788. }
  789. if (macb_is_gem(macb)) {
  790. /* Initialize DMA properties */
  791. gmac_configure_dma(macb);
  792. /* Check the multi queue and initialize the queue for tx */
  793. gmac_init_multi_queues(macb);
  794. /*
  795. * When the GMAC IP with GE feature, this bit is used to
  796. * select interface between RGMII and GMII.
  797. * When the GMAC IP without GE feature, this bit is used
  798. * to select interface between RMII and MII.
  799. */
  800. #ifdef CONFIG_DM_ETH
  801. if (macb->phy_interface == PHY_INTERFACE_MODE_RGMII ||
  802. macb->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
  803. macb->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
  804. macb->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
  805. val = macb->config->usrio->rgmii;
  806. else if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
  807. val = macb->config->usrio->rmii;
  808. else if (macb->phy_interface == PHY_INTERFACE_MODE_MII)
  809. val = macb->config->usrio->mii;
  810. if (macb->config->caps & MACB_CAPS_USRIO_HAS_CLKEN)
  811. val |= macb->config->usrio->clken;
  812. gem_writel(macb, USRIO, val);
  813. if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) {
  814. unsigned int ncfgr = macb_readl(macb, NCFGR);
  815. ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
  816. macb_writel(macb, NCFGR, ncfgr);
  817. }
  818. #else
  819. #if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
  820. gem_writel(macb, USRIO, macb->config->usrio->rgmii);
  821. #else
  822. gem_writel(macb, USRIO, 0);
  823. #endif
  824. #endif
  825. } else {
  826. /* choose RMII or MII mode. This depends on the board */
  827. #ifdef CONFIG_DM_ETH
  828. #ifdef CONFIG_AT91FAMILY
  829. if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
  830. macb_writel(macb, USRIO,
  831. macb->config->usrio->rmii |
  832. macb->config->usrio->clken);
  833. } else {
  834. macb_writel(macb, USRIO, macb->config->usrio->clken);
  835. }
  836. #else
  837. if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
  838. macb_writel(macb, USRIO, 0);
  839. else
  840. macb_writel(macb, USRIO, macb->config->usrio->mii);
  841. #endif
  842. #else
  843. #ifdef CONFIG_RMII
  844. #ifdef CONFIG_AT91FAMILY
  845. macb_writel(macb, USRIO, macb->config->usrio->rmii |
  846. macb->config->usrio->clken);
  847. #else
  848. macb_writel(macb, USRIO, 0);
  849. #endif
  850. #else
  851. #ifdef CONFIG_AT91FAMILY
  852. macb_writel(macb, USRIO, macb->config->usrio->clken);
  853. #else
  854. macb_writel(macb, USRIO, macb->config->usrio->mii);
  855. #endif
  856. #endif /* CONFIG_RMII */
  857. #endif
  858. }
  859. #ifdef CONFIG_DM_ETH
  860. ret = macb_phy_init(dev, name);
  861. #else
  862. ret = macb_phy_init(macb, name);
  863. #endif
  864. if (ret)
  865. return ret;
  866. /* Enable TX and RX */
  867. macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
  868. return 0;
  869. }
  870. static void _macb_halt(struct macb_device *macb)
  871. {
  872. u32 ncr, tsr;
  873. /* Halt the controller and wait for any ongoing transmission to end. */
  874. ncr = macb_readl(macb, NCR);
  875. ncr |= MACB_BIT(THALT);
  876. macb_writel(macb, NCR, ncr);
  877. do {
  878. tsr = macb_readl(macb, TSR);
  879. } while (tsr & MACB_BIT(TGO));
  880. /* Disable TX and RX, and clear statistics */
  881. macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
  882. }
  883. static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
  884. {
  885. u32 hwaddr_bottom;
  886. u16 hwaddr_top;
  887. /* set hardware address */
  888. hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
  889. enetaddr[2] << 16 | enetaddr[3] << 24;
  890. macb_writel(macb, SA1B, hwaddr_bottom);
  891. hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
  892. macb_writel(macb, SA1T, hwaddr_top);
  893. return 0;
  894. }
  895. static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
  896. {
  897. u32 config;
  898. #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
  899. unsigned long macb_hz = macb->pclk_rate;
  900. #else
  901. unsigned long macb_hz = get_macb_pclk_rate(id);
  902. #endif
  903. if (macb_hz < 20000000)
  904. config = MACB_BF(CLK, MACB_CLK_DIV8);
  905. else if (macb_hz < 40000000)
  906. config = MACB_BF(CLK, MACB_CLK_DIV16);
  907. else if (macb_hz < 80000000)
  908. config = MACB_BF(CLK, MACB_CLK_DIV32);
  909. else
  910. config = MACB_BF(CLK, MACB_CLK_DIV64);
  911. return config;
  912. }
  913. static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
  914. {
  915. u32 config;
  916. #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
  917. unsigned long macb_hz = macb->pclk_rate;
  918. #else
  919. unsigned long macb_hz = get_macb_pclk_rate(id);
  920. #endif
  921. if (macb_hz < 20000000)
  922. config = GEM_BF(CLK, GEM_CLK_DIV8);
  923. else if (macb_hz < 40000000)
  924. config = GEM_BF(CLK, GEM_CLK_DIV16);
  925. else if (macb_hz < 80000000)
  926. config = GEM_BF(CLK, GEM_CLK_DIV32);
  927. else if (macb_hz < 120000000)
  928. config = GEM_BF(CLK, GEM_CLK_DIV48);
  929. else if (macb_hz < 160000000)
  930. config = GEM_BF(CLK, GEM_CLK_DIV64);
  931. else if (macb_hz < 240000000)
  932. config = GEM_BF(CLK, GEM_CLK_DIV96);
  933. else if (macb_hz < 320000000)
  934. config = GEM_BF(CLK, GEM_CLK_DIV128);
  935. else
  936. config = GEM_BF(CLK, GEM_CLK_DIV224);
  937. return config;
  938. }
  939. /*
  940. * Get the DMA bus width field of the network configuration register that we
  941. * should program. We find the width from decoding the design configuration
  942. * register to find the maximum supported data bus width.
  943. */
  944. static u32 macb_dbw(struct macb_device *macb)
  945. {
  946. switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
  947. case 4:
  948. return GEM_BF(DBW, GEM_DBW128);
  949. case 2:
  950. return GEM_BF(DBW, GEM_DBW64);
  951. case 1:
  952. default:
  953. return GEM_BF(DBW, GEM_DBW32);
  954. }
  955. }
  956. static void _macb_eth_initialize(struct macb_device *macb)
  957. {
  958. int id = 0; /* This is not used by functions we call */
  959. u32 ncfgr;
  960. if (macb_is_gem(macb))
  961. macb->rx_buffer_size = GEM_RX_BUFFER_SIZE;
  962. else
  963. macb->rx_buffer_size = MACB_RX_BUFFER_SIZE;
  964. /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
  965. macb->rx_buffer = dma_alloc_coherent(macb->rx_buffer_size *
  966. MACB_RX_RING_SIZE,
  967. &macb->rx_buffer_dma);
  968. macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
  969. &macb->rx_ring_dma);
  970. macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
  971. &macb->tx_ring_dma);
  972. macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
  973. &macb->dummy_desc_dma);
  974. /*
  975. * Do some basic initialization so that we at least can talk
  976. * to the PHY
  977. */
  978. if (macb_is_gem(macb)) {
  979. ncfgr = gem_mdc_clk_div(id, macb);
  980. ncfgr |= macb_dbw(macb);
  981. } else {
  982. ncfgr = macb_mdc_clk_div(id, macb);
  983. }
  984. macb_writel(macb, NCFGR, ncfgr);
  985. }
  986. #ifndef CONFIG_DM_ETH
  987. static int macb_send(struct eth_device *netdev, void *packet, int length)
  988. {
  989. struct macb_device *macb = to_macb(netdev);
  990. return _macb_send(macb, netdev->name, packet, length);
  991. }
  992. static int macb_recv(struct eth_device *netdev)
  993. {
  994. struct macb_device *macb = to_macb(netdev);
  995. uchar *packet;
  996. int length;
  997. macb->wrapped = false;
  998. for (;;) {
  999. macb->next_rx_tail = macb->rx_tail;
  1000. length = _macb_recv(macb, &packet);
  1001. if (length >= 0) {
  1002. net_process_received_packet(packet, length);
  1003. reclaim_rx_buffers(macb, macb->next_rx_tail);
  1004. } else {
  1005. return length;
  1006. }
  1007. }
  1008. }
  1009. static int macb_init(struct eth_device *netdev, struct bd_info *bd)
  1010. {
  1011. struct macb_device *macb = to_macb(netdev);
  1012. return _macb_init(macb, netdev->name);
  1013. }
  1014. static void macb_halt(struct eth_device *netdev)
  1015. {
  1016. struct macb_device *macb = to_macb(netdev);
  1017. return _macb_halt(macb);
  1018. }
  1019. static int macb_write_hwaddr(struct eth_device *netdev)
  1020. {
  1021. struct macb_device *macb = to_macb(netdev);
  1022. return _macb_write_hwaddr(macb, netdev->enetaddr);
  1023. }
  1024. int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
  1025. {
  1026. struct macb_device *macb;
  1027. struct eth_device *netdev;
  1028. macb = malloc(sizeof(struct macb_device));
  1029. if (!macb) {
  1030. printf("Error: Failed to allocate memory for MACB%d\n", id);
  1031. return -1;
  1032. }
  1033. memset(macb, 0, sizeof(struct macb_device));
  1034. netdev = &macb->netdev;
  1035. macb->regs = regs;
  1036. macb->phy_addr = phy_addr;
  1037. if (macb_is_gem(macb))
  1038. sprintf(netdev->name, "gmac%d", id);
  1039. else
  1040. sprintf(netdev->name, "macb%d", id);
  1041. netdev->init = macb_init;
  1042. netdev->halt = macb_halt;
  1043. netdev->send = macb_send;
  1044. netdev->recv = macb_recv;
  1045. netdev->write_hwaddr = macb_write_hwaddr;
  1046. _macb_eth_initialize(macb);
  1047. eth_register(netdev);
  1048. #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
  1049. int retval;
  1050. struct mii_dev *mdiodev = mdio_alloc();
  1051. if (!mdiodev)
  1052. return -ENOMEM;
  1053. strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
  1054. mdiodev->read = macb_miiphy_read;
  1055. mdiodev->write = macb_miiphy_write;
  1056. retval = mdio_register(mdiodev);
  1057. if (retval < 0)
  1058. return retval;
  1059. macb->bus = miiphy_get_dev_by_name(netdev->name);
  1060. #endif
  1061. return 0;
  1062. }
  1063. #endif /* !CONFIG_DM_ETH */
  1064. #ifdef CONFIG_DM_ETH
  1065. static int macb_start(struct udevice *dev)
  1066. {
  1067. return _macb_init(dev, dev->name);
  1068. }
  1069. static int macb_send(struct udevice *dev, void *packet, int length)
  1070. {
  1071. struct macb_device *macb = dev_get_priv(dev);
  1072. return _macb_send(macb, dev->name, packet, length);
  1073. }
  1074. static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
  1075. {
  1076. struct macb_device *macb = dev_get_priv(dev);
  1077. macb->next_rx_tail = macb->rx_tail;
  1078. macb->wrapped = false;
  1079. return _macb_recv(macb, packetp);
  1080. }
  1081. static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
  1082. {
  1083. struct macb_device *macb = dev_get_priv(dev);
  1084. reclaim_rx_buffers(macb, macb->next_rx_tail);
  1085. return 0;
  1086. }
  1087. static void macb_stop(struct udevice *dev)
  1088. {
  1089. struct macb_device *macb = dev_get_priv(dev);
  1090. _macb_halt(macb);
  1091. }
  1092. static int macb_write_hwaddr(struct udevice *dev)
  1093. {
  1094. struct eth_pdata *plat = dev_get_plat(dev);
  1095. struct macb_device *macb = dev_get_priv(dev);
  1096. return _macb_write_hwaddr(macb, plat->enetaddr);
  1097. }
  1098. static const struct eth_ops macb_eth_ops = {
  1099. .start = macb_start,
  1100. .send = macb_send,
  1101. .recv = macb_recv,
  1102. .stop = macb_stop,
  1103. .free_pkt = macb_free_pkt,
  1104. .write_hwaddr = macb_write_hwaddr,
  1105. };
  1106. #ifdef CONFIG_CLK
  1107. static int macb_enable_clk(struct udevice *dev)
  1108. {
  1109. struct macb_device *macb = dev_get_priv(dev);
  1110. struct clk clk;
  1111. ulong clk_rate;
  1112. int ret;
  1113. ret = clk_get_by_index(dev, 0, &clk);
  1114. if (ret)
  1115. return -EINVAL;
  1116. /*
  1117. * If clock driver didn't support enable or disable then
  1118. * we get -ENOSYS from clk_enable(). To handle this, we
  1119. * don't fail for ret == -ENOSYS.
  1120. */
  1121. ret = clk_enable(&clk);
  1122. if (ret && ret != -ENOSYS)
  1123. return ret;
  1124. clk_rate = clk_get_rate(&clk);
  1125. if (!clk_rate)
  1126. return -EINVAL;
  1127. macb->pclk_rate = clk_rate;
  1128. return 0;
  1129. }
  1130. #endif
  1131. static const struct macb_usrio_cfg macb_default_usrio = {
  1132. .mii = MACB_BIT(MII),
  1133. .rmii = MACB_BIT(RMII),
  1134. .rgmii = GEM_BIT(RGMII),
  1135. .clken = MACB_BIT(CLKEN),
  1136. };
  1137. static const struct macb_config default_gem_config = {
  1138. .dma_burst_length = 16,
  1139. .hw_dma_cap = HW_DMA_CAP_32B,
  1140. .clk_init = NULL,
  1141. .usrio = &macb_default_usrio,
  1142. };
  1143. static int macb_eth_probe(struct udevice *dev)
  1144. {
  1145. struct eth_pdata *pdata = dev_get_plat(dev);
  1146. struct macb_device *macb = dev_get_priv(dev);
  1147. struct ofnode_phandle_args phandle_args;
  1148. const char *phy_mode;
  1149. int ret;
  1150. phy_mode = dev_read_prop(dev, "phy-mode", NULL);
  1151. if (phy_mode)
  1152. macb->phy_interface = phy_get_interface_by_name(phy_mode);
  1153. if (macb->phy_interface == -1) {
  1154. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  1155. return -EINVAL;
  1156. }
  1157. /* Read phyaddr from DT */
  1158. if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
  1159. &phandle_args))
  1160. macb->phy_addr = ofnode_read_u32_default(phandle_args.node,
  1161. "reg", -1);
  1162. macb->regs = (void *)pdata->iobase;
  1163. macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
  1164. macb->config = (struct macb_config *)dev_get_driver_data(dev);
  1165. if (!macb->config)
  1166. macb->config = &default_gem_config;
  1167. #ifdef CONFIG_CLK
  1168. ret = macb_enable_clk(dev);
  1169. if (ret)
  1170. return ret;
  1171. #endif
  1172. _macb_eth_initialize(macb);
  1173. #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
  1174. macb->bus = mdio_alloc();
  1175. if (!macb->bus)
  1176. return -ENOMEM;
  1177. strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
  1178. macb->bus->read = macb_miiphy_read;
  1179. macb->bus->write = macb_miiphy_write;
  1180. ret = mdio_register(macb->bus);
  1181. if (ret < 0)
  1182. return ret;
  1183. macb->bus = miiphy_get_dev_by_name(dev->name);
  1184. #endif
  1185. return 0;
  1186. }
  1187. static int macb_eth_remove(struct udevice *dev)
  1188. {
  1189. struct macb_device *macb = dev_get_priv(dev);
  1190. #ifdef CONFIG_PHYLIB
  1191. free(macb->phydev);
  1192. #endif
  1193. mdio_unregister(macb->bus);
  1194. mdio_free(macb->bus);
  1195. return 0;
  1196. }
  1197. /**
  1198. * macb_late_eth_of_to_plat
  1199. * @dev: udevice struct
  1200. * Returns 0 when operation success and negative errno number
  1201. * when operation failed.
  1202. */
  1203. int __weak macb_late_eth_of_to_plat(struct udevice *dev)
  1204. {
  1205. return 0;
  1206. }
  1207. static int macb_eth_of_to_plat(struct udevice *dev)
  1208. {
  1209. struct eth_pdata *pdata = dev_get_plat(dev);
  1210. pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
  1211. if (!pdata->iobase)
  1212. return -EINVAL;
  1213. return macb_late_eth_of_to_plat(dev);
  1214. }
  1215. static const struct macb_usrio_cfg sama7g5_usrio = {
  1216. .mii = 0,
  1217. .rmii = 1,
  1218. .rgmii = 2,
  1219. .clken = BIT(2),
  1220. };
  1221. static const struct macb_config microchip_config = {
  1222. .dma_burst_length = 16,
  1223. .hw_dma_cap = HW_DMA_CAP_64B,
  1224. .clk_init = NULL,
  1225. .usrio = &macb_default_usrio,
  1226. };
  1227. static const struct macb_config sama5d4_config = {
  1228. .dma_burst_length = 4,
  1229. .hw_dma_cap = HW_DMA_CAP_32B,
  1230. .clk_init = NULL,
  1231. .usrio = &macb_default_usrio,
  1232. };
  1233. static const struct macb_config sifive_config = {
  1234. .dma_burst_length = 16,
  1235. .hw_dma_cap = HW_DMA_CAP_32B,
  1236. .clk_init = macb_sifive_clk_init,
  1237. .usrio = &macb_default_usrio,
  1238. };
  1239. static const struct macb_config sama7g5_gmac_config = {
  1240. .dma_burst_length = 16,
  1241. .hw_dma_cap = HW_DMA_CAP_32B,
  1242. .clk_init = macb_sama7g5_clk_init,
  1243. .usrio = &sama7g5_usrio,
  1244. };
  1245. static const struct macb_config sama7g5_emac_config = {
  1246. .caps = MACB_CAPS_USRIO_HAS_CLKEN,
  1247. .dma_burst_length = 16,
  1248. .hw_dma_cap = HW_DMA_CAP_32B,
  1249. .usrio = &sama7g5_usrio,
  1250. };
  1251. static const struct udevice_id macb_eth_ids[] = {
  1252. { .compatible = "cdns,macb" },
  1253. { .compatible = "cdns,at91sam9260-macb" },
  1254. { .compatible = "cdns,sam9x60-macb" },
  1255. { .compatible = "cdns,sama7g5-gem",
  1256. .data = (ulong)&sama7g5_gmac_config },
  1257. { .compatible = "cdns,sama7g5-emac",
  1258. .data = (ulong)&sama7g5_emac_config },
  1259. { .compatible = "atmel,sama5d2-gem" },
  1260. { .compatible = "atmel,sama5d3-gem" },
  1261. { .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config },
  1262. { .compatible = "cdns,zynq-gem" },
  1263. { .compatible = "sifive,fu540-c000-gem",
  1264. .data = (ulong)&sifive_config },
  1265. { .compatible = "microchip,mpfs-mss-gem",
  1266. .data = (ulong)&microchip_config },
  1267. { }
  1268. };
  1269. U_BOOT_DRIVER(eth_macb) = {
  1270. .name = "eth_macb",
  1271. .id = UCLASS_ETH,
  1272. .of_match = macb_eth_ids,
  1273. .of_to_plat = macb_eth_of_to_plat,
  1274. .probe = macb_eth_probe,
  1275. .remove = macb_eth_remove,
  1276. .ops = &macb_eth_ops,
  1277. .priv_auto = sizeof(struct macb_device),
  1278. .plat_auto = sizeof(struct eth_pdata),
  1279. };
  1280. #endif
  1281. #endif