lan91c96.h 22 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*------------------------------------------------------------------------
  3. * lan91c96.h
  4. *
  5. * (C) Copyright 2002
  6. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  7. * Rolf Offermanns <rof@sysgo.de>
  8. * Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
  9. * Developed by Simple Network Magic Corporation (SNMC)
  10. * Copyright (C) 1996 by Erik Stahlman (ES)
  11. *
  12. * This file contains register information and access macros for
  13. * the LAN91C96 single chip ethernet controller. It is a modified
  14. * version of the smc9111.h file.
  15. *
  16. * Information contained in this file was obtained from the LAN91C96
  17. * manual from SMC. To get a copy, if you really want one, you can find
  18. * information under www.smsc.com.
  19. *
  20. * Authors
  21. * Erik Stahlman ( erik@vt.edu )
  22. * Daris A Nevil ( dnevil@snmc.com )
  23. *
  24. * History
  25. * 04/30/03 Mathijs Haarman Modified smc91111.h (u-boot version)
  26. * for lan91c96
  27. *-------------------------------------------------------------------------
  28. */
  29. #ifndef _LAN91C96_H_
  30. #define _LAN91C96_H_
  31. #include <asm/types.h>
  32. #include <asm/io.h>
  33. #include <config.h>
  34. /* I want some simple types */
  35. typedef unsigned char byte;
  36. typedef unsigned short word;
  37. typedef unsigned long int dword;
  38. /*
  39. * DEBUGGING LEVELS
  40. *
  41. * 0 for normal operation
  42. * 1 for slightly more details
  43. * >2 for various levels of increasingly useless information
  44. * 2 for interrupt tracking, status flags
  45. * 3 for packet info
  46. * 4 for complete packet dumps
  47. */
  48. /*#define SMC_DEBUG 0 */
  49. /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
  50. #define SMC_IO_EXTENT 16
  51. #ifdef CONFIG_CPU_PXA25X
  52. #define SMC_IO_SHIFT 0
  53. #define SMCREG(edev, r) ((edev)->iobase+((r)<<SMC_IO_SHIFT))
  54. #define SMC_inl(edev, r) (*((volatile dword *)SMCREG(edev, r)))
  55. #define SMC_inw(edev, r) (*((volatile word *)SMCREG(edev, r)))
  56. #define SMC_inb(edev, p) ({ \
  57. unsigned int __p = p; \
  58. unsigned int __v = SMC_inw(edev, __p & ~1); \
  59. if (__p & 1) __v >>= 8; \
  60. else __v &= 0xff; \
  61. __v; })
  62. #define SMC_outl(edev, d, r) (*((volatile dword *)SMCREG(edev, r)) = d)
  63. #define SMC_outw(edev, d, r) (*((volatile word *)SMCREG(edev, r)) = d)
  64. #define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \
  65. word __w = SMC_inw(edev, (r)&~1); \
  66. __w &= ((r)&1) ? 0x00FF : 0xFF00; \
  67. __w |= ((r)&1) ? __d<<8 : __d; \
  68. SMC_outw(edev, __w, (r)&~1); \
  69. })
  70. #define SMC_outsl(edev, r, b, l) ({ int __i; \
  71. dword *__b2; \
  72. __b2 = (dword *) b; \
  73. for (__i = 0; __i < l; __i++) { \
  74. SMC_outl(edev, *(__b2 + __i),\
  75. r); \
  76. } \
  77. })
  78. #define SMC_outsw(edev, r, b, l) ({ int __i; \
  79. word *__b2; \
  80. __b2 = (word *) b; \
  81. for (__i = 0; __i < l; __i++) { \
  82. SMC_outw(edev, *(__b2 + __i),\
  83. r); \
  84. } \
  85. })
  86. #define SMC_insl(edev, r, b, l) ({ int __i ; \
  87. dword *__b2; \
  88. __b2 = (dword *) b; \
  89. for (__i = 0; __i < l; __i++) { \
  90. *(__b2 + __i) = SMC_inl(edev,\
  91. r); \
  92. SMC_inl(edev, 0); \
  93. }; \
  94. })
  95. #define SMC_insw(edev, r, b, l) ({ int __i ; \
  96. word *__b2; \
  97. __b2 = (word *) b; \
  98. for (__i = 0; __i < l; __i++) { \
  99. *(__b2 + __i) = SMC_inw(edev,\
  100. r); \
  101. SMC_inw(edev, 0); \
  102. }; \
  103. })
  104. #define SMC_insb(edev, r, b, l) ({ int __i ; \
  105. byte *__b2; \
  106. __b2 = (byte *) b; \
  107. for (__i = 0; __i < l; __i++) { \
  108. *(__b2 + __i) = SMC_inb(edev,\
  109. r); \
  110. SMC_inb(edev, 0); \
  111. }; \
  112. })
  113. #else /* if not CONFIG_CPU_PXA25X */
  114. /*
  115. * We have only 16 Bit PCMCIA access on Socket 0
  116. */
  117. #define SMC_inw(edev, r) (*((volatile word *)((edev)->iobase+(r))))
  118. #define SMC_inb(edev, r) (((r)&1) ? SMC_inw(edev, (r)&~1)>>8 :\
  119. SMC_inw(edev, r)&0xFF)
  120. #define SMC_outw(edev, d, r) (*((volatile word *)((edev)->iobase+(r))) = d)
  121. #define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \
  122. word __w = SMC_inw(edev, (r)&~1); \
  123. __w &= ((r)&1) ? 0x00FF : 0xFF00; \
  124. __w |= ((r)&1) ? __d<<8 : __d; \
  125. SMC_outw(edev, __w, (r)&~1); \
  126. })
  127. #define SMC_outsw(edev, r, b, l) ({ int __i; \
  128. word *__b2; \
  129. __b2 = (word *) b; \
  130. for (__i = 0; __i < l; __i++) { \
  131. SMC_outw(edev, *(__b2 + __i),\
  132. r); \
  133. } \
  134. })
  135. #define SMC_insw(edev, r, b, l) ({ int __i ; \
  136. word *__b2; \
  137. __b2 = (word *) b; \
  138. for (__i = 0; __i < l; __i++) { \
  139. *(__b2 + __i) = SMC_inw(edev,\
  140. r); \
  141. SMC_inw(edev, 0); \
  142. }; \
  143. })
  144. #endif
  145. /*
  146. ****************************************************************************
  147. * Bank Select Field
  148. ****************************************************************************
  149. */
  150. #define LAN91C96_BANK_SELECT 14 /* Bank Select Register */
  151. #define LAN91C96_BANKSELECT (0x3UC << 0)
  152. #define BANK0 0x00
  153. #define BANK1 0x01
  154. #define BANK2 0x02
  155. #define BANK3 0x03
  156. #define BANK4 0x04
  157. /*
  158. ****************************************************************************
  159. * EEPROM Addresses.
  160. ****************************************************************************
  161. */
  162. #define EEPROM_MAC_OFFSET_1 0x6020
  163. #define EEPROM_MAC_OFFSET_2 0x6021
  164. #define EEPROM_MAC_OFFSET_3 0x6022
  165. /*
  166. ****************************************************************************
  167. * Bank 0 Register Map in I/O Space
  168. ****************************************************************************
  169. */
  170. #define LAN91C96_TCR 0 /* Transmit Control Register */
  171. #define LAN91C96_EPH_STATUS 2 /* EPH Status Register */
  172. #define LAN91C96_RCR 4 /* Receive Control Register */
  173. #define LAN91C96_COUNTER 6 /* Counter Register */
  174. #define LAN91C96_MIR 8 /* Memory Information Register */
  175. #define LAN91C96_MCR 10 /* Memory Configuration Register */
  176. /*
  177. ****************************************************************************
  178. * Transmit Control Register - Bank 0 - Offset 0
  179. ****************************************************************************
  180. */
  181. #define LAN91C96_TCR_TXENA (0x1U << 0)
  182. #define LAN91C96_TCR_LOOP (0x1U << 1)
  183. #define LAN91C96_TCR_FORCOL (0x1U << 2)
  184. #define LAN91C96_TCR_TXP_EN (0x1U << 3)
  185. #define LAN91C96_TCR_PAD_EN (0x1U << 7)
  186. #define LAN91C96_TCR_NOCRC (0x1U << 8)
  187. #define LAN91C96_TCR_MON_CSN (0x1U << 10)
  188. #define LAN91C96_TCR_FDUPLX (0x1U << 11)
  189. #define LAN91C96_TCR_STP_SQET (0x1U << 12)
  190. #define LAN91C96_TCR_EPH_LOOP (0x1U << 13)
  191. #define LAN91C96_TCR_ETEN_TYPE (0x1U << 14)
  192. #define LAN91C96_TCR_FDSE (0x1U << 15)
  193. /*
  194. ****************************************************************************
  195. * EPH Status Register - Bank 0 - Offset 2
  196. ****************************************************************************
  197. */
  198. #define LAN91C96_EPHSR_TX_SUC (0x1U << 0)
  199. #define LAN91C96_EPHSR_SNGL_COL (0x1U << 1)
  200. #define LAN91C96_EPHSR_MUL_COL (0x1U << 2)
  201. #define LAN91C96_EPHSR_LTX_MULT (0x1U << 3)
  202. #define LAN91C96_EPHSR_16COL (0x1U << 4)
  203. #define LAN91C96_EPHSR_SQET (0x1U << 5)
  204. #define LAN91C96_EPHSR_LTX_BRD (0x1U << 6)
  205. #define LAN91C96_EPHSR_TX_DEFR (0x1U << 7)
  206. #define LAN91C96_EPHSR_WAKEUP (0x1U << 8)
  207. #define LAN91C96_EPHSR_LATCOL (0x1U << 9)
  208. #define LAN91C96_EPHSR_LOST_CARR (0x1U << 10)
  209. #define LAN91C96_EPHSR_EXC_DEF (0x1U << 11)
  210. #define LAN91C96_EPHSR_CTR_ROL (0x1U << 12)
  211. #define LAN91C96_EPHSR_LINK_OK (0x1U << 14)
  212. #define LAN91C96_EPHSR_TX_UNRN (0x1U << 15)
  213. #define LAN91C96_EPHSR_ERRORS (LAN91C96_EPHSR_SNGL_COL | \
  214. LAN91C96_EPHSR_MUL_COL | \
  215. LAN91C96_EPHSR_16COL | \
  216. LAN91C96_EPHSR_SQET | \
  217. LAN91C96_EPHSR_TX_DEFR | \
  218. LAN91C96_EPHSR_LATCOL | \
  219. LAN91C96_EPHSR_LOST_CARR | \
  220. LAN91C96_EPHSR_EXC_DEF | \
  221. LAN91C96_EPHSR_LINK_OK | \
  222. LAN91C96_EPHSR_TX_UNRN)
  223. /*
  224. ****************************************************************************
  225. * Receive Control Register - Bank 0 - Offset 4
  226. ****************************************************************************
  227. */
  228. #define LAN91C96_RCR_RX_ABORT (0x1U << 0)
  229. #define LAN91C96_RCR_PRMS (0x1U << 1)
  230. #define LAN91C96_RCR_ALMUL (0x1U << 2)
  231. #define LAN91C96_RCR_RXEN (0x1U << 8)
  232. #define LAN91C96_RCR_STRIP_CRC (0x1U << 9)
  233. #define LAN91C96_RCR_FILT_CAR (0x1U << 14)
  234. #define LAN91C96_RCR_SOFT_RST (0x1U << 15)
  235. /*
  236. ****************************************************************************
  237. * Counter Register - Bank 0 - Offset 6
  238. ****************************************************************************
  239. */
  240. #define LAN91C96_ECR_SNGL_COL (0xFU << 0)
  241. #define LAN91C96_ECR_MULT_COL (0xFU << 5)
  242. #define LAN91C96_ECR_DEF_TX (0xFU << 8)
  243. #define LAN91C96_ECR_EXC_DEF_TX (0xFU << 12)
  244. /*
  245. ****************************************************************************
  246. * Memory Information Register - Bank 0 - OFfset 8
  247. ****************************************************************************
  248. */
  249. #define LAN91C96_MIR_SIZE (0x18 << 0) /* 6144 bytes */
  250. /*
  251. ****************************************************************************
  252. * Memory Configuration Register - Bank 0 - Offset 10
  253. ****************************************************************************
  254. */
  255. #define LAN91C96_MCR_MEM_RES (0xFFU << 0)
  256. #define LAN91C96_MCR_MEM_MULT (0x3U << 9)
  257. #define LAN91C96_MCR_HIGH_ID (0x3U << 12)
  258. #define LAN91C96_MCR_TRANSMIT_PAGES 0x6
  259. /*
  260. ****************************************************************************
  261. * Bank 1 Register Map in I/O Space
  262. ****************************************************************************
  263. */
  264. #define LAN91C96_CONFIG 0 /* Configuration Register */
  265. #define LAN91C96_BASE 2 /* Base Address Register */
  266. #define LAN91C96_IA0 4 /* Individual Address Register - 0 */
  267. #define LAN91C96_IA1 5 /* Individual Address Register - 1 */
  268. #define LAN91C96_IA2 6 /* Individual Address Register - 2 */
  269. #define LAN91C96_IA3 7 /* Individual Address Register - 3 */
  270. #define LAN91C96_IA4 8 /* Individual Address Register - 4 */
  271. #define LAN91C96_IA5 9 /* Individual Address Register - 5 */
  272. #define LAN91C96_GEN_PURPOSE 10 /* General Address Registers */
  273. #define LAN91C96_CONTROL 12 /* Control Register */
  274. /*
  275. ****************************************************************************
  276. * Configuration Register - Bank 1 - Offset 0
  277. ****************************************************************************
  278. */
  279. #define LAN91C96_CR_INT_SEL0 (0x1U << 1)
  280. #define LAN91C96_CR_INT_SEL1 (0x1U << 2)
  281. #define LAN91C96_CR_RES (0x3U << 3)
  282. #define LAN91C96_CR_DIS_LINK (0x1U << 6)
  283. #define LAN91C96_CR_16BIT (0x1U << 7)
  284. #define LAN91C96_CR_AUI_SELECT (0x1U << 8)
  285. #define LAN91C96_CR_SET_SQLCH (0x1U << 9)
  286. #define LAN91C96_CR_FULL_STEP (0x1U << 10)
  287. #define LAN91C96_CR_NO_WAIT (0x1U << 12)
  288. /*
  289. ****************************************************************************
  290. * Base Address Register - Bank 1 - Offset 2
  291. ****************************************************************************
  292. */
  293. #define LAN91C96_BAR_RA_BITS (0x27U << 0)
  294. #define LAN91C96_BAR_ROM_SIZE (0x1U << 6)
  295. #define LAN91C96_BAR_A_BITS (0xFFU << 8)
  296. /*
  297. ****************************************************************************
  298. * Control Register - Bank 1 - Offset 12
  299. ****************************************************************************
  300. */
  301. #define LAN91C96_CTR_STORE (0x1U << 0)
  302. #define LAN91C96_CTR_RELOAD (0x1U << 1)
  303. #define LAN91C96_CTR_EEPROM (0x1U << 2)
  304. #define LAN91C96_CTR_TE_ENABLE (0x1U << 5)
  305. #define LAN91C96_CTR_CR_ENABLE (0x1U << 6)
  306. #define LAN91C96_CTR_LE_ENABLE (0x1U << 7)
  307. #define LAN91C96_CTR_BIT_8 (0x1U << 8)
  308. #define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11)
  309. #define LAN91C96_CTR_WAKEUP_EN (0x1U << 12)
  310. #define LAN91C96_CTR_PWRDN (0x1U << 13)
  311. #define LAN91C96_CTR_RCV_BAD (0x1U << 14)
  312. /*
  313. ****************************************************************************
  314. * Bank 2 Register Map in I/O Space
  315. ****************************************************************************
  316. */
  317. #define LAN91C96_MMU 0 /* MMU Command Register */
  318. #define LAN91C96_AUTO_TX_START 1 /* Auto Tx Start Register */
  319. #define LAN91C96_PNR 2 /* Packet Number Register */
  320. #define LAN91C96_ARR 3 /* Allocation Result Register */
  321. #define LAN91C96_FIFO 4 /* FIFO Ports Register */
  322. #define LAN91C96_POINTER 6 /* Pointer Register */
  323. #define LAN91C96_DATA_HIGH 8 /* Data High Register */
  324. #define LAN91C96_DATA_LOW 10 /* Data Low Register */
  325. #define LAN91C96_INT_STATS 12 /* Interrupt Status Register - RO */
  326. #define LAN91C96_INT_ACK 12 /* Interrupt Acknowledge Register -WO */
  327. #define LAN91C96_INT_MASK 13 /* Interrupt Mask Register */
  328. /*
  329. ****************************************************************************
  330. * MMU Command Register - Bank 2 - Offset 0
  331. ****************************************************************************
  332. */
  333. #define LAN91C96_MMUCR_NO_BUSY (0x1U << 0)
  334. #define LAN91C96_MMUCR_N1 (0x1U << 1)
  335. #define LAN91C96_MMUCR_N2 (0x1U << 2)
  336. #define LAN91C96_MMUCR_COMMAND (0xFU << 4)
  337. #define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) /* WXYZ = 0010 */
  338. #define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) /* WXYZ = 0100 */
  339. #define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) /* WXYZ = 0110 */
  340. #define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) /* WXYZ = 0111 */
  341. #define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) /* WXYZ = 1000 */
  342. #define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) /* WXYZ = 1010 */
  343. #define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) /* WXYZ = 1100 */
  344. #define LAN91C96_MMUCR_RESET_TX (0xEU << 4) /* WXYZ = 1110 */
  345. /*
  346. ****************************************************************************
  347. * Auto Tx Start Register - Bank 2 - Offset 1
  348. ****************************************************************************
  349. */
  350. #define LAN91C96_AUTOTX (0xFFU << 0)
  351. /*
  352. ****************************************************************************
  353. * Packet Number Register - Bank 2 - Offset 2
  354. ****************************************************************************
  355. */
  356. #define LAN91C96_PNR_TX (0x1FU << 0)
  357. /*
  358. ****************************************************************************
  359. * Allocation Result Register - Bank 2 - Offset 3
  360. ****************************************************************************
  361. */
  362. #define LAN91C96_ARR_ALLOC_PN (0x7FU << 0)
  363. #define LAN91C96_ARR_FAILED (0x1U << 7)
  364. /*
  365. ****************************************************************************
  366. * FIFO Ports Register - Bank 2 - Offset 4
  367. ****************************************************************************
  368. */
  369. #define LAN91C96_FIFO_TX_DONE_PN (0x1FU << 0)
  370. #define LAN91C96_FIFO_TEMPTY (0x1U << 7)
  371. #define LAN91C96_FIFO_RX_DONE_PN (0x1FU << 8)
  372. #define LAN91C96_FIFO_RXEMPTY (0x1U << 15)
  373. /*
  374. ****************************************************************************
  375. * Pointer Register - Bank 2 - Offset 6
  376. ****************************************************************************
  377. */
  378. #define LAN91C96_PTR_LOW (0xFFU << 0)
  379. #define LAN91C96_PTR_HIGH (0x7U << 8)
  380. #define LAN91C96_PTR_AUTO_TX (0x1U << 11)
  381. #define LAN91C96_PTR_ETEN (0x1U << 12)
  382. #define LAN91C96_PTR_READ (0x1U << 13)
  383. #define LAN91C96_PTR_AUTO_INCR (0x1U << 14)
  384. #define LAN91C96_PTR_RCV (0x1U << 15)
  385. #define LAN91C96_PTR_RX_FRAME (LAN91C96_PTR_RCV | \
  386. LAN91C96_PTR_AUTO_INCR | \
  387. LAN91C96_PTR_READ)
  388. /*
  389. ****************************************************************************
  390. * Data Register - Bank 2 - Offset 8
  391. ****************************************************************************
  392. */
  393. #define LAN91C96_CONTROL_CRC (0x1U << 4) /* CRC bit */
  394. #define LAN91C96_CONTROL_ODD (0x1U << 5) /* ODD bit */
  395. /*
  396. ****************************************************************************
  397. * Interrupt Status Register - Bank 2 - Offset 12
  398. ****************************************************************************
  399. */
  400. #define LAN91C96_IST_RCV_INT (0x1U << 0)
  401. #define LAN91C96_IST_TX_INT (0x1U << 1)
  402. #define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2)
  403. #define LAN91C96_IST_ALLOC_INT (0x1U << 3)
  404. #define LAN91C96_IST_RX_OVRN_INT (0x1U << 4)
  405. #define LAN91C96_IST_EPH_INT (0x1U << 5)
  406. #define LAN91C96_IST_ERCV_INT (0x1U << 6)
  407. #define LAN91C96_IST_RX_IDLE_INT (0x1U << 7)
  408. /*
  409. ****************************************************************************
  410. * Interrupt Acknowledge Register - Bank 2 - Offset 12
  411. ****************************************************************************
  412. */
  413. #define LAN91C96_ACK_TX_INT (0x1U << 1)
  414. #define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2)
  415. #define LAN91C96_ACK_RX_OVRN_INT (0x1U << 4)
  416. #define LAN91C96_ACK_ERCV_INT (0x1U << 6)
  417. /*
  418. ****************************************************************************
  419. * Interrupt Mask Register - Bank 2 - Offset 13
  420. ****************************************************************************
  421. */
  422. #define LAN91C96_MSK_RCV_INT (0x1U << 0)
  423. #define LAN91C96_MSK_TX_INT (0x1U << 1)
  424. #define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2)
  425. #define LAN91C96_MSK_ALLOC_INT (0x1U << 3)
  426. #define LAN91C96_MSK_RX_OVRN_INT (0x1U << 4)
  427. #define LAN91C96_MSK_EPH_INT (0x1U << 5)
  428. #define LAN91C96_MSK_ERCV_INT (0x1U << 6)
  429. #define LAN91C96_MSK_TX_IDLE_INT (0x1U << 7)
  430. /*
  431. ****************************************************************************
  432. * Bank 3 Register Map in I/O Space
  433. **************************************************************************
  434. */
  435. #define LAN91C96_MGMT_MDO (0x1U << 0)
  436. #define LAN91C96_MGMT_MDI (0x1U << 1)
  437. #define LAN91C96_MGMT_MCLK (0x1U << 2)
  438. #define LAN91C96_MGMT_MDOE (0x1U << 3)
  439. #define LAN91C96_MGMT_LOW_ID (0x3U << 4)
  440. #define LAN91C96_MGMT_IOS0 (0x1U << 8)
  441. #define LAN91C96_MGMT_IOS1 (0x1U << 9)
  442. #define LAN91C96_MGMT_IOS2 (0x1U << 10)
  443. #define LAN91C96_MGMT_nXNDEC (0x1U << 11)
  444. #define LAN91C96_MGMT_HIGH_ID (0x3U << 12)
  445. /*
  446. ****************************************************************************
  447. * Revision Register - Bank 3 - Offset 10
  448. ****************************************************************************
  449. */
  450. #define LAN91C96_REV_REVID (0xFU << 0)
  451. #define LAN91C96_REV_CHIPID (0xFU << 4)
  452. /*
  453. ****************************************************************************
  454. * Early RCV Register - Bank 3 - Offset 12
  455. ****************************************************************************
  456. */
  457. #define LAN91C96_ERCV_THRESHOLD (0x1FU << 0)
  458. #define LAN91C96_ERCV_RCV_DISCRD (0x1U << 7)
  459. /*
  460. ****************************************************************************
  461. * PCMCIA Configuration Registers
  462. ****************************************************************************
  463. */
  464. #define LAN91C96_ECOR 0x8000 /* Ethernet Configuration Register */
  465. #define LAN91C96_ECSR 0x8002 /* Ethernet Configuration and Status */
  466. /*
  467. ****************************************************************************
  468. * PCMCIA Ethernet Configuration Option Register (ECOR)
  469. ****************************************************************************
  470. */
  471. #define LAN91C96_ECOR_ENABLE (0x1U << 0)
  472. #define LAN91C96_ECOR_WR_ATTRIB (0x1U << 2)
  473. #define LAN91C96_ECOR_LEVEL_REQ (0x1U << 6)
  474. #define LAN91C96_ECOR_SRESET (0x1U << 7)
  475. /*
  476. ****************************************************************************
  477. * PCMCIA Ethernet Configuration and Status Register (ECSR)
  478. ****************************************************************************
  479. */
  480. #define LAN91C96_ECSR_INTR (0x1U << 1)
  481. #define LAN91C96_ECSR_PWRDWN (0x1U << 2)
  482. #define LAN91C96_ECSR_IOIS8 (0x1U << 5)
  483. /*
  484. ****************************************************************************
  485. * Receive Frame Status Word - See page 38 of the LAN91C96 specification.
  486. ****************************************************************************
  487. */
  488. #define LAN91C96_TOO_SHORT (0x1U << 10)
  489. #define LAN91C96_TOO_LONG (0x1U << 11)
  490. #define LAN91C96_ODD_FRM (0x1U << 12)
  491. #define LAN91C96_BAD_CRC (0x1U << 13)
  492. #define LAN91C96_BROD_CAST (0x1U << 14)
  493. #define LAN91C96_ALGN_ERR (0x1U << 15)
  494. #define FRAME_FILTER (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG | LAN91C96_BAD_CRC | LAN91C96_ALGN_ERR)
  495. /*
  496. ****************************************************************************
  497. * Default MAC Address
  498. ****************************************************************************
  499. */
  500. #define MAC_DEF_HI 0x0800
  501. #define MAC_DEF_MED 0x3333
  502. #define MAC_DEF_LO 0x0100
  503. /*
  504. ****************************************************************************
  505. * Default I/O Signature - 0x33
  506. ****************************************************************************
  507. */
  508. #define LAN91C96_LOW_SIGNATURE (0x33U << 0)
  509. #define LAN91C96_HIGH_SIGNATURE (0x33U << 8)
  510. #define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE)
  511. #define LAN91C96_MAX_PAGES 6 /* Maximum number of 256 pages. */
  512. #define ETHERNET_MAX_LENGTH 1514
  513. /*-------------------------------------------------------------------------
  514. * I define some macros to make it easier to do somewhat common
  515. * or slightly complicated, repeated tasks.
  516. *-------------------------------------------------------------------------
  517. */
  518. /* select a register bank, 0 to 3 */
  519. #define SMC_SELECT_BANK(edev, x) { SMC_outw(edev, x, LAN91C96_BANK_SELECT); }
  520. /* this enables an interrupt in the interrupt mask register */
  521. #define SMC_ENABLE_INT(edev, x) {\
  522. unsigned char mask;\
  523. SMC_SELECT_BANK(edev, 2);\
  524. mask = SMC_inb(edev, LAN91C96_INT_MASK);\
  525. mask |= (x);\
  526. SMC_outb(edev, mask, LAN91C96_INT_MASK); \
  527. }
  528. /* this disables an interrupt from the interrupt mask register */
  529. #define SMC_DISABLE_INT(edev, x) {\
  530. unsigned char mask;\
  531. SMC_SELECT_BANK(edev, 2);\
  532. mask = SMC_inb(edev, LAN91C96_INT_MASK);\
  533. mask &= ~(x);\
  534. SMC_outb(edev, mask, LAN91C96_INT_MASK); \
  535. }
  536. /*----------------------------------------------------------------------
  537. * Define the interrupts that I want to receive from the card
  538. *
  539. * I want:
  540. * LAN91C96_IST_EPH_INT, for nasty errors
  541. * LAN91C96_IST_RCV_INT, for happy received packets
  542. * LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver
  543. *-------------------------------------------------------------------------
  544. */
  545. #define SMC_INTERRUPT_MASK (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT)
  546. #endif /* _LAN91C96_H_ */