gmac_rockchip.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
  4. *
  5. * Rockchip GMAC ethernet IP driver for U-Boot
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <clk.h>
  10. #include <log.h>
  11. #include <net.h>
  12. #include <phy.h>
  13. #include <syscon.h>
  14. #include <asm/global_data.h>
  15. #include <asm/io.h>
  16. #include <asm/arch-rockchip/periph.h>
  17. #include <asm/arch-rockchip/clock.h>
  18. #include <asm/arch-rockchip/hardware.h>
  19. #include <asm/arch-rockchip/grf_px30.h>
  20. #include <asm/arch-rockchip/grf_rk322x.h>
  21. #include <asm/arch-rockchip/grf_rk3288.h>
  22. #include <asm/arch-rk3308/grf_rk3308.h>
  23. #include <asm/arch-rockchip/grf_rk3328.h>
  24. #include <asm/arch-rockchip/grf_rk3368.h>
  25. #include <asm/arch-rockchip/grf_rk3399.h>
  26. #include <asm/arch-rockchip/grf_rv1108.h>
  27. #include <dm/pinctrl.h>
  28. #include <dt-bindings/clock/rk3288-cru.h>
  29. #include <linux/bitops.h>
  30. #include "designware.h"
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #define DELAY_ENABLE(soc, tx, rx) \
  33. (((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
  34. ((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
  35. /*
  36. * Platform data for the gmac
  37. *
  38. * dw_eth_pdata: Required platform data for designware driver (must be first)
  39. */
  40. struct gmac_rockchip_plat {
  41. struct dw_eth_pdata dw_eth_pdata;
  42. bool clock_input;
  43. int tx_delay;
  44. int rx_delay;
  45. };
  46. struct rk_gmac_ops {
  47. int (*fix_mac_speed)(struct dw_eth_dev *priv);
  48. void (*set_to_rmii)(struct gmac_rockchip_plat *pdata);
  49. void (*set_to_rgmii)(struct gmac_rockchip_plat *pdata);
  50. };
  51. static int gmac_rockchip_of_to_plat(struct udevice *dev)
  52. {
  53. struct gmac_rockchip_plat *pdata = dev_get_plat(dev);
  54. const char *string;
  55. string = dev_read_string(dev, "clock_in_out");
  56. if (!strcmp(string, "input"))
  57. pdata->clock_input = true;
  58. else
  59. pdata->clock_input = false;
  60. /* Check the new naming-style first... */
  61. pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
  62. pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
  63. /* ... and fall back to the old naming style or default, if necessary */
  64. if (pdata->tx_delay == -ENOENT)
  65. pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30);
  66. if (pdata->rx_delay == -ENOENT)
  67. pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
  68. return designware_eth_of_to_plat(dev);
  69. }
  70. static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  71. {
  72. struct px30_grf *grf;
  73. struct clk clk_speed;
  74. int speed, ret;
  75. enum {
  76. PX30_GMAC_SPEED_SHIFT = 0x2,
  77. PX30_GMAC_SPEED_MASK = BIT(2),
  78. PX30_GMAC_SPEED_10M = 0,
  79. PX30_GMAC_SPEED_100M = BIT(2),
  80. };
  81. ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
  82. &clk_speed);
  83. if (ret)
  84. return ret;
  85. switch (priv->phydev->speed) {
  86. case 10:
  87. speed = PX30_GMAC_SPEED_10M;
  88. ret = clk_set_rate(&clk_speed, 2500000);
  89. if (ret)
  90. return ret;
  91. break;
  92. case 100:
  93. speed = PX30_GMAC_SPEED_100M;
  94. ret = clk_set_rate(&clk_speed, 25000000);
  95. if (ret)
  96. return ret;
  97. break;
  98. default:
  99. debug("Unknown phy speed: %d\n", priv->phydev->speed);
  100. return -EINVAL;
  101. }
  102. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  103. rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed);
  104. return 0;
  105. }
  106. static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  107. {
  108. struct rk322x_grf *grf;
  109. int clk;
  110. enum {
  111. RK3228_GMAC_CLK_SEL_SHIFT = 8,
  112. RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8),
  113. RK3228_GMAC_CLK_SEL_125M = 0 << 8,
  114. RK3228_GMAC_CLK_SEL_25M = 3 << 8,
  115. RK3228_GMAC_CLK_SEL_2_5M = 2 << 8,
  116. };
  117. switch (priv->phydev->speed) {
  118. case 10:
  119. clk = RK3228_GMAC_CLK_SEL_2_5M;
  120. break;
  121. case 100:
  122. clk = RK3228_GMAC_CLK_SEL_25M;
  123. break;
  124. case 1000:
  125. clk = RK3228_GMAC_CLK_SEL_125M;
  126. break;
  127. default:
  128. debug("Unknown phy speed: %d\n", priv->phydev->speed);
  129. return -EINVAL;
  130. }
  131. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  132. rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk);
  133. return 0;
  134. }
  135. static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  136. {
  137. struct rk3288_grf *grf;
  138. int clk;
  139. switch (priv->phydev->speed) {
  140. case 10:
  141. clk = RK3288_GMAC_CLK_SEL_2_5M;
  142. break;
  143. case 100:
  144. clk = RK3288_GMAC_CLK_SEL_25M;
  145. break;
  146. case 1000:
  147. clk = RK3288_GMAC_CLK_SEL_125M;
  148. break;
  149. default:
  150. debug("Unknown phy speed: %d\n", priv->phydev->speed);
  151. return -EINVAL;
  152. }
  153. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  154. rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
  155. return 0;
  156. }
  157. static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  158. {
  159. struct rk3308_grf *grf;
  160. struct clk clk_speed;
  161. int speed, ret;
  162. enum {
  163. RK3308_GMAC_SPEED_SHIFT = 0x0,
  164. RK3308_GMAC_SPEED_MASK = BIT(0),
  165. RK3308_GMAC_SPEED_10M = 0,
  166. RK3308_GMAC_SPEED_100M = BIT(0),
  167. };
  168. ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
  169. &clk_speed);
  170. if (ret)
  171. return ret;
  172. switch (priv->phydev->speed) {
  173. case 10:
  174. speed = RK3308_GMAC_SPEED_10M;
  175. ret = clk_set_rate(&clk_speed, 2500000);
  176. if (ret)
  177. return ret;
  178. break;
  179. case 100:
  180. speed = RK3308_GMAC_SPEED_100M;
  181. ret = clk_set_rate(&clk_speed, 25000000);
  182. if (ret)
  183. return ret;
  184. break;
  185. default:
  186. debug("Unknown phy speed: %d\n", priv->phydev->speed);
  187. return -EINVAL;
  188. }
  189. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  190. rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed);
  191. return 0;
  192. }
  193. static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  194. {
  195. struct rk3328_grf_regs *grf;
  196. int clk;
  197. enum {
  198. RK3328_GMAC_CLK_SEL_SHIFT = 11,
  199. RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11),
  200. RK3328_GMAC_CLK_SEL_125M = 0 << 11,
  201. RK3328_GMAC_CLK_SEL_25M = 3 << 11,
  202. RK3328_GMAC_CLK_SEL_2_5M = 2 << 11,
  203. };
  204. switch (priv->phydev->speed) {
  205. case 10:
  206. clk = RK3328_GMAC_CLK_SEL_2_5M;
  207. break;
  208. case 100:
  209. clk = RK3328_GMAC_CLK_SEL_25M;
  210. break;
  211. case 1000:
  212. clk = RK3328_GMAC_CLK_SEL_125M;
  213. break;
  214. default:
  215. debug("Unknown phy speed: %d\n", priv->phydev->speed);
  216. return -EINVAL;
  217. }
  218. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  219. rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
  220. return 0;
  221. }
  222. static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  223. {
  224. struct rk3368_grf *grf;
  225. int clk;
  226. enum {
  227. RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
  228. RK3368_GMAC_CLK_SEL_25M = 3 << 4,
  229. RK3368_GMAC_CLK_SEL_125M = 0 << 4,
  230. RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
  231. };
  232. switch (priv->phydev->speed) {
  233. case 10:
  234. clk = RK3368_GMAC_CLK_SEL_2_5M;
  235. break;
  236. case 100:
  237. clk = RK3368_GMAC_CLK_SEL_25M;
  238. break;
  239. case 1000:
  240. clk = RK3368_GMAC_CLK_SEL_125M;
  241. break;
  242. default:
  243. debug("Unknown phy speed: %d\n", priv->phydev->speed);
  244. return -EINVAL;
  245. }
  246. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  247. rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
  248. return 0;
  249. }
  250. static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  251. {
  252. struct rk3399_grf_regs *grf;
  253. int clk;
  254. switch (priv->phydev->speed) {
  255. case 10:
  256. clk = RK3399_GMAC_CLK_SEL_2_5M;
  257. break;
  258. case 100:
  259. clk = RK3399_GMAC_CLK_SEL_25M;
  260. break;
  261. case 1000:
  262. clk = RK3399_GMAC_CLK_SEL_125M;
  263. break;
  264. default:
  265. debug("Unknown phy speed: %d\n", priv->phydev->speed);
  266. return -EINVAL;
  267. }
  268. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  269. rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);
  270. return 0;
  271. }
  272. static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
  273. {
  274. struct rv1108_grf *grf;
  275. int clk, speed;
  276. enum {
  277. RV1108_GMAC_SPEED_MASK = BIT(2),
  278. RV1108_GMAC_SPEED_10M = 0 << 2,
  279. RV1108_GMAC_SPEED_100M = 1 << 2,
  280. RV1108_GMAC_CLK_SEL_MASK = BIT(7),
  281. RV1108_GMAC_CLK_SEL_2_5M = 0 << 7,
  282. RV1108_GMAC_CLK_SEL_25M = 1 << 7,
  283. };
  284. switch (priv->phydev->speed) {
  285. case 10:
  286. clk = RV1108_GMAC_CLK_SEL_2_5M;
  287. speed = RV1108_GMAC_SPEED_10M;
  288. break;
  289. case 100:
  290. clk = RV1108_GMAC_CLK_SEL_25M;
  291. speed = RV1108_GMAC_SPEED_100M;
  292. break;
  293. default:
  294. debug("Unknown phy speed: %d\n", priv->phydev->speed);
  295. return -EINVAL;
  296. }
  297. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  298. rk_clrsetreg(&grf->gmac_con0,
  299. RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
  300. clk | speed);
  301. return 0;
  302. }
  303. static void px30_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
  304. {
  305. struct px30_grf *grf;
  306. enum {
  307. PX30_GMAC_PHY_INTF_SEL_SHIFT = 4,
  308. PX30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6),
  309. PX30_GMAC_PHY_INTF_SEL_RMII = BIT(6),
  310. };
  311. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  312. rk_clrsetreg(&grf->mac_con1,
  313. PX30_GMAC_PHY_INTF_SEL_MASK,
  314. PX30_GMAC_PHY_INTF_SEL_RMII);
  315. }
  316. static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
  317. {
  318. struct rk322x_grf *grf;
  319. enum {
  320. RK3228_RMII_MODE_SHIFT = 10,
  321. RK3228_RMII_MODE_MASK = BIT(10),
  322. RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
  323. RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
  324. RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
  325. RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
  326. RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
  327. RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
  328. RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
  329. RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
  330. RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
  331. };
  332. enum {
  333. RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
  334. RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
  335. RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
  336. RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
  337. };
  338. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  339. rk_clrsetreg(&grf->mac_con[1],
  340. RK3228_RMII_MODE_MASK |
  341. RK3228_GMAC_PHY_INTF_SEL_MASK |
  342. RK3228_RXCLK_DLY_ENA_GMAC_MASK |
  343. RK3228_TXCLK_DLY_ENA_GMAC_MASK,
  344. RK3228_GMAC_PHY_INTF_SEL_RGMII |
  345. DELAY_ENABLE(RK3228, pdata->tx_delay, pdata->rx_delay));
  346. rk_clrsetreg(&grf->mac_con[0],
  347. RK3228_CLK_RX_DL_CFG_GMAC_MASK |
  348. RK3228_CLK_TX_DL_CFG_GMAC_MASK,
  349. pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
  350. pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
  351. }
  352. static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
  353. {
  354. struct rk3288_grf *grf;
  355. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  356. rk_clrsetreg(&grf->soc_con1,
  357. RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,
  358. RK3288_GMAC_PHY_INTF_SEL_RGMII);
  359. rk_clrsetreg(&grf->soc_con3,
  360. RK3288_RXCLK_DLY_ENA_GMAC_MASK |
  361. RK3288_TXCLK_DLY_ENA_GMAC_MASK |
  362. RK3288_CLK_RX_DL_CFG_GMAC_MASK |
  363. RK3288_CLK_TX_DL_CFG_GMAC_MASK,
  364. DELAY_ENABLE(RK3288, pdata->rx_delay, pdata->tx_delay) |
  365. pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
  366. pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
  367. }
  368. static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
  369. {
  370. struct rk3308_grf *grf;
  371. enum {
  372. RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2,
  373. RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2),
  374. RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4),
  375. };
  376. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  377. rk_clrsetreg(&grf->mac_con0,
  378. RK3308_GMAC_PHY_INTF_SEL_MASK,
  379. RK3308_GMAC_PHY_INTF_SEL_RMII);
  380. }
  381. static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
  382. {
  383. struct rk3328_grf_regs *grf;
  384. enum {
  385. RK3328_RMII_MODE_SHIFT = 9,
  386. RK3328_RMII_MODE_MASK = BIT(9),
  387. RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
  388. RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
  389. RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
  390. RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
  391. RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
  392. RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
  393. RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
  394. RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
  395. RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
  396. };
  397. enum {
  398. RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
  399. RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
  400. RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
  401. RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
  402. };
  403. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  404. rk_clrsetreg(&grf->mac_con[1],
  405. RK3328_RMII_MODE_MASK |
  406. RK3328_GMAC_PHY_INTF_SEL_MASK |
  407. RK3328_RXCLK_DLY_ENA_GMAC_MASK |
  408. RK3328_TXCLK_DLY_ENA_GMAC_MASK,
  409. RK3328_GMAC_PHY_INTF_SEL_RGMII |
  410. DELAY_ENABLE(RK3328, pdata->tx_delay, pdata->rx_delay));
  411. rk_clrsetreg(&grf->mac_con[0],
  412. RK3328_CLK_RX_DL_CFG_GMAC_MASK |
  413. RK3328_CLK_TX_DL_CFG_GMAC_MASK,
  414. pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
  415. pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
  416. }
  417. static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
  418. {
  419. struct rk3368_grf *grf;
  420. enum {
  421. RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
  422. RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
  423. RK3368_RMII_MODE_MASK = BIT(6),
  424. RK3368_RMII_MODE = BIT(6),
  425. };
  426. enum {
  427. RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
  428. RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
  429. RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
  430. RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
  431. RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
  432. RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
  433. RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
  434. RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
  435. RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
  436. RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
  437. };
  438. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  439. rk_clrsetreg(&grf->soc_con15,
  440. RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
  441. RK3368_GMAC_PHY_INTF_SEL_RGMII);
  442. rk_clrsetreg(&grf->soc_con16,
  443. RK3368_RXCLK_DLY_ENA_GMAC_MASK |
  444. RK3368_TXCLK_DLY_ENA_GMAC_MASK |
  445. RK3368_CLK_RX_DL_CFG_GMAC_MASK |
  446. RK3368_CLK_TX_DL_CFG_GMAC_MASK,
  447. DELAY_ENABLE(RK3368, pdata->tx_delay, pdata->rx_delay) |
  448. pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
  449. pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
  450. }
  451. static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
  452. {
  453. struct rk3399_grf_regs *grf;
  454. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  455. rk_clrsetreg(&grf->soc_con5,
  456. RK3399_GMAC_PHY_INTF_SEL_MASK,
  457. RK3399_GMAC_PHY_INTF_SEL_RGMII);
  458. rk_clrsetreg(&grf->soc_con6,
  459. RK3399_RXCLK_DLY_ENA_GMAC_MASK |
  460. RK3399_TXCLK_DLY_ENA_GMAC_MASK |
  461. RK3399_CLK_RX_DL_CFG_GMAC_MASK |
  462. RK3399_CLK_TX_DL_CFG_GMAC_MASK,
  463. DELAY_ENABLE(RK3399, pdata->tx_delay, pdata->rx_delay) |
  464. pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
  465. pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
  466. }
  467. static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
  468. {
  469. struct rv1108_grf *grf;
  470. enum {
  471. RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
  472. RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4,
  473. };
  474. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  475. rk_clrsetreg(&grf->gmac_con0,
  476. RV1108_GMAC_PHY_INTF_SEL_MASK,
  477. RV1108_GMAC_PHY_INTF_SEL_RMII);
  478. }
  479. static int gmac_rockchip_probe(struct udevice *dev)
  480. {
  481. struct gmac_rockchip_plat *pdata = dev_get_plat(dev);
  482. struct rk_gmac_ops *ops =
  483. (struct rk_gmac_ops *)dev_get_driver_data(dev);
  484. struct dw_eth_pdata *dw_pdata = dev_get_plat(dev);
  485. struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata;
  486. struct clk clk;
  487. ulong rate;
  488. int ret;
  489. ret = clk_set_defaults(dev, CLK_DEFAULTS_PRE);
  490. if (ret)
  491. debug("%s clk_set_defaults failed %d\n", __func__, ret);
  492. ret = clk_get_by_index(dev, 0, &clk);
  493. if (ret)
  494. return ret;
  495. switch (eth_pdata->phy_interface) {
  496. case PHY_INTERFACE_MODE_RGMII:
  497. /* Set to RGMII mode */
  498. if (ops->set_to_rgmii)
  499. ops->set_to_rgmii(pdata);
  500. else
  501. return -EPERM;
  502. /*
  503. * If the gmac clock is from internal pll, need to set and
  504. * check the return value for gmac clock at RGMII mode. If
  505. * the gmac clock is from external source, the clock rate
  506. * is not set, because of it is bypassed.
  507. */
  508. if (!pdata->clock_input) {
  509. rate = clk_set_rate(&clk, 125000000);
  510. if (rate != 125000000)
  511. return -EINVAL;
  512. }
  513. break;
  514. case PHY_INTERFACE_MODE_RGMII_ID:
  515. /* Set to RGMII mode */
  516. if (ops->set_to_rgmii) {
  517. pdata->tx_delay = 0;
  518. pdata->rx_delay = 0;
  519. ops->set_to_rgmii(pdata);
  520. } else
  521. return -EPERM;
  522. if (!pdata->clock_input) {
  523. rate = clk_set_rate(&clk, 125000000);
  524. if (rate != 125000000)
  525. return -EINVAL;
  526. }
  527. break;
  528. case PHY_INTERFACE_MODE_RMII:
  529. /* Set to RMII mode */
  530. if (ops->set_to_rmii)
  531. ops->set_to_rmii(pdata);
  532. else
  533. return -EPERM;
  534. if (!pdata->clock_input) {
  535. rate = clk_set_rate(&clk, 50000000);
  536. if (rate != 50000000)
  537. return -EINVAL;
  538. }
  539. break;
  540. case PHY_INTERFACE_MODE_RGMII_RXID:
  541. /* Set to RGMII_RXID mode */
  542. if (ops->set_to_rgmii) {
  543. pdata->tx_delay = 0;
  544. ops->set_to_rgmii(pdata);
  545. } else
  546. return -EPERM;
  547. if (!pdata->clock_input) {
  548. rate = clk_set_rate(&clk, 125000000);
  549. if (rate != 125000000)
  550. return -EINVAL;
  551. }
  552. break;
  553. case PHY_INTERFACE_MODE_RGMII_TXID:
  554. /* Set to RGMII_TXID mode */
  555. if (ops->set_to_rgmii) {
  556. pdata->rx_delay = 0;
  557. ops->set_to_rgmii(pdata);
  558. } else
  559. return -EPERM;
  560. if (!pdata->clock_input) {
  561. rate = clk_set_rate(&clk, 125000000);
  562. if (rate != 125000000)
  563. return -EINVAL;
  564. }
  565. break;
  566. default:
  567. debug("NO interface defined!\n");
  568. return -ENXIO;
  569. }
  570. return designware_eth_probe(dev);
  571. }
  572. static int gmac_rockchip_eth_start(struct udevice *dev)
  573. {
  574. struct eth_pdata *pdata = dev_get_plat(dev);
  575. struct dw_eth_dev *priv = dev_get_priv(dev);
  576. struct rk_gmac_ops *ops =
  577. (struct rk_gmac_ops *)dev_get_driver_data(dev);
  578. int ret;
  579. ret = designware_eth_init(priv, pdata->enetaddr);
  580. if (ret)
  581. return ret;
  582. ret = ops->fix_mac_speed(priv);
  583. if (ret)
  584. return ret;
  585. ret = designware_eth_enable(priv);
  586. if (ret)
  587. return ret;
  588. return 0;
  589. }
  590. const struct eth_ops gmac_rockchip_eth_ops = {
  591. .start = gmac_rockchip_eth_start,
  592. .send = designware_eth_send,
  593. .recv = designware_eth_recv,
  594. .free_pkt = designware_eth_free_pkt,
  595. .stop = designware_eth_stop,
  596. .write_hwaddr = designware_eth_write_hwaddr,
  597. };
  598. const struct rk_gmac_ops px30_gmac_ops = {
  599. .fix_mac_speed = px30_gmac_fix_mac_speed,
  600. .set_to_rmii = px30_gmac_set_to_rmii,
  601. };
  602. const struct rk_gmac_ops rk3228_gmac_ops = {
  603. .fix_mac_speed = rk3228_gmac_fix_mac_speed,
  604. .set_to_rgmii = rk3228_gmac_set_to_rgmii,
  605. };
  606. const struct rk_gmac_ops rk3288_gmac_ops = {
  607. .fix_mac_speed = rk3288_gmac_fix_mac_speed,
  608. .set_to_rgmii = rk3288_gmac_set_to_rgmii,
  609. };
  610. const struct rk_gmac_ops rk3308_gmac_ops = {
  611. .fix_mac_speed = rk3308_gmac_fix_mac_speed,
  612. .set_to_rmii = rk3308_gmac_set_to_rmii,
  613. };
  614. const struct rk_gmac_ops rk3328_gmac_ops = {
  615. .fix_mac_speed = rk3328_gmac_fix_mac_speed,
  616. .set_to_rgmii = rk3328_gmac_set_to_rgmii,
  617. };
  618. const struct rk_gmac_ops rk3368_gmac_ops = {
  619. .fix_mac_speed = rk3368_gmac_fix_mac_speed,
  620. .set_to_rgmii = rk3368_gmac_set_to_rgmii,
  621. };
  622. const struct rk_gmac_ops rk3399_gmac_ops = {
  623. .fix_mac_speed = rk3399_gmac_fix_mac_speed,
  624. .set_to_rgmii = rk3399_gmac_set_to_rgmii,
  625. };
  626. const struct rk_gmac_ops rv1108_gmac_ops = {
  627. .fix_mac_speed = rv1108_set_rmii_speed,
  628. .set_to_rmii = rv1108_gmac_set_to_rmii,
  629. };
  630. static const struct udevice_id rockchip_gmac_ids[] = {
  631. { .compatible = "rockchip,px30-gmac",
  632. .data = (ulong)&px30_gmac_ops },
  633. { .compatible = "rockchip,rk3228-gmac",
  634. .data = (ulong)&rk3228_gmac_ops },
  635. { .compatible = "rockchip,rk3288-gmac",
  636. .data = (ulong)&rk3288_gmac_ops },
  637. { .compatible = "rockchip,rk3308-mac",
  638. .data = (ulong)&rk3308_gmac_ops },
  639. { .compatible = "rockchip,rk3328-gmac",
  640. .data = (ulong)&rk3328_gmac_ops },
  641. { .compatible = "rockchip,rk3368-gmac",
  642. .data = (ulong)&rk3368_gmac_ops },
  643. { .compatible = "rockchip,rk3399-gmac",
  644. .data = (ulong)&rk3399_gmac_ops },
  645. { .compatible = "rockchip,rv1108-gmac",
  646. .data = (ulong)&rv1108_gmac_ops },
  647. { }
  648. };
  649. U_BOOT_DRIVER(eth_gmac_rockchip) = {
  650. .name = "gmac_rockchip",
  651. .id = UCLASS_ETH,
  652. .of_match = rockchip_gmac_ids,
  653. .of_to_plat = gmac_rockchip_of_to_plat,
  654. .probe = gmac_rockchip_probe,
  655. .ops = &gmac_rockchip_eth_ops,
  656. .priv_auto = sizeof(struct dw_eth_dev),
  657. .plat_auto = sizeof(struct gmac_rockchip_plat),
  658. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  659. };