ftgmac100.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Faraday FTGMAC100 Ethernet
  4. *
  5. * (C) Copyright 2009 Faraday Technology
  6. * Po-Yu Chuang <ratbert@faraday-tech.com>
  7. *
  8. * (C) Copyright 2010 Andes Technology
  9. * Macpaul Lin <macpaul@andestech.com>
  10. *
  11. * Copyright (C) 2018, IBM Corporation.
  12. */
  13. #include <common.h>
  14. #include <clk.h>
  15. #include <cpu_func.h>
  16. #include <dm.h>
  17. #include <log.h>
  18. #include <malloc.h>
  19. #include <miiphy.h>
  20. #include <net.h>
  21. #include <wait_bit.h>
  22. #include <asm/cache.h>
  23. #include <dm/device_compat.h>
  24. #include <linux/bitops.h>
  25. #include <linux/io.h>
  26. #include <linux/iopoll.h>
  27. #include "ftgmac100.h"
  28. /* Min frame ethernet frame size without FCS */
  29. #define ETH_ZLEN 60
  30. /* Receive Buffer Size Register - HW default is 0x640 */
  31. #define FTGMAC100_RBSR_DEFAULT 0x640
  32. /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
  33. #define PKTBUFSTX 4 /* must be power of 2 */
  34. /* Timeout for transmit */
  35. #define FTGMAC100_TX_TIMEOUT_MS 1000
  36. /* Timeout for a mdio read/write operation */
  37. #define FTGMAC100_MDIO_TIMEOUT_USEC 10000
  38. /*
  39. * MDC clock cycle threshold
  40. *
  41. * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
  42. */
  43. #define MDC_CYCTHR 0x34
  44. /*
  45. * ftgmac100 model variants
  46. */
  47. enum ftgmac100_model {
  48. FTGMAC100_MODEL_FARADAY,
  49. FTGMAC100_MODEL_ASPEED,
  50. };
  51. /**
  52. * struct ftgmac100_data - private data for the FTGMAC100 driver
  53. *
  54. * @iobase: The base address of the hardware registers
  55. * @txdes: The array of transmit descriptors
  56. * @rxdes: The array of receive descriptors
  57. * @tx_index: Transmit descriptor index in @txdes
  58. * @rx_index: Receive descriptor index in @rxdes
  59. * @phy_addr: The PHY interface address to use
  60. * @phydev: The PHY device backing the MAC
  61. * @bus: The mdio bus
  62. * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
  63. * @max_speed: Maximum speed of Ethernet connection supported by MAC
  64. * @clks: The bulk of clocks assigned to the device in the DT
  65. * @rxdes0_edorr_mask: The bit number identifying the end of the RX ring buffer
  66. * @txdes0_edotr_mask: The bit number identifying the end of the TX ring buffer
  67. */
  68. struct ftgmac100_data {
  69. struct ftgmac100 *iobase;
  70. struct ftgmac100_txdes txdes[PKTBUFSTX] __aligned(ARCH_DMA_MINALIGN);
  71. struct ftgmac100_rxdes rxdes[PKTBUFSRX] __aligned(ARCH_DMA_MINALIGN);
  72. int tx_index;
  73. int rx_index;
  74. u32 phy_addr;
  75. struct phy_device *phydev;
  76. struct mii_dev *bus;
  77. u32 phy_mode;
  78. u32 max_speed;
  79. struct clk_bulk clks;
  80. /* End of RX/TX ring buffer bits. Depend on model */
  81. u32 rxdes0_edorr_mask;
  82. u32 txdes0_edotr_mask;
  83. };
  84. /*
  85. * struct mii_bus functions
  86. */
  87. static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
  88. int reg_addr)
  89. {
  90. struct ftgmac100_data *priv = bus->priv;
  91. struct ftgmac100 *ftgmac100 = priv->iobase;
  92. int phycr;
  93. int data;
  94. int ret;
  95. phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
  96. FTGMAC100_PHYCR_PHYAD(phy_addr) |
  97. FTGMAC100_PHYCR_REGAD(reg_addr) |
  98. FTGMAC100_PHYCR_MIIRD;
  99. writel(phycr, &ftgmac100->phycr);
  100. ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
  101. !(phycr & FTGMAC100_PHYCR_MIIRD),
  102. FTGMAC100_MDIO_TIMEOUT_USEC);
  103. if (ret) {
  104. pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
  105. priv->phydev->dev->name, phy_addr, reg_addr);
  106. return ret;
  107. }
  108. data = readl(&ftgmac100->phydata);
  109. return FTGMAC100_PHYDATA_MIIRDATA(data);
  110. }
  111. static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr,
  112. int reg_addr, u16 value)
  113. {
  114. struct ftgmac100_data *priv = bus->priv;
  115. struct ftgmac100 *ftgmac100 = priv->iobase;
  116. int phycr;
  117. int data;
  118. int ret;
  119. phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
  120. FTGMAC100_PHYCR_PHYAD(phy_addr) |
  121. FTGMAC100_PHYCR_REGAD(reg_addr) |
  122. FTGMAC100_PHYCR_MIIWR;
  123. data = FTGMAC100_PHYDATA_MIIWDATA(value);
  124. writel(data, &ftgmac100->phydata);
  125. writel(phycr, &ftgmac100->phycr);
  126. ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
  127. !(phycr & FTGMAC100_PHYCR_MIIWR),
  128. FTGMAC100_MDIO_TIMEOUT_USEC);
  129. if (ret) {
  130. pr_err("%s: mdio write failed (phy:%d reg:%x)\n",
  131. priv->phydev->dev->name, phy_addr, reg_addr);
  132. }
  133. return ret;
  134. }
  135. static int ftgmac100_mdio_init(struct udevice *dev)
  136. {
  137. struct ftgmac100_data *priv = dev_get_priv(dev);
  138. struct mii_dev *bus;
  139. int ret;
  140. bus = mdio_alloc();
  141. if (!bus)
  142. return -ENOMEM;
  143. bus->read = ftgmac100_mdio_read;
  144. bus->write = ftgmac100_mdio_write;
  145. bus->priv = priv;
  146. ret = mdio_register_seq(bus, dev_seq(dev));
  147. if (ret) {
  148. free(bus);
  149. return ret;
  150. }
  151. priv->bus = bus;
  152. return 0;
  153. }
  154. static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv)
  155. {
  156. struct ftgmac100 *ftgmac100 = priv->iobase;
  157. struct phy_device *phydev = priv->phydev;
  158. u32 maccr;
  159. if (!phydev->link) {
  160. dev_err(phydev->dev, "No link\n");
  161. return -EREMOTEIO;
  162. }
  163. /* read MAC control register and clear related bits */
  164. maccr = readl(&ftgmac100->maccr) &
  165. ~(FTGMAC100_MACCR_GIGA_MODE |
  166. FTGMAC100_MACCR_FAST_MODE |
  167. FTGMAC100_MACCR_FULLDUP);
  168. if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000)
  169. maccr |= FTGMAC100_MACCR_GIGA_MODE;
  170. if (phydev->speed == 100)
  171. maccr |= FTGMAC100_MACCR_FAST_MODE;
  172. if (phydev->duplex)
  173. maccr |= FTGMAC100_MACCR_FULLDUP;
  174. /* update MII config into maccr */
  175. writel(maccr, &ftgmac100->maccr);
  176. return 0;
  177. }
  178. static int ftgmac100_phy_init(struct udevice *dev)
  179. {
  180. struct ftgmac100_data *priv = dev_get_priv(dev);
  181. struct phy_device *phydev;
  182. int ret;
  183. phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
  184. if (!phydev)
  185. return -ENODEV;
  186. phydev->supported &= PHY_GBIT_FEATURES;
  187. if (priv->max_speed) {
  188. ret = phy_set_supported(phydev, priv->max_speed);
  189. if (ret)
  190. return ret;
  191. }
  192. phydev->advertising = phydev->supported;
  193. priv->phydev = phydev;
  194. phy_config(phydev);
  195. return 0;
  196. }
  197. /*
  198. * Reset MAC
  199. */
  200. static void ftgmac100_reset(struct ftgmac100_data *priv)
  201. {
  202. struct ftgmac100 *ftgmac100 = priv->iobase;
  203. debug("%s()\n", __func__);
  204. setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
  205. while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
  206. ;
  207. }
  208. /*
  209. * Set MAC address
  210. */
  211. static int ftgmac100_set_mac(struct ftgmac100_data *priv,
  212. const unsigned char *mac)
  213. {
  214. struct ftgmac100 *ftgmac100 = priv->iobase;
  215. unsigned int maddr = mac[0] << 8 | mac[1];
  216. unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
  217. debug("%s(%x %x)\n", __func__, maddr, laddr);
  218. writel(maddr, &ftgmac100->mac_madr);
  219. writel(laddr, &ftgmac100->mac_ladr);
  220. return 0;
  221. }
  222. /*
  223. * Get MAC address
  224. */
  225. static int ftgmac100_get_mac(struct ftgmac100_data *priv,
  226. unsigned char *mac)
  227. {
  228. struct ftgmac100 *ftgmac100 = priv->iobase;
  229. unsigned int maddr = readl(&ftgmac100->mac_madr);
  230. unsigned int laddr = readl(&ftgmac100->mac_ladr);
  231. debug("%s(%x %x)\n", __func__, maddr, laddr);
  232. mac[0] = (maddr >> 8) & 0xff;
  233. mac[1] = maddr & 0xff;
  234. mac[2] = (laddr >> 24) & 0xff;
  235. mac[3] = (laddr >> 16) & 0xff;
  236. mac[4] = (laddr >> 8) & 0xff;
  237. mac[5] = laddr & 0xff;
  238. return 0;
  239. }
  240. /*
  241. * disable transmitter, receiver
  242. */
  243. static void ftgmac100_stop(struct udevice *dev)
  244. {
  245. struct ftgmac100_data *priv = dev_get_priv(dev);
  246. struct ftgmac100 *ftgmac100 = priv->iobase;
  247. debug("%s()\n", __func__);
  248. writel(0, &ftgmac100->maccr);
  249. phy_shutdown(priv->phydev);
  250. }
  251. static int ftgmac100_start(struct udevice *dev)
  252. {
  253. struct eth_pdata *plat = dev_get_plat(dev);
  254. struct ftgmac100_data *priv = dev_get_priv(dev);
  255. struct ftgmac100 *ftgmac100 = priv->iobase;
  256. struct phy_device *phydev = priv->phydev;
  257. unsigned int maccr;
  258. ulong start, end;
  259. int ret;
  260. int i;
  261. debug("%s()\n", __func__);
  262. ftgmac100_reset(priv);
  263. /* set the ethernet address */
  264. ftgmac100_set_mac(priv, plat->enetaddr);
  265. /* disable all interrupts */
  266. writel(0, &ftgmac100->ier);
  267. /* initialize descriptors */
  268. priv->tx_index = 0;
  269. priv->rx_index = 0;
  270. for (i = 0; i < PKTBUFSTX; i++) {
  271. priv->txdes[i].txdes3 = 0;
  272. priv->txdes[i].txdes0 = 0;
  273. }
  274. priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
  275. start = ((ulong)&priv->txdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
  276. end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
  277. flush_dcache_range(start, end);
  278. for (i = 0; i < PKTBUFSRX; i++) {
  279. priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
  280. priv->rxdes[i].rxdes0 = 0;
  281. }
  282. priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
  283. start = ((ulong)&priv->rxdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
  284. end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
  285. flush_dcache_range(start, end);
  286. /* transmit ring */
  287. writel((u32)priv->txdes, &ftgmac100->txr_badr);
  288. /* receive ring */
  289. writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
  290. /* poll receive descriptor automatically */
  291. writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
  292. /* config receive buffer size register */
  293. writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
  294. /* enable transmitter, receiver */
  295. maccr = FTGMAC100_MACCR_TXMAC_EN |
  296. FTGMAC100_MACCR_RXMAC_EN |
  297. FTGMAC100_MACCR_TXDMA_EN |
  298. FTGMAC100_MACCR_RXDMA_EN |
  299. FTGMAC100_MACCR_CRC_APD |
  300. FTGMAC100_MACCR_FULLDUP |
  301. FTGMAC100_MACCR_RX_RUNT |
  302. FTGMAC100_MACCR_RX_BROADPKT;
  303. writel(maccr, &ftgmac100->maccr);
  304. ret = phy_startup(phydev);
  305. if (ret) {
  306. dev_err(phydev->dev, "Could not start PHY\n");
  307. return ret;
  308. }
  309. ret = ftgmac100_phy_adjust_link(priv);
  310. if (ret) {
  311. dev_err(phydev->dev, "Could not adjust link\n");
  312. return ret;
  313. }
  314. printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name,
  315. phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr);
  316. return 0;
  317. }
  318. static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
  319. {
  320. struct ftgmac100_data *priv = dev_get_priv(dev);
  321. struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
  322. ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
  323. ulong des_end = des_start +
  324. roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
  325. /* Release buffer to DMA and flush descriptor */
  326. curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
  327. flush_dcache_range(des_start, des_end);
  328. /* Move to next descriptor */
  329. priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
  330. return 0;
  331. }
  332. /*
  333. * Get a data block via Ethernet
  334. */
  335. static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
  336. {
  337. struct ftgmac100_data *priv = dev_get_priv(dev);
  338. struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
  339. unsigned short rxlen;
  340. ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
  341. ulong des_end = des_start +
  342. roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
  343. ulong data_start = curr_des->rxdes3;
  344. ulong data_end;
  345. invalidate_dcache_range(des_start, des_end);
  346. if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
  347. return -EAGAIN;
  348. if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
  349. FTGMAC100_RXDES0_CRC_ERR |
  350. FTGMAC100_RXDES0_FTL |
  351. FTGMAC100_RXDES0_RUNT |
  352. FTGMAC100_RXDES0_RX_ODD_NB)) {
  353. return -EAGAIN;
  354. }
  355. rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
  356. debug("%s(): RX buffer %d, %x received\n",
  357. __func__, priv->rx_index, rxlen);
  358. /* Invalidate received data */
  359. data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN);
  360. invalidate_dcache_range(data_start, data_end);
  361. *packetp = (uchar *)data_start;
  362. return rxlen;
  363. }
  364. static u32 ftgmac100_read_txdesc(const void *desc)
  365. {
  366. const struct ftgmac100_txdes *txdes = desc;
  367. ulong des_start = ((ulong)txdes) & ~(ARCH_DMA_MINALIGN - 1);
  368. ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN);
  369. invalidate_dcache_range(des_start, des_end);
  370. return txdes->txdes0;
  371. }
  372. BUILD_WAIT_FOR_BIT(ftgmac100_txdone, u32, ftgmac100_read_txdesc)
  373. /*
  374. * Send a data block via Ethernet
  375. */
  376. static int ftgmac100_send(struct udevice *dev, void *packet, int length)
  377. {
  378. struct ftgmac100_data *priv = dev_get_priv(dev);
  379. struct ftgmac100 *ftgmac100 = priv->iobase;
  380. struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
  381. ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
  382. ulong des_end = des_start +
  383. roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
  384. ulong data_start;
  385. ulong data_end;
  386. int rc;
  387. invalidate_dcache_range(des_start, des_end);
  388. if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
  389. dev_err(dev, "no TX descriptor available\n");
  390. return -EPERM;
  391. }
  392. debug("%s(%x, %x)\n", __func__, (int)packet, length);
  393. length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
  394. curr_des->txdes3 = (unsigned int)packet;
  395. /* Flush data to be sent */
  396. data_start = curr_des->txdes3;
  397. data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
  398. flush_dcache_range(data_start, data_end);
  399. /* Only one segment on TXBUF */
  400. curr_des->txdes0 &= priv->txdes0_edotr_mask;
  401. curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
  402. FTGMAC100_TXDES0_LTS |
  403. FTGMAC100_TXDES0_TXBUF_SIZE(length) |
  404. FTGMAC100_TXDES0_TXDMA_OWN ;
  405. /* Flush modified buffer descriptor */
  406. flush_dcache_range(des_start, des_end);
  407. /* Start transmit */
  408. writel(1, &ftgmac100->txpd);
  409. rc = wait_for_bit_ftgmac100_txdone(curr_des,
  410. FTGMAC100_TXDES0_TXDMA_OWN, false,
  411. FTGMAC100_TX_TIMEOUT_MS, true);
  412. if (rc)
  413. return rc;
  414. debug("%s(): packet sent\n", __func__);
  415. /* Move to next descriptor */
  416. priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
  417. return 0;
  418. }
  419. static int ftgmac100_write_hwaddr(struct udevice *dev)
  420. {
  421. struct eth_pdata *pdata = dev_get_plat(dev);
  422. struct ftgmac100_data *priv = dev_get_priv(dev);
  423. return ftgmac100_set_mac(priv, pdata->enetaddr);
  424. }
  425. static int ftgmac_read_hwaddr(struct udevice *dev)
  426. {
  427. struct eth_pdata *pdata = dev_get_plat(dev);
  428. struct ftgmac100_data *priv = dev_get_priv(dev);
  429. return ftgmac100_get_mac(priv, pdata->enetaddr);
  430. }
  431. static int ftgmac100_of_to_plat(struct udevice *dev)
  432. {
  433. struct eth_pdata *pdata = dev_get_plat(dev);
  434. struct ftgmac100_data *priv = dev_get_priv(dev);
  435. const char *phy_mode;
  436. pdata->iobase = dev_read_addr(dev);
  437. pdata->phy_interface = -1;
  438. phy_mode = dev_read_string(dev, "phy-mode");
  439. if (phy_mode)
  440. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  441. if (pdata->phy_interface == -1) {
  442. dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
  443. return -EINVAL;
  444. }
  445. pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
  446. if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
  447. priv->rxdes0_edorr_mask = BIT(30);
  448. priv->txdes0_edotr_mask = BIT(30);
  449. } else {
  450. priv->rxdes0_edorr_mask = BIT(15);
  451. priv->txdes0_edotr_mask = BIT(15);
  452. }
  453. return clk_get_bulk(dev, &priv->clks);
  454. }
  455. static int ftgmac100_probe(struct udevice *dev)
  456. {
  457. struct eth_pdata *pdata = dev_get_plat(dev);
  458. struct ftgmac100_data *priv = dev_get_priv(dev);
  459. int ret;
  460. priv->iobase = (struct ftgmac100 *)pdata->iobase;
  461. priv->phy_mode = pdata->phy_interface;
  462. priv->max_speed = pdata->max_speed;
  463. priv->phy_addr = 0;
  464. #ifdef CONFIG_PHY_ADDR
  465. priv->phy_addr = CONFIG_PHY_ADDR;
  466. #endif
  467. ret = clk_enable_bulk(&priv->clks);
  468. if (ret)
  469. goto out;
  470. ret = ftgmac100_mdio_init(dev);
  471. if (ret) {
  472. dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
  473. goto out;
  474. }
  475. ret = ftgmac100_phy_init(dev);
  476. if (ret) {
  477. dev_err(dev, "Failed to initialize PHY: %d\n", ret);
  478. goto out;
  479. }
  480. ftgmac_read_hwaddr(dev);
  481. out:
  482. if (ret)
  483. clk_release_bulk(&priv->clks);
  484. return ret;
  485. }
  486. static int ftgmac100_remove(struct udevice *dev)
  487. {
  488. struct ftgmac100_data *priv = dev_get_priv(dev);
  489. free(priv->phydev);
  490. mdio_unregister(priv->bus);
  491. mdio_free(priv->bus);
  492. clk_release_bulk(&priv->clks);
  493. return 0;
  494. }
  495. static const struct eth_ops ftgmac100_ops = {
  496. .start = ftgmac100_start,
  497. .send = ftgmac100_send,
  498. .recv = ftgmac100_recv,
  499. .stop = ftgmac100_stop,
  500. .free_pkt = ftgmac100_free_pkt,
  501. .write_hwaddr = ftgmac100_write_hwaddr,
  502. };
  503. static const struct udevice_id ftgmac100_ids[] = {
  504. { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
  505. { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
  506. { }
  507. };
  508. U_BOOT_DRIVER(ftgmac100) = {
  509. .name = "ftgmac100",
  510. .id = UCLASS_ETH,
  511. .of_match = ftgmac100_ids,
  512. .of_to_plat = ftgmac100_of_to_plat,
  513. .probe = ftgmac100_probe,
  514. .remove = ftgmac100_remove,
  515. .ops = &ftgmac100_ops,
  516. .priv_auto = sizeof(struct ftgmac100_data),
  517. .plat_auto = sizeof(struct eth_pdata),
  518. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  519. };