fsl_mcdmafec.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2004
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. *
  6. * (C) Copyright 2007 Freescale Semiconductor, Inc.
  7. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  8. *
  9. * Conversion to DM
  10. * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
  11. */
  12. #include <common.h>
  13. #include <env.h>
  14. #include <hang.h>
  15. #include <malloc.h>
  16. #include <command.h>
  17. #include <config.h>
  18. #include <net.h>
  19. #include <miiphy.h>
  20. #include <asm/global_data.h>
  21. #include <linux/delay.h>
  22. #include <linux/mii.h>
  23. #include <asm/immap.h>
  24. #include <asm/fsl_mcdmafec.h>
  25. #include "MCD_dma.h"
  26. #undef ET_DEBUG
  27. #undef MII_DEBUG
  28. /* Ethernet Transmit and Receive Buffers */
  29. #define DBUF_LENGTH 1520
  30. #define PKT_MAXBUF_SIZE 1518
  31. #define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
  32. /* RxBD bits definitions */
  33. #define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
  34. BD_ENET_RX_OV | BD_ENET_RX_TR)
  35. DECLARE_GLOBAL_DATA_PTR;
  36. static void init_eth_info(struct fec_info_dma *info)
  37. {
  38. /* setup Receive and Transmit buffer descriptor */
  39. #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
  40. static u32 tmp;
  41. if (info->index == 0)
  42. tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
  43. else
  44. info->rxbd = (cbd_t *)DBUF_LENGTH;
  45. info->rxbd = (cbd_t *)((u32)info->rxbd + tmp);
  46. tmp = (u32)info->rxbd;
  47. info->txbd =
  48. (cbd_t *)((u32)info->txbd + tmp +
  49. (PKTBUFSRX * sizeof(cbd_t)));
  50. tmp = (u32)info->txbd;
  51. info->txbuf =
  52. (char *)((u32)info->txbuf + tmp +
  53. (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
  54. tmp = (u32)info->txbuf;
  55. #else
  56. info->rxbd =
  57. (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
  58. (PKTBUFSRX * sizeof(cbd_t)));
  59. info->txbd =
  60. (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
  61. (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
  62. info->txbuf =
  63. (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
  64. #endif
  65. #ifdef ET_DEBUG
  66. printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd);
  67. #endif
  68. info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
  69. }
  70. static void fec_halt(struct udevice *dev)
  71. {
  72. struct fec_info_dma *info = dev_get_priv(dev);
  73. volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
  74. int counter = 0xffff;
  75. /* issue graceful stop command to the FEC transmitter if necessary */
  76. fecp->tcr |= FEC_TCR_GTS;
  77. /* wait for graceful stop to register */
  78. while ((counter--) && (!(fecp->eir & FEC_EIR_GRA)))
  79. ;
  80. /* Disable DMA tasks */
  81. MCD_killDma(info->tx_task);
  82. MCD_killDma(info->rx_task);
  83. /* Disable the Ethernet Controller */
  84. fecp->ecr &= ~FEC_ECR_ETHER_EN;
  85. /* Clear FIFO status registers */
  86. fecp->rfsr &= FIFO_ERRSTAT;
  87. fecp->tfsr &= FIFO_ERRSTAT;
  88. fecp->frst = 0x01000000;
  89. /* Issue a reset command to the FEC chip */
  90. fecp->ecr |= FEC_ECR_RESET;
  91. /* wait at least 20 clock cycles */
  92. mdelay(10);
  93. #ifdef ET_DEBUG
  94. printf("Ethernet task stopped\n");
  95. #endif
  96. }
  97. #ifdef ET_DEBUG
  98. static void dbg_fec_regs(struct eth_device *dev)
  99. {
  100. struct fec_info_dma *info = dev->priv;
  101. volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
  102. printf("=====\n");
  103. printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
  104. printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
  105. printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
  106. printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
  107. printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
  108. printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
  109. printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
  110. printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
  111. printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
  112. printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
  113. printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
  114. printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
  115. printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
  116. printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
  117. printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
  118. printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
  119. printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
  120. printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
  121. printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
  122. printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
  123. printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
  124. printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
  125. printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
  126. printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
  127. printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
  128. printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
  129. printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
  130. printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
  131. printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
  132. printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
  133. printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
  134. printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
  135. printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
  136. printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
  137. printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
  138. }
  139. #endif
  140. static void set_fec_duplex_speed(volatile fecdma_t *fecp, int dup_spd)
  141. {
  142. struct bd_info *bd = gd->bd;
  143. if ((dup_spd >> 16) == FULL) {
  144. /* Set maximum frame length */
  145. fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
  146. FEC_RCR_PROM | 0x100;
  147. fecp->tcr = FEC_TCR_FDEN;
  148. } else {
  149. /* Half duplex mode */
  150. fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
  151. FEC_RCR_MII_MODE | FEC_RCR_DRT;
  152. fecp->tcr &= ~FEC_TCR_FDEN;
  153. }
  154. if ((dup_spd & 0xFFFF) == _100BASET) {
  155. #ifdef MII_DEBUG
  156. printf("100Mbps\n");
  157. #endif
  158. bd->bi_ethspeed = 100;
  159. } else {
  160. #ifdef MII_DEBUG
  161. printf("10Mbps\n");
  162. #endif
  163. bd->bi_ethspeed = 10;
  164. }
  165. }
  166. static void fec_set_hwaddr(volatile fecdma_t *fecp, u8 *mac)
  167. {
  168. u8 curr_byte; /* byte for which to compute the CRC */
  169. int byte; /* loop - counter */
  170. int bit; /* loop - counter */
  171. u32 crc = 0xffffffff; /* initial value */
  172. for (byte = 0; byte < 6; byte++) {
  173. curr_byte = mac[byte];
  174. for (bit = 0; bit < 8; bit++) {
  175. if ((curr_byte & 0x01) ^ (crc & 0x01)) {
  176. crc >>= 1;
  177. crc = crc ^ 0xedb88320;
  178. } else {
  179. crc >>= 1;
  180. }
  181. curr_byte >>= 1;
  182. }
  183. }
  184. crc = crc >> 26;
  185. /* Set individual hash table register */
  186. if (crc >= 32) {
  187. fecp->ialr = (1 << (crc - 32));
  188. fecp->iaur = 0;
  189. } else {
  190. fecp->ialr = 0;
  191. fecp->iaur = (1 << crc);
  192. }
  193. /* Set physical address */
  194. fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
  195. fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
  196. /* Clear multicast address hash table */
  197. fecp->gaur = 0;
  198. fecp->galr = 0;
  199. }
  200. static int fec_init(struct udevice *dev)
  201. {
  202. struct fec_info_dma *info = dev_get_priv(dev);
  203. volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
  204. int rval, i;
  205. uchar enetaddr[6];
  206. #ifdef ET_DEBUG
  207. printf("fec_init: iobase 0x%08x ...\n", info->iobase);
  208. #endif
  209. fecpin_setclear(info, 1);
  210. fec_halt(dev);
  211. #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
  212. defined (CONFIG_SYS_DISCOVER_PHY)
  213. mii_init();
  214. set_fec_duplex_speed(fecp, info->dup_spd);
  215. #else
  216. #ifndef CONFIG_SYS_DISCOVER_PHY
  217. set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED);
  218. #endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
  219. #endif /* CONFIG_CMD_MII || CONFIG_MII */
  220. /* We use strictly polling mode only */
  221. fecp->eimr = 0;
  222. /* Clear any pending interrupt */
  223. fecp->eir = 0xffffffff;
  224. /* Set station address */
  225. if (info->index == 0)
  226. rval = eth_env_get_enetaddr("ethaddr", enetaddr);
  227. else
  228. rval = eth_env_get_enetaddr("eth1addr", enetaddr);
  229. if (!rval) {
  230. puts("Please set a valid MAC address\n");
  231. return -EINVAL;
  232. }
  233. fec_set_hwaddr(fecp, enetaddr);
  234. /* Set Opcode/Pause Duration Register */
  235. fecp->opd = 0x00010020;
  236. /* Setup Buffers and Buffer Descriptors */
  237. info->rx_idx = 0;
  238. info->tx_idx = 0;
  239. /* Setup Receiver Buffer Descriptors (13.14.24.18)
  240. * Settings: Empty, Wrap */
  241. for (i = 0; i < PKTBUFSRX; i++) {
  242. info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
  243. info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
  244. info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
  245. }
  246. info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
  247. /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
  248. * Settings: Last, Tx CRC */
  249. for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
  250. info->txbd[i].cbd_sc = 0;
  251. info->txbd[i].cbd_datlen = 0;
  252. info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
  253. }
  254. info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
  255. info->used_tbd_idx = 0;
  256. info->clean_tbd_num = CONFIG_SYS_TX_ETH_BUFFER;
  257. /* Set Rx FIFO alarm and granularity value */
  258. fecp->rfcr = 0x0c000000;
  259. fecp->rfar = 0x0000030c;
  260. /* Set Tx FIFO granularity value */
  261. fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
  262. fecp->tfar = 0x00000080;
  263. fecp->tfwr = 0x2;
  264. fecp->ctcwr = 0x03000000;
  265. /* Enable DMA receive task */
  266. MCD_startDma(info->rx_task,
  267. (s8 *)info->rxbd,
  268. 0,
  269. (s8 *)&fecp->rfdr,
  270. 4,
  271. 0,
  272. 4,
  273. info->rx_init,
  274. info->rx_pri,
  275. (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),
  276. (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
  277. );
  278. /* Enable DMA tx task with no ready buffer descriptors */
  279. MCD_startDma(info->tx_task,
  280. (s8 *)info->txbd,
  281. 0,
  282. (s8 *)&fecp->tfdr,
  283. 4,
  284. 0,
  285. 4,
  286. info->tx_init,
  287. info->tx_pri,
  288. (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),
  289. (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
  290. );
  291. /* Now enable the transmit and receive processing */
  292. fecp->ecr |= FEC_ECR_ETHER_EN;
  293. return 0;
  294. }
  295. static int mcdmafec_init(struct udevice *dev)
  296. {
  297. return fec_init(dev);
  298. }
  299. static int mcdmafec_send(struct udevice *dev, void *packet, int length)
  300. {
  301. struct fec_info_dma *info = dev_get_priv(dev);
  302. cbd_t *p_tbd, *p_used_tbd;
  303. u16 phy_status;
  304. miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
  305. /* process all the consumed TBDs */
  306. while (info->clean_tbd_num < CONFIG_SYS_TX_ETH_BUFFER) {
  307. p_used_tbd = &info->txbd[info->used_tbd_idx];
  308. if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) {
  309. #ifdef ET_DEBUG
  310. printf("Cannot clean TBD %d, in use\n",
  311. info->clean_tbd_num);
  312. #endif
  313. return 0;
  314. }
  315. /* clean this buffer descriptor */
  316. if (info->used_tbd_idx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
  317. p_used_tbd->cbd_sc = BD_ENET_TX_WRAP;
  318. else
  319. p_used_tbd->cbd_sc = 0;
  320. /* update some indeces for a correct handling of TBD ring */
  321. info->clean_tbd_num++;
  322. info->used_tbd_idx = (info->used_tbd_idx + 1)
  323. % CONFIG_SYS_TX_ETH_BUFFER;
  324. }
  325. /* Check for valid length of data. */
  326. if (length > 1500 || length <= 0)
  327. return -1;
  328. /* Check the number of vacant TxBDs. */
  329. if (info->clean_tbd_num < 1) {
  330. printf("No available TxBDs ...\n");
  331. return -1;
  332. }
  333. /* Get the first TxBD to send the mac header */
  334. p_tbd = &info->txbd[info->tx_idx];
  335. p_tbd->cbd_datlen = length;
  336. p_tbd->cbd_bufaddr = (u32)packet;
  337. p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
  338. info->tx_idx = (info->tx_idx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
  339. /* Enable DMA transmit task */
  340. MCD_continDma(info->tx_task);
  341. info->clean_tbd_num -= 1;
  342. /* wait until frame is sent . */
  343. while (p_tbd->cbd_sc & BD_ENET_TX_READY)
  344. udelay(10);
  345. return (int)(info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS);
  346. }
  347. static int mcdmafec_recv(struct udevice *dev, int flags, uchar **packetp)
  348. {
  349. struct fec_info_dma *info = dev_get_priv(dev);
  350. volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
  351. cbd_t *prbd = &info->rxbd[info->rx_idx];
  352. u32 ievent;
  353. int frame_length, len = 0;
  354. /* Check if any critical events have happened */
  355. ievent = fecp->eir;
  356. if (ievent != 0) {
  357. fecp->eir = ievent;
  358. if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
  359. printf("fec_recv: error\n");
  360. fec_halt(dev);
  361. fec_init(dev);
  362. return 0;
  363. }
  364. if (ievent & FEC_EIR_HBERR) {
  365. /* Heartbeat error */
  366. fecp->tcr |= FEC_TCR_GTS;
  367. }
  368. if (ievent & FEC_EIR_GRA) {
  369. /* Graceful stop complete */
  370. if (fecp->tcr & FEC_TCR_GTS) {
  371. printf("fec_recv: tcr_gts\n");
  372. fec_halt(dev);
  373. fecp->tcr &= ~FEC_TCR_GTS;
  374. fec_init(dev);
  375. }
  376. }
  377. }
  378. if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
  379. if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
  380. !(prbd->cbd_sc & BD_ENET_RX_ERR) &&
  381. ((prbd->cbd_datlen - 4) > 14)) {
  382. /* Get buffer address and size */
  383. frame_length = prbd->cbd_datlen - 4;
  384. /* Fill the buffer and pass it to upper layers */
  385. net_process_received_packet((uchar *)prbd->cbd_bufaddr,
  386. frame_length);
  387. len = frame_length;
  388. }
  389. /* Reset buffer descriptor as empty */
  390. if (info->rx_idx == (PKTBUFSRX - 1))
  391. prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
  392. else
  393. prbd->cbd_sc = BD_ENET_RX_EMPTY;
  394. prbd->cbd_datlen = PKTSIZE_ALIGN;
  395. /* Now, we have an empty RxBD, restart the DMA receive task */
  396. MCD_continDma(info->rx_task);
  397. /* Increment BD count */
  398. info->rx_idx = (info->rx_idx + 1) % PKTBUFSRX;
  399. }
  400. return len;
  401. }
  402. static void mcdmafec_halt(struct udevice *dev)
  403. {
  404. fec_halt(dev);
  405. }
  406. static const struct eth_ops mcdmafec_ops = {
  407. .start = mcdmafec_init,
  408. .send = mcdmafec_send,
  409. .recv = mcdmafec_recv,
  410. .stop = mcdmafec_halt,
  411. };
  412. /*
  413. * Boot sequence, called just after mcffec_of_to_plat,
  414. * as DM way, it replaces old mcffec_initialize.
  415. */
  416. static int mcdmafec_probe(struct udevice *dev)
  417. {
  418. struct fec_info_dma *info = dev_get_priv(dev);
  419. struct eth_pdata *pdata = dev_get_plat(dev);
  420. int node = dev_of_offset(dev);
  421. int retval;
  422. const u32 *val;
  423. info->index = dev_seq(dev);
  424. info->iobase = pdata->iobase;
  425. info->miibase = pdata->iobase;
  426. info->phy_addr = -1;
  427. val = fdt_getprop(gd->fdt_blob, node, "rx-task", NULL);
  428. if (val)
  429. info->rx_task = fdt32_to_cpu(*val);
  430. val = fdt_getprop(gd->fdt_blob, node, "tx-task", NULL);
  431. if (val)
  432. info->tx_task = fdt32_to_cpu(*val);
  433. val = fdt_getprop(gd->fdt_blob, node, "rx-prioprity", NULL);
  434. if (val)
  435. info->rx_pri = fdt32_to_cpu(*val);
  436. val = fdt_getprop(gd->fdt_blob, node, "tx-prioprity", NULL);
  437. if (val)
  438. info->tx_pri = fdt32_to_cpu(*val);
  439. val = fdt_getprop(gd->fdt_blob, node, "rx-init", NULL);
  440. if (val)
  441. info->rx_init = fdt32_to_cpu(*val);
  442. val = fdt_getprop(gd->fdt_blob, node, "tx-init", NULL);
  443. if (val)
  444. info->tx_init = fdt32_to_cpu(*val);
  445. #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
  446. u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
  447. #endif
  448. init_eth_info(info);
  449. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  450. info->bus = mdio_alloc();
  451. if (!info->bus)
  452. return -ENOMEM;
  453. strncpy(info->bus->name, dev->name, MDIO_NAME_LEN);
  454. info->bus->read = mcffec_miiphy_read;
  455. info->bus->write = mcffec_miiphy_write;
  456. retval = mdio_register(info->bus);
  457. if (retval < 0)
  458. return retval;
  459. #endif
  460. return 0;
  461. }
  462. static int mcdmafec_remove(struct udevice *dev)
  463. {
  464. struct fec_info_dma *priv = dev_get_priv(dev);
  465. mdio_unregister(priv->bus);
  466. mdio_free(priv->bus);
  467. return 0;
  468. }
  469. /*
  470. * Boot sequence, called 1st
  471. */
  472. static int mcdmafec_of_to_plat(struct udevice *dev)
  473. {
  474. struct eth_pdata *pdata = dev_get_plat(dev);
  475. const u32 *val;
  476. pdata->iobase = dev_read_addr(dev);
  477. /* Default to 10Mbit/s */
  478. pdata->max_speed = 10;
  479. val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
  480. if (val)
  481. pdata->max_speed = fdt32_to_cpu(*val);
  482. return 0;
  483. }
  484. static const struct udevice_id mcdmafec_ids[] = {
  485. { .compatible = "fsl,mcf-dma-fec" },
  486. { }
  487. };
  488. U_BOOT_DRIVER(mcffec) = {
  489. .name = "mcdmafec",
  490. .id = UCLASS_ETH,
  491. .of_match = mcdmafec_ids,
  492. .of_to_plat = mcdmafec_of_to_plat,
  493. .probe = mcdmafec_probe,
  494. .remove = mcdmafec_remove,
  495. .ops = &mcdmafec_ops,
  496. .priv_auto = sizeof(struct fec_info_dma),
  497. .plat_auto = sizeof(struct eth_pdata),
  498. };