fsl_enetc.h 6.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * ENETC ethernet controller driver
  4. * Copyright 2017-2021 NXP
  5. */
  6. #ifndef _ENETC_H
  7. #define _ENETC_H
  8. #include <linux/bitops.h>
  9. #define enetc_dbg(dev, fmt, args...) debug("%s:" fmt, dev->name, ##args)
  10. /* PCI function IDs */
  11. #define PCI_DEVICE_ID_ENETC_ETH 0xE100
  12. #define PCI_DEVICE_ID_ENETC_MDIO 0xEE01
  13. /* ENETC Ethernet controller registers */
  14. /* Station interface register offsets */
  15. #define ENETC_SIMR 0x000
  16. #define ENETC_SIMR_EN BIT(31)
  17. #define ENETC_SICAR0 0x040
  18. /* write cache cfg: snoop, no allocate, data & BD coherent */
  19. #define ENETC_SICAR_WR_CFG 0x6767
  20. /* read cache cfg: coherent copy, look up, don't alloc in cache */
  21. #define ENETC_SICAR_RD_CFG 0x27270000
  22. #define ENETC_SIROCT 0x300
  23. #define ENETC_SIRFRM 0x308
  24. #define ENETC_SITOCT 0x320
  25. #define ENETC_SITFRM 0x328
  26. /* Rx/Tx Buffer Descriptor Ring registers */
  27. enum enetc_bdr_type {TX, RX};
  28. #define ENETC_BDR(type, n, off) (0x8000 + (type) * 0x100 + (n) * 0x200 + (off))
  29. #define ENETC_BDR_IDX_MASK 0xffff
  30. /* Rx BDR reg offsets */
  31. #define ENETC_RBMR 0x00
  32. #define ENETC_RBMR_EN BIT(31)
  33. #define ENETC_RBBSR 0x08
  34. /* initial consumer index for Rx BDR */
  35. #define ENETC_RBCIR 0x0c
  36. #define ENETC_RBBAR0 0x10
  37. #define ENETC_RBBAR1 0x14
  38. #define ENETC_RBPIR 0x18
  39. #define ENETC_RBLENR 0x20
  40. /* Tx BDR reg offsets */
  41. #define ENETC_TBMR 0x00
  42. #define ENETC_TBMR_EN BIT(31)
  43. #define ENETC_TBBAR0 0x10
  44. #define ENETC_TBBAR1 0x14
  45. #define ENETC_TBPIR 0x18
  46. #define ENETC_TBCIR 0x1c
  47. #define ENETC_TBLENR 0x20
  48. /* Port registers offset */
  49. #define ENETC_PORT_REGS_OFF 0x10000
  50. /* Port registers */
  51. #define ENETC_PMR 0x0000
  52. #define ENETC_PMR_SI0_EN BIT(16)
  53. #define ENETC_PSIPMMR 0x0018
  54. #define ENETC_PSIPMAR0 0x0100
  55. #define ENETC_PSIPMAR1 0x0104
  56. #define ENETC_PCAPR0 0x0900
  57. #define ENETC_PCAPRO_MDIO BIT(11)
  58. #define ENETC_PSICFGR(n) (0x0940 + (n) * 0x10)
  59. #define ENETC_PSICFGR_SET_TXBDR(val) ((val) & 0xff)
  60. #define ENETC_PSICFGR_SET_RXBDR(val) (((val) & 0xff) << 16)
  61. /* MAC configuration */
  62. #define ENETC_PM_CC 0x8008
  63. #define ENETC_PM_CC_DEFAULT 0x0810
  64. #define ENETC_PM_CC_RX_TX_EN 0x8813
  65. #define ENETC_PM_MAXFRM 0x8014
  66. #define ENETC_RX_MAXFRM_SIZE PKTSIZE_ALIGN
  67. #define ENETC_PM_IMDIO_BASE 0x8030
  68. #define ENETC_PM_IF_MODE 0x8300
  69. #define ENETC_PM_IF_MODE_RG BIT(2)
  70. #define ENETC_PM_IF_MODE_AN_ENA BIT(15)
  71. #define ENETC_PM_IFM_SSP_MASK GENMASK(14, 13)
  72. #define ENETC_PM_IFM_SSP_1000 (2 << 13)
  73. #define ENETC_PM_IFM_SSP_100 (0 << 13)
  74. #define ENETC_PM_IFM_SSP_10 (1 << 13)
  75. #define ENETC_PM_IFM_FULL_DPX BIT(12)
  76. #define ENETC_PM_IF_IFMODE_MASK GENMASK(1, 0)
  77. /* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */
  78. #define ENETC_BD_CNT CONFIG_SYS_RX_ETH_BUFFER
  79. #define ENETC_BD_ALIGN 128
  80. /* single pair of Rx/Tx rings */
  81. #define ENETC_RX_BDR_CNT 1
  82. #define ENETC_TX_BDR_CNT 1
  83. #define ENETC_RX_BDR_ID 0
  84. #define ENETC_TX_BDR_ID 0
  85. /* Tx buffer descriptor */
  86. struct enetc_tx_bd {
  87. __le64 addr;
  88. __le16 buf_len;
  89. __le16 frm_len;
  90. __le16 err_csum;
  91. __le16 flags;
  92. };
  93. #define ENETC_TXBD_FLAGS_F BIT(15)
  94. #define ENETC_POLL_TRIES 32000
  95. /* Rx buffer descriptor */
  96. union enetc_rx_bd {
  97. /* SW provided BD format */
  98. struct {
  99. __le64 addr;
  100. u8 reserved[8];
  101. } w;
  102. /* ENETC returned BD format */
  103. struct {
  104. __le16 inet_csum;
  105. __le16 parse_summary;
  106. __le32 rss_hash;
  107. __le16 buf_len;
  108. __le16 vlan_opt;
  109. union {
  110. struct {
  111. __le16 flags;
  112. __le16 error;
  113. };
  114. __le32 lstatus;
  115. };
  116. } r;
  117. };
  118. #define ENETC_RXBD_STATUS_R(status) (((status) >> 30) & 0x1)
  119. #define ENETC_RXBD_STATUS_F(status) (((status) >> 31) & 0x1)
  120. #define ENETC_RXBD_STATUS_ERRORS(status) (((status) >> 16) & 0xff)
  121. #define ENETC_RXBD_STATUS(flags) ((flags) << 16)
  122. /* Tx/Rx ring info */
  123. struct bd_ring {
  124. void *cons_idx;
  125. void *prod_idx;
  126. /* next BD index to use */
  127. int next_prod_idx;
  128. int next_cons_idx;
  129. int bd_count;
  130. };
  131. /* ENETC private structure */
  132. struct enetc_priv {
  133. struct enetc_tx_bd *enetc_txbd;
  134. union enetc_rx_bd *enetc_rxbd;
  135. void *regs_base; /* base ENETC registers */
  136. void *port_regs; /* base ENETC port registers */
  137. /* Rx/Tx buffer descriptor rings info */
  138. struct bd_ring tx_bdr;
  139. struct bd_ring rx_bdr;
  140. int if_type;
  141. struct mii_dev imdio;
  142. struct phy_device *phy;
  143. };
  144. /* register accessors */
  145. #define enetc_read_reg(x) readl((x))
  146. #define enetc_write_reg(x, val) writel((val), (x))
  147. #define enetc_read(priv, off) enetc_read_reg((priv)->regs_base + (off))
  148. #define enetc_write(priv, off, v) \
  149. enetc_write_reg((priv)->regs_base + (off), v)
  150. /* port register accessors */
  151. #define enetc_port_regs(priv, off) ((priv)->port_regs + (off))
  152. #define enetc_read_port(priv, off) \
  153. enetc_read_reg(enetc_port_regs((priv), (off)))
  154. #define enetc_write_port(priv, off, v) \
  155. enetc_write_reg(enetc_port_regs((priv), (off)), v)
  156. /* BDR register accessors, see ENETC_BDR() */
  157. #define enetc_bdr_read(priv, t, n, off) \
  158. enetc_read(priv, ENETC_BDR(t, n, off))
  159. #define enetc_bdr_write(priv, t, n, off, val) \
  160. enetc_write(priv, ENETC_BDR(t, n, off), val)
  161. /* PCS / internal SoC PHY ID, it defaults to 0 on all interfaces */
  162. #define ENETC_PCS_PHY_ADDR 0
  163. /* PCS registers */
  164. #define ENETC_PCS_CR 0x00
  165. #define ENETC_PCS_CR_RESET_AN 0x1200
  166. #define ENETC_PCS_CR_DEF_VAL 0x0140
  167. #define ENETC_PCS_CR_RST BIT(15)
  168. #define ENETC_PCS_DEV_ABILITY 0x04
  169. #define ENETC_PCS_DEV_ABILITY_SGMII 0x4001
  170. #define ENETC_PCS_DEV_ABILITY_SXGMII 0x5001
  171. #define ENETC_PCS_LINK_TIMER1 0x12
  172. #define ENETC_PCS_LINK_TIMER1_VAL 0x06a0
  173. #define ENETC_PCS_LINK_TIMER2 0x13
  174. #define ENETC_PCS_LINK_TIMER2_VAL 0x0003
  175. #define ENETC_PCS_IF_MODE 0x14
  176. #define ENETC_PCS_IF_MODE_SGMII BIT(0)
  177. #define ENETC_PCS_IF_MODE_SGMII_AN BIT(1)
  178. #define ENETC_PCS_IF_MODE_SPEED_1G BIT(3)
  179. /* PCS replicator block for USXGMII */
  180. #define ENETC_PCS_DEVAD_REPL 0x1f
  181. #define ENETC_PCS_REPL_LINK_TIMER_1 0x12
  182. #define ENETC_PCS_REPL_LINK_TIMER_1_DEF 0x0003
  183. #define ENETC_PCS_REPL_LINK_TIMER_2 0x13
  184. #define ENETC_PCS_REPL_LINK_TIMER_2_DEF 0x06a0
  185. /* ENETC external MDIO registers */
  186. #define ENETC_MDIO_BASE 0x1c00
  187. #define ENETC_MDIO_CFG 0x00
  188. #define ENETC_EMDIO_CFG_C22 0x00809508
  189. #define ENETC_EMDIO_CFG_C45 0x00809548
  190. #define ENETC_EMDIO_CFG_RD_ER BIT(1)
  191. #define ENETC_EMDIO_CFG_BSY BIT(0)
  192. #define ENETC_MDIO_CTL 0x04
  193. #define ENETC_MDIO_CTL_READ BIT(15)
  194. #define ENETC_MDIO_DATA 0x08
  195. #define ENETC_MDIO_STAT 0x0c
  196. #define ENETC_MDIO_READ_ERR 0xffff
  197. struct enetc_mdio_priv {
  198. void *regs_base;
  199. };
  200. /*
  201. * these functions are implemented by ENETC_MDIO and are re-used by ENETC driver
  202. * to drive serdes / internal SoC PHYs
  203. */
  204. int enetc_mdio_read_priv(struct enetc_mdio_priv *priv, int addr, int devad,
  205. int reg);
  206. int enetc_mdio_write_priv(struct enetc_mdio_priv *priv, int addr, int devad,
  207. int reg, u16 val);
  208. /* sets up primary MAC addresses in DT/IERB */
  209. void fdt_fixup_enetc_mac(void *blob);
  210. #endif /* _ENETC_H */