fsl_enetc.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ENETC ethernet controller driver
  4. * Copyright 2017-2021 NXP
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <fdt_support.h>
  10. #include <malloc.h>
  11. #include <memalign.h>
  12. #include <net.h>
  13. #include <asm/cache.h>
  14. #include <asm/io.h>
  15. #include <pci.h>
  16. #include <miiphy.h>
  17. #include <linux/bug.h>
  18. #include <linux/delay.h>
  19. #include "fsl_enetc.h"
  20. #define ENETC_DRIVER_NAME "enetc_eth"
  21. /*
  22. * sets the MAC address in IERB registers, this setting is persistent and
  23. * carried over to Linux.
  24. */
  25. static void enetc_set_ierb_primary_mac(struct udevice *dev, int devfn,
  26. const u8 *enetaddr)
  27. {
  28. #ifdef CONFIG_ARCH_LS1028A
  29. /*
  30. * LS1028A is the only part with IERB at this time and there are plans to change
  31. * its structure, keep this LS1028A specific for now
  32. */
  33. #define IERB_BASE 0x1f0800000ULL
  34. #define IERB_PFMAC(pf, vf, n) (IERB_BASE + 0x8000 + (pf) * 0x100 + (vf) * 8 \
  35. + (n) * 4)
  36. static int ierb_fn_to_pf[] = {0, 1, 2, -1, -1, -1, 3};
  37. u16 lower = *(const u16 *)(enetaddr + 4);
  38. u32 upper = *(const u32 *)enetaddr;
  39. if (ierb_fn_to_pf[devfn] < 0)
  40. return;
  41. out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 0), upper);
  42. out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 1), (u32)lower);
  43. #endif
  44. }
  45. /* sets up primary MAC addresses in DT/IERB */
  46. void fdt_fixup_enetc_mac(void *blob)
  47. {
  48. struct pci_child_plat *ppdata;
  49. struct eth_pdata *pdata;
  50. struct udevice *dev;
  51. struct uclass *uc;
  52. char path[256];
  53. int offset;
  54. int devfn;
  55. uclass_get(UCLASS_ETH, &uc);
  56. uclass_foreach_dev(dev, uc) {
  57. if (!dev->driver || !dev->driver->name ||
  58. strcmp(dev->driver->name, ENETC_DRIVER_NAME))
  59. continue;
  60. pdata = dev_get_plat(dev);
  61. ppdata = dev_get_parent_plat(dev);
  62. devfn = PCI_FUNC(ppdata->devfn);
  63. enetc_set_ierb_primary_mac(dev, devfn, pdata->enetaddr);
  64. snprintf(path, 256, "/soc/pcie@1f0000000/ethernet@%x,%x",
  65. PCI_DEV(ppdata->devfn), PCI_FUNC(ppdata->devfn));
  66. offset = fdt_path_offset(blob, path);
  67. if (offset < 0)
  68. continue;
  69. fdt_setprop(blob, offset, "mac-address", pdata->enetaddr, 6);
  70. }
  71. }
  72. /*
  73. * Bind the device:
  74. * - set a more explicit name on the interface
  75. */
  76. static int enetc_bind(struct udevice *dev)
  77. {
  78. char name[16];
  79. static int eth_num_devices;
  80. /*
  81. * prefer using PCI function numbers to number interfaces, but these
  82. * are only available if dts nodes are present. For PCI they are
  83. * optional, handle that case too. Just in case some nodes are present
  84. * and some are not, use different naming scheme - enetc-N based on
  85. * PCI function # and enetc#N based on interface count
  86. */
  87. if (ofnode_valid(dev_ofnode(dev)))
  88. sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev)));
  89. else
  90. sprintf(name, "enetc#%u", eth_num_devices++);
  91. device_set_name(dev, name);
  92. return 0;
  93. }
  94. /* MDIO wrappers, we're using these to drive internal MDIO to get to serdes */
  95. static int enetc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  96. {
  97. struct enetc_mdio_priv priv;
  98. priv.regs_base = bus->priv;
  99. return enetc_mdio_read_priv(&priv, addr, devad, reg);
  100. }
  101. static int enetc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  102. u16 val)
  103. {
  104. struct enetc_mdio_priv priv;
  105. priv.regs_base = bus->priv;
  106. return enetc_mdio_write_priv(&priv, addr, devad, reg, val);
  107. }
  108. /* only interfaces that can pin out through serdes have internal MDIO */
  109. static bool enetc_has_imdio(struct udevice *dev)
  110. {
  111. struct enetc_priv *priv = dev_get_priv(dev);
  112. return !!(priv->imdio.priv);
  113. }
  114. /* set up serdes for SGMII */
  115. static int enetc_init_sgmii(struct udevice *dev)
  116. {
  117. struct enetc_priv *priv = dev_get_priv(dev);
  118. bool is2500 = false;
  119. u16 reg;
  120. if (!enetc_has_imdio(dev))
  121. return 0;
  122. if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500)
  123. is2500 = true;
  124. /*
  125. * Set to SGMII mode, for 1Gbps enable AN, for 2.5Gbps set fixed speed.
  126. * Although fixed speed is 1Gbps, we could be running at 2.5Gbps based
  127. * on PLL configuration. Setting 1G for 2.5G here is counter intuitive
  128. * but intentional.
  129. */
  130. reg = ENETC_PCS_IF_MODE_SGMII;
  131. reg |= is2500 ? ENETC_PCS_IF_MODE_SPEED_1G : ENETC_PCS_IF_MODE_SGMII_AN;
  132. enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
  133. ENETC_PCS_IF_MODE, reg);
  134. /* Dev ability - SGMII */
  135. enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
  136. ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SGMII);
  137. /* Adjust link timer for SGMII */
  138. enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
  139. ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL);
  140. enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
  141. ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL);
  142. reg = ENETC_PCS_CR_DEF_VAL;
  143. reg |= is2500 ? ENETC_PCS_CR_RST : ENETC_PCS_CR_RESET_AN;
  144. /* restart PCS AN */
  145. enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
  146. ENETC_PCS_CR, reg);
  147. return 0;
  148. }
  149. /* set up MAC for RGMII */
  150. static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev)
  151. {
  152. struct enetc_priv *priv = dev_get_priv(dev);
  153. u32 old_val, val;
  154. old_val = val = enetc_read_port(priv, ENETC_PM_IF_MODE);
  155. /* disable unreliable RGMII in-band signaling and force the MAC into
  156. * the speed negotiated by the PHY.
  157. */
  158. val &= ~ENETC_PM_IF_MODE_AN_ENA;
  159. if (phydev->speed == SPEED_1000) {
  160. val &= ~ENETC_PM_IFM_SSP_MASK;
  161. val |= ENETC_PM_IFM_SSP_1000;
  162. } else if (phydev->speed == SPEED_100) {
  163. val &= ~ENETC_PM_IFM_SSP_MASK;
  164. val |= ENETC_PM_IFM_SSP_100;
  165. } else if (phydev->speed == SPEED_10) {
  166. val &= ~ENETC_PM_IFM_SSP_MASK;
  167. val |= ENETC_PM_IFM_SSP_10;
  168. }
  169. if (phydev->duplex == DUPLEX_FULL)
  170. val |= ENETC_PM_IFM_FULL_DPX;
  171. else
  172. val &= ~ENETC_PM_IFM_FULL_DPX;
  173. if (val == old_val)
  174. return;
  175. enetc_write_port(priv, ENETC_PM_IF_MODE, val);
  176. }
  177. /* set up MAC configuration for the given interface type */
  178. static void enetc_setup_mac_iface(struct udevice *dev,
  179. struct phy_device *phydev)
  180. {
  181. struct enetc_priv *priv = dev_get_priv(dev);
  182. u32 if_mode;
  183. switch (priv->if_type) {
  184. case PHY_INTERFACE_MODE_RGMII:
  185. case PHY_INTERFACE_MODE_RGMII_ID:
  186. case PHY_INTERFACE_MODE_RGMII_RXID:
  187. case PHY_INTERFACE_MODE_RGMII_TXID:
  188. enetc_init_rgmii(dev, phydev);
  189. break;
  190. case PHY_INTERFACE_MODE_XGMII:
  191. case PHY_INTERFACE_MODE_USXGMII:
  192. case PHY_INTERFACE_MODE_XFI:
  193. /* set ifmode to (US)XGMII */
  194. if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
  195. if_mode &= ~ENETC_PM_IF_IFMODE_MASK;
  196. enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
  197. break;
  198. };
  199. }
  200. /* set up serdes for SXGMII */
  201. static int enetc_init_sxgmii(struct udevice *dev)
  202. {
  203. struct enetc_priv *priv = dev_get_priv(dev);
  204. if (!enetc_has_imdio(dev))
  205. return 0;
  206. /* Dev ability - SXGMII */
  207. enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
  208. ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);
  209. /* Restart PCS AN */
  210. enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
  211. ENETC_PCS_CR,
  212. ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);
  213. return 0;
  214. }
  215. /* Apply protocol specific configuration to MAC, serdes as needed */
  216. static void enetc_start_pcs(struct udevice *dev)
  217. {
  218. struct enetc_priv *priv = dev_get_priv(dev);
  219. const char *if_str;
  220. priv->if_type = PHY_INTERFACE_MODE_NONE;
  221. /* register internal MDIO for debug purposes */
  222. if (enetc_read_port(priv, ENETC_PCAPR0) & ENETC_PCAPRO_MDIO) {
  223. priv->imdio.read = enetc_mdio_read;
  224. priv->imdio.write = enetc_mdio_write;
  225. priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE;
  226. strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
  227. if (!miiphy_get_dev_by_name(priv->imdio.name))
  228. mdio_register(&priv->imdio);
  229. }
  230. if (!ofnode_valid(dev_ofnode(dev))) {
  231. enetc_dbg(dev, "no enetc ofnode found, skipping PCS set-up\n");
  232. return;
  233. }
  234. if_str = ofnode_read_string(dev_ofnode(dev), "phy-mode");
  235. if (if_str)
  236. priv->if_type = phy_get_interface_by_name(if_str);
  237. else
  238. enetc_dbg(dev,
  239. "phy-mode property not found, defaulting to SGMII\n");
  240. if (priv->if_type < 0)
  241. priv->if_type = PHY_INTERFACE_MODE_NONE;
  242. switch (priv->if_type) {
  243. case PHY_INTERFACE_MODE_SGMII:
  244. case PHY_INTERFACE_MODE_SGMII_2500:
  245. enetc_init_sgmii(dev);
  246. break;
  247. case PHY_INTERFACE_MODE_XGMII:
  248. case PHY_INTERFACE_MODE_USXGMII:
  249. case PHY_INTERFACE_MODE_XFI:
  250. enetc_init_sxgmii(dev);
  251. break;
  252. };
  253. }
  254. /* Configure the actual/external ethernet PHY, if one is found */
  255. static int enetc_config_phy(struct udevice *dev)
  256. {
  257. struct enetc_priv *priv = dev_get_priv(dev);
  258. int supported;
  259. priv->phy = dm_eth_phy_connect(dev);
  260. if (!priv->phy)
  261. return -ENODEV;
  262. supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
  263. priv->phy->supported &= supported;
  264. priv->phy->advertising &= supported;
  265. return phy_config(priv->phy);
  266. }
  267. /*
  268. * Probe ENETC driver:
  269. * - initialize port and station interface BARs
  270. */
  271. static int enetc_probe(struct udevice *dev)
  272. {
  273. struct enetc_priv *priv = dev_get_priv(dev);
  274. if (ofnode_valid(dev_ofnode(dev)) && !ofnode_is_available(dev_ofnode(dev))) {
  275. enetc_dbg(dev, "interface disabled\n");
  276. return -ENODEV;
  277. }
  278. priv->enetc_txbd = memalign(ENETC_BD_ALIGN,
  279. sizeof(struct enetc_tx_bd) * ENETC_BD_CNT);
  280. priv->enetc_rxbd = memalign(ENETC_BD_ALIGN,
  281. sizeof(union enetc_rx_bd) * ENETC_BD_CNT);
  282. if (!priv->enetc_txbd || !priv->enetc_rxbd) {
  283. /* free should be able to handle NULL, just free all pointers */
  284. free(priv->enetc_txbd);
  285. free(priv->enetc_rxbd);
  286. return -ENOMEM;
  287. }
  288. /* initialize register */
  289. priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
  290. if (!priv->regs_base) {
  291. enetc_dbg(dev, "failed to map BAR0\n");
  292. return -EINVAL;
  293. }
  294. priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF;
  295. dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
  296. enetc_start_pcs(dev);
  297. return enetc_config_phy(dev);
  298. }
  299. /*
  300. * Remove the driver from an interface:
  301. * - free up allocated memory
  302. */
  303. static int enetc_remove(struct udevice *dev)
  304. {
  305. struct enetc_priv *priv = dev_get_priv(dev);
  306. free(priv->enetc_txbd);
  307. free(priv->enetc_rxbd);
  308. return 0;
  309. }
  310. /*
  311. * LS1028A is the only part with IERB at this time and there are plans to
  312. * change its structure, keep this LS1028A specific for now.
  313. */
  314. #define LS1028A_IERB_BASE 0x1f0800000ULL
  315. #define LS1028A_IERB_PSIPMAR0(pf, vf) (LS1028A_IERB_BASE + 0x8000 \
  316. + (pf) * 0x100 + (vf) * 8)
  317. #define LS1028A_IERB_PSIPMAR1(pf, vf) (LS1028A_IERB_PSIPMAR0(pf, vf) + 4)
  318. static int enetc_ls1028a_write_hwaddr(struct udevice *dev)
  319. {
  320. struct pci_child_plat *ppdata = dev_get_parent_plat(dev);
  321. const int devfn_to_pf[] = {0, 1, 2, -1, -1, -1, 3};
  322. struct eth_pdata *plat = dev_get_plat(dev);
  323. int devfn = PCI_FUNC(ppdata->devfn);
  324. u8 *addr = plat->enetaddr;
  325. u32 lower, upper;
  326. int pf;
  327. if (devfn >= ARRAY_SIZE(devfn_to_pf))
  328. return 0;
  329. pf = devfn_to_pf[devfn];
  330. if (pf < 0)
  331. return 0;
  332. lower = *(const u16 *)(addr + 4);
  333. upper = *(const u32 *)addr;
  334. out_le32(LS1028A_IERB_PSIPMAR0(pf, 0), upper);
  335. out_le32(LS1028A_IERB_PSIPMAR1(pf, 0), lower);
  336. return 0;
  337. }
  338. static int enetc_write_hwaddr(struct udevice *dev)
  339. {
  340. struct eth_pdata *plat = dev_get_plat(dev);
  341. struct enetc_priv *priv = dev_get_priv(dev);
  342. u8 *addr = plat->enetaddr;
  343. if (IS_ENABLED(CONFIG_ARCH_LS1028A))
  344. return enetc_ls1028a_write_hwaddr(dev);
  345. u16 lower = *(const u16 *)(addr + 4);
  346. u32 upper = *(const u32 *)addr;
  347. enetc_write_port(priv, ENETC_PSIPMAR0, upper);
  348. enetc_write_port(priv, ENETC_PSIPMAR1, lower);
  349. return 0;
  350. }
  351. /* Configure port parameters (# of rings, frame size, enable port) */
  352. static void enetc_enable_si_port(struct enetc_priv *priv)
  353. {
  354. u32 val;
  355. /* set Rx/Tx BDR count */
  356. val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT);
  357. val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT);
  358. enetc_write_port(priv, ENETC_PSICFGR(0), val);
  359. /* set Rx max frame size */
  360. enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE);
  361. /* enable MAC port */
  362. enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN);
  363. /* enable port */
  364. enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN);
  365. /* set SI cache policy */
  366. enetc_write(priv, ENETC_SICAR0,
  367. ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG);
  368. /* enable SI */
  369. enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN);
  370. }
  371. /* returns DMA address for a given buffer index */
  372. static inline u64 enetc_rxb_address(struct udevice *dev, int i)
  373. {
  374. return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i]));
  375. }
  376. /*
  377. * Setup a single Tx BD Ring (ID = 0):
  378. * - set Tx buffer descriptor address
  379. * - set the BD count
  380. * - initialize the producer and consumer index
  381. */
  382. static void enetc_setup_tx_bdr(struct udevice *dev)
  383. {
  384. struct enetc_priv *priv = dev_get_priv(dev);
  385. struct bd_ring *tx_bdr = &priv->tx_bdr;
  386. u64 tx_bd_add = (u64)priv->enetc_txbd;
  387. /* used later to advance to the next Tx BD */
  388. tx_bdr->bd_count = ENETC_BD_CNT;
  389. tx_bdr->next_prod_idx = 0;
  390. tx_bdr->next_cons_idx = 0;
  391. tx_bdr->cons_idx = priv->regs_base +
  392. ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR);
  393. tx_bdr->prod_idx = priv->regs_base +
  394. ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR);
  395. /* set Tx BD address */
  396. enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0,
  397. lower_32_bits(tx_bd_add));
  398. enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1,
  399. upper_32_bits(tx_bd_add));
  400. /* set Tx 8 BD count */
  401. enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR,
  402. tx_bdr->bd_count);
  403. /* reset both producer/consumer indexes */
  404. enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx);
  405. enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx);
  406. /* enable TX ring */
  407. enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN);
  408. }
  409. /*
  410. * Setup a single Rx BD Ring (ID = 0):
  411. * - set Rx buffer descriptors address (one descriptor per buffer)
  412. * - set buffer size as max frame size
  413. * - enable Rx ring
  414. * - reset consumer and producer indexes
  415. * - set buffer for each descriptor
  416. */
  417. static void enetc_setup_rx_bdr(struct udevice *dev)
  418. {
  419. struct enetc_priv *priv = dev_get_priv(dev);
  420. struct bd_ring *rx_bdr = &priv->rx_bdr;
  421. u64 rx_bd_add = (u64)priv->enetc_rxbd;
  422. int i;
  423. /* used later to advance to the next BD produced by ENETC HW */
  424. rx_bdr->bd_count = ENETC_BD_CNT;
  425. rx_bdr->next_prod_idx = 0;
  426. rx_bdr->next_cons_idx = 0;
  427. rx_bdr->cons_idx = priv->regs_base +
  428. ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR);
  429. rx_bdr->prod_idx = priv->regs_base +
  430. ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR);
  431. /* set Rx BD address */
  432. enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0,
  433. lower_32_bits(rx_bd_add));
  434. enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1,
  435. upper_32_bits(rx_bd_add));
  436. /* set Rx BD count (multiple of 8) */
  437. enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR,
  438. rx_bdr->bd_count);
  439. /* set Rx buffer size */
  440. enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN);
  441. /* fill Rx BD */
  442. memset(priv->enetc_rxbd, 0,
  443. rx_bdr->bd_count * sizeof(union enetc_rx_bd));
  444. for (i = 0; i < rx_bdr->bd_count; i++) {
  445. priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i);
  446. /* each RX buffer must be aligned to 64B */
  447. WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1));
  448. }
  449. /* reset producer (ENETC owned) and consumer (SW owned) index */
  450. enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx);
  451. enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx);
  452. /* enable Rx ring */
  453. enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN);
  454. }
  455. /*
  456. * Start ENETC interface:
  457. * - perform FLR
  458. * - enable access to port and SI registers
  459. * - set mac address
  460. * - setup TX/RX buffer descriptors
  461. * - enable Tx/Rx rings
  462. */
  463. static int enetc_start(struct udevice *dev)
  464. {
  465. struct enetc_priv *priv = dev_get_priv(dev);
  466. /* reset and enable the PCI device */
  467. dm_pci_flr(dev);
  468. dm_pci_clrset_config16(dev, PCI_COMMAND, 0,
  469. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  470. enetc_enable_si_port(priv);
  471. /* setup Tx/Rx buffer descriptors */
  472. enetc_setup_tx_bdr(dev);
  473. enetc_setup_rx_bdr(dev);
  474. enetc_setup_mac_iface(dev, priv->phy);
  475. return phy_startup(priv->phy);
  476. }
  477. /*
  478. * Stop the network interface:
  479. * - just quiesce it, we can wipe all configuration as _start starts from
  480. * scratch each time
  481. */
  482. static void enetc_stop(struct udevice *dev)
  483. {
  484. /* FLR is sufficient to quiesce the device */
  485. dm_pci_flr(dev);
  486. /* leave the BARs accessible after we stop, this is needed to use
  487. * internal MDIO in command line.
  488. */
  489. dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
  490. }
  491. /*
  492. * ENETC transmit packet:
  493. * - check if Tx BD ring is full
  494. * - set buffer/packet address (dma address)
  495. * - set final fragment flag
  496. * - try while producer index equals consumer index or timeout
  497. */
  498. static int enetc_send(struct udevice *dev, void *packet, int length)
  499. {
  500. struct enetc_priv *priv = dev_get_priv(dev);
  501. struct bd_ring *txr = &priv->tx_bdr;
  502. void *nv_packet = (void *)packet;
  503. int tries = ENETC_POLL_TRIES;
  504. u32 pi, ci;
  505. pi = txr->next_prod_idx;
  506. ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK;
  507. /* Tx ring is full when */
  508. if (((pi + 1) % txr->bd_count) == ci) {
  509. enetc_dbg(dev, "Tx BDR full\n");
  510. return -ETIMEDOUT;
  511. }
  512. enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length,
  513. upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet));
  514. /* prepare Tx BD */
  515. memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd));
  516. priv->enetc_txbd[pi].addr =
  517. cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet));
  518. priv->enetc_txbd[pi].buf_len = cpu_to_le16(length);
  519. priv->enetc_txbd[pi].frm_len = cpu_to_le16(length);
  520. priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F);
  521. dmb();
  522. /* send frame: increment producer index */
  523. pi = (pi + 1) % txr->bd_count;
  524. txr->next_prod_idx = pi;
  525. enetc_write_reg(txr->prod_idx, pi);
  526. while ((--tries >= 0) &&
  527. (pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK)))
  528. udelay(10);
  529. return tries > 0 ? 0 : -ETIMEDOUT;
  530. }
  531. /*
  532. * Receive frame:
  533. * - wait for the next BD to get ready bit set
  534. * - clean up the descriptor
  535. * - move on and indicate to HW that the cleaned BD is available for Rx
  536. */
  537. static int enetc_recv(struct udevice *dev, int flags, uchar **packetp)
  538. {
  539. struct enetc_priv *priv = dev_get_priv(dev);
  540. struct bd_ring *rxr = &priv->rx_bdr;
  541. int tries = ENETC_POLL_TRIES;
  542. int pi = rxr->next_prod_idx;
  543. int ci = rxr->next_cons_idx;
  544. u32 status;
  545. int len;
  546. u8 rdy;
  547. do {
  548. dmb();
  549. status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus);
  550. /* check if current BD is ready to be consumed */
  551. rdy = ENETC_RXBD_STATUS_R(status);
  552. } while (--tries >= 0 && !rdy);
  553. if (!rdy)
  554. return -EAGAIN;
  555. dmb();
  556. len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len);
  557. *packetp = (uchar *)enetc_rxb_address(dev, pi);
  558. enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len,
  559. ENETC_RXBD_STATUS_ERRORS(status),
  560. upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp));
  561. /* BD clean up and advance to next in ring */
  562. memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd));
  563. priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi);
  564. rxr->next_prod_idx = (pi + 1) % rxr->bd_count;
  565. ci = (ci + 1) % rxr->bd_count;
  566. rxr->next_cons_idx = ci;
  567. dmb();
  568. /* free up the slot in the ring for HW */
  569. enetc_write_reg(rxr->cons_idx, ci);
  570. return len;
  571. }
  572. static const struct eth_ops enetc_ops = {
  573. .start = enetc_start,
  574. .send = enetc_send,
  575. .recv = enetc_recv,
  576. .stop = enetc_stop,
  577. .write_hwaddr = enetc_write_hwaddr,
  578. };
  579. U_BOOT_DRIVER(eth_enetc) = {
  580. .name = ENETC_DRIVER_NAME,
  581. .id = UCLASS_ETH,
  582. .bind = enetc_bind,
  583. .probe = enetc_probe,
  584. .remove = enetc_remove,
  585. .ops = &enetc_ops,
  586. .priv_auto = sizeof(struct enetc_priv),
  587. .plat_auto = sizeof(struct eth_pdata),
  588. };
  589. static struct pci_device_id enetc_ids[] = {
  590. { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) },
  591. {}
  592. };
  593. U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids);