eth.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2012 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. * Dave Liu <daveliu@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <log.h>
  9. #include <part.h>
  10. #include <asm/io.h>
  11. #ifdef CONFIG_DM_ETH
  12. #include <dm.h>
  13. #include <dm/ofnode.h>
  14. #include <linux/compat.h>
  15. #include <phy_interface.h>
  16. #endif
  17. #include <malloc.h>
  18. #include <net.h>
  19. #include <hwconfig.h>
  20. #include <fm_eth.h>
  21. #include <fsl_mdio.h>
  22. #include <miiphy.h>
  23. #include <phy.h>
  24. #include <fsl_dtsec.h>
  25. #include <fsl_tgec.h>
  26. #include <fsl_memac.h>
  27. #include <linux/delay.h>
  28. #include "fm.h"
  29. #ifndef CONFIG_DM_ETH
  30. static struct eth_device *devlist[NUM_FM_PORTS];
  31. static int num_controllers;
  32. #endif
  33. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
  34. #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
  35. TBIANA_FULL_DUPLEX)
  36. #define TBIANA_SGMII_ACK 0x4001
  37. #define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
  38. TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
  39. /* Configure the TBI for SGMII operation */
  40. static void dtsec_configure_serdes(struct fm_eth *priv)
  41. {
  42. #ifdef CONFIG_SYS_FMAN_V3
  43. u32 value;
  44. struct mii_dev bus;
  45. bool sgmii_2500 = (priv->enet_if ==
  46. PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
  47. int i = 0, j;
  48. #ifndef CONFIG_DM_ETH
  49. bus.priv = priv->mac->phyregs;
  50. #else
  51. bus.priv = priv->pcs_mdio;
  52. bus.read = memac_mdio_read;
  53. bus.write = memac_mdio_write;
  54. bus.reset = memac_mdio_reset;
  55. #endif
  56. qsgmii_loop:
  57. /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
  58. if (sgmii_2500)
  59. value = PHY_SGMII_CR_PHY_RESET |
  60. PHY_SGMII_IF_SPEED_GIGABIT |
  61. PHY_SGMII_IF_MODE_SGMII;
  62. else
  63. value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
  64. for (j = 0; j <= 3; j++)
  65. debug("dump PCS reg %#x: %#x\n", j,
  66. memac_mdio_read(&bus, i, MDIO_DEVAD_NONE, j));
  67. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
  68. /* Dev ability according to SGMII specification */
  69. value = PHY_SGMII_DEV_ABILITY_SGMII;
  70. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
  71. if (sgmii_2500) {
  72. /* Adjust link timer for 2.5G SGMII,
  73. * 1.6 ms in units of 3.2 ns:
  74. * 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
  75. */
  76. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
  77. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
  78. } else {
  79. /* Adjust link timer for SGMII,
  80. * 1.6 ms in units of 8 ns:
  81. * 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
  82. */
  83. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003);
  84. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);
  85. }
  86. /* Restart AN */
  87. value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
  88. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
  89. if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
  90. i++;
  91. goto qsgmii_loop;
  92. }
  93. #else
  94. struct dtsec *regs = priv->mac->base;
  95. struct tsec_mii_mng *phyregs = priv->mac->phyregs;
  96. /*
  97. * Access TBI PHY registers at given TSEC register offset as
  98. * opposed to the register offset used for external PHY accesses
  99. */
  100. tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_TBICON,
  101. TBICON_CLK_SELECT);
  102. tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_ANA,
  103. TBIANA_SGMII_ACK);
  104. tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,
  105. TBI_CR, TBICR_SETTINGS);
  106. #endif
  107. }
  108. static void dtsec_init_phy(struct fm_eth *fm_eth)
  109. {
  110. #ifndef CONFIG_SYS_FMAN_V3
  111. struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
  112. /* Assign a Physical address to the TBI */
  113. out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
  114. #endif
  115. if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
  116. fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
  117. fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
  118. dtsec_configure_serdes(fm_eth);
  119. }
  120. #ifndef CONFIG_DM_ETH
  121. #ifdef CONFIG_PHYLIB
  122. static int tgec_is_fibre(struct fm_eth *fm)
  123. {
  124. char phyopt[20];
  125. sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
  126. return hwconfig_arg_cmp(phyopt, "xfi");
  127. }
  128. #endif
  129. #endif /* CONFIG_DM_ETH */
  130. #endif
  131. static u16 muram_readw(u16 *addr)
  132. {
  133. ulong base = (ulong)addr & ~0x3UL;
  134. u32 val32 = in_be32((void *)base);
  135. int byte_pos;
  136. u16 ret;
  137. byte_pos = (ulong)addr & 0x3UL;
  138. if (byte_pos)
  139. ret = (u16)(val32 & 0x0000ffff);
  140. else
  141. ret = (u16)((val32 & 0xffff0000) >> 16);
  142. return ret;
  143. }
  144. static void muram_writew(u16 *addr, u16 val)
  145. {
  146. ulong base = (ulong)addr & ~0x3UL;
  147. u32 org32 = in_be32((void *)base);
  148. u32 val32;
  149. int byte_pos;
  150. byte_pos = (ulong)addr & 0x3UL;
  151. if (byte_pos)
  152. val32 = (org32 & 0xffff0000) | val;
  153. else
  154. val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
  155. out_be32((void *)base, val32);
  156. }
  157. static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
  158. {
  159. int timeout = 1000000;
  160. clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
  161. /* wait until the rx port is not busy */
  162. while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
  163. ;
  164. if (!timeout)
  165. printf("%s - timeout\n", __func__);
  166. }
  167. static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
  168. {
  169. /* set BMI to independent mode, Rx port disable */
  170. out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
  171. /* clear FOF in IM case */
  172. out_be32(&rx_port->fmbm_rim, 0);
  173. /* Rx frame next engine -RISC */
  174. out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
  175. /* Rx command attribute - no order, MR[3] = 1 */
  176. clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
  177. setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
  178. /* enable Rx statistic counters */
  179. out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
  180. /* disable Rx performance counters */
  181. out_be32(&rx_port->fmbm_rpc, 0);
  182. }
  183. static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
  184. {
  185. int timeout = 1000000;
  186. clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
  187. /* wait until the tx port is not busy */
  188. while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
  189. ;
  190. if (!timeout)
  191. printf("%s - timeout\n", __func__);
  192. }
  193. static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
  194. {
  195. /* set BMI to independent mode, Tx port disable */
  196. out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
  197. /* Tx frame next engine -RISC */
  198. out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
  199. out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
  200. /* Tx command attribute - no order, MR[3] = 1 */
  201. clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
  202. setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
  203. /* enable Tx statistic counters */
  204. out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
  205. /* disable Tx performance counters */
  206. out_be32(&tx_port->fmbm_tpc, 0);
  207. }
  208. static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
  209. {
  210. struct fm_port_global_pram *pram;
  211. u32 pram_page_offset;
  212. void *rx_bd_ring_base;
  213. void *rx_buf_pool;
  214. u32 bd_ring_base_lo, bd_ring_base_hi;
  215. u32 buf_lo, buf_hi;
  216. struct fm_port_bd *rxbd;
  217. struct fm_port_qd *rxqd;
  218. struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
  219. int i;
  220. /* alloc global parameter ram at MURAM */
  221. pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
  222. FM_PRAM_SIZE, FM_PRAM_ALIGN);
  223. if (!pram) {
  224. printf("%s: No muram for Rx global parameter\n", __func__);
  225. return -ENOMEM;
  226. }
  227. fm_eth->rx_pram = pram;
  228. /* parameter page offset to MURAM */
  229. pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
  230. /* enable global mode- snooping data buffers and BDs */
  231. out_be32(&pram->mode, PRAM_MODE_GLOBAL);
  232. /* init the Rx queue descriptor pionter */
  233. out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
  234. /* set the max receive buffer length, power of 2 */
  235. muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
  236. /* alloc Rx buffer descriptors from main memory */
  237. rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
  238. * RX_BD_RING_SIZE);
  239. if (!rx_bd_ring_base)
  240. return -ENOMEM;
  241. memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
  242. * RX_BD_RING_SIZE);
  243. /* alloc Rx buffer from main memory */
  244. rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
  245. if (!rx_buf_pool) {
  246. free(rx_bd_ring_base);
  247. return -ENOMEM;
  248. }
  249. memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
  250. debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
  251. /* save them to fm_eth */
  252. fm_eth->rx_bd_ring = rx_bd_ring_base;
  253. fm_eth->cur_rxbd = rx_bd_ring_base;
  254. fm_eth->rx_buf = rx_buf_pool;
  255. /* init Rx BDs ring */
  256. rxbd = (struct fm_port_bd *)rx_bd_ring_base;
  257. for (i = 0; i < RX_BD_RING_SIZE; i++) {
  258. muram_writew(&rxbd->status, RxBD_EMPTY);
  259. muram_writew(&rxbd->len, 0);
  260. buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
  261. i * MAX_RXBUF_LEN));
  262. buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
  263. i * MAX_RXBUF_LEN));
  264. muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
  265. out_be32(&rxbd->buf_ptr_lo, buf_lo);
  266. rxbd++;
  267. }
  268. /* set the Rx queue descriptor */
  269. rxqd = &pram->rxqd;
  270. muram_writew(&rxqd->gen, 0);
  271. bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
  272. bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
  273. muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
  274. out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
  275. muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
  276. * RX_BD_RING_SIZE);
  277. muram_writew(&rxqd->offset_in, 0);
  278. muram_writew(&rxqd->offset_out, 0);
  279. /* set IM parameter ram pointer to Rx Frame Queue ID */
  280. out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
  281. return 0;
  282. }
  283. static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
  284. {
  285. struct fm_port_global_pram *pram;
  286. u32 pram_page_offset;
  287. void *tx_bd_ring_base;
  288. u32 bd_ring_base_lo, bd_ring_base_hi;
  289. struct fm_port_bd *txbd;
  290. struct fm_port_qd *txqd;
  291. struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
  292. int i;
  293. /* alloc global parameter ram at MURAM */
  294. pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
  295. FM_PRAM_SIZE, FM_PRAM_ALIGN);
  296. if (!pram) {
  297. printf("%s: No muram for Tx global parameter\n", __func__);
  298. return -ENOMEM;
  299. }
  300. fm_eth->tx_pram = pram;
  301. /* parameter page offset to MURAM */
  302. pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
  303. /* enable global mode- snooping data buffers and BDs */
  304. out_be32(&pram->mode, PRAM_MODE_GLOBAL);
  305. /* init the Tx queue descriptor pionter */
  306. out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
  307. /* alloc Tx buffer descriptors from main memory */
  308. tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
  309. * TX_BD_RING_SIZE);
  310. if (!tx_bd_ring_base)
  311. return -ENOMEM;
  312. memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
  313. * TX_BD_RING_SIZE);
  314. /* save it to fm_eth */
  315. fm_eth->tx_bd_ring = tx_bd_ring_base;
  316. fm_eth->cur_txbd = tx_bd_ring_base;
  317. /* init Tx BDs ring */
  318. txbd = (struct fm_port_bd *)tx_bd_ring_base;
  319. for (i = 0; i < TX_BD_RING_SIZE; i++) {
  320. muram_writew(&txbd->status, TxBD_LAST);
  321. muram_writew(&txbd->len, 0);
  322. muram_writew(&txbd->buf_ptr_hi, 0);
  323. out_be32(&txbd->buf_ptr_lo, 0);
  324. txbd++;
  325. }
  326. /* set the Tx queue decriptor */
  327. txqd = &pram->txqd;
  328. bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base));
  329. bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base));
  330. muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
  331. out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo);
  332. muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
  333. * TX_BD_RING_SIZE);
  334. muram_writew(&txqd->offset_in, 0);
  335. muram_writew(&txqd->offset_out, 0);
  336. /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
  337. out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
  338. return 0;
  339. }
  340. static int fm_eth_init(struct fm_eth *fm_eth)
  341. {
  342. int ret;
  343. ret = fm_eth_rx_port_parameter_init(fm_eth);
  344. if (ret)
  345. return ret;
  346. ret = fm_eth_tx_port_parameter_init(fm_eth);
  347. if (ret)
  348. return ret;
  349. return 0;
  350. }
  351. static int fm_eth_startup(struct fm_eth *fm_eth)
  352. {
  353. struct fsl_enet_mac *mac;
  354. int ret;
  355. mac = fm_eth->mac;
  356. /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
  357. ret = fm_eth_init(fm_eth);
  358. if (ret)
  359. return ret;
  360. /* setup the MAC controller */
  361. mac->init_mac(mac);
  362. /* For some reason we need to set SPEED_100 */
  363. if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
  364. (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
  365. (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
  366. mac->set_if_mode)
  367. mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
  368. /* init bmi rx port, IM mode and disable */
  369. bmi_rx_port_init(fm_eth->rx_port);
  370. /* init bmi tx port, IM mode and disable */
  371. bmi_tx_port_init(fm_eth->tx_port);
  372. return 0;
  373. }
  374. static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
  375. {
  376. struct fm_port_global_pram *pram;
  377. pram = fm_eth->tx_pram;
  378. /* graceful stop transmission of frames */
  379. setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
  380. sync();
  381. }
  382. static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
  383. {
  384. struct fm_port_global_pram *pram;
  385. pram = fm_eth->tx_pram;
  386. /* re-enable transmission of frames */
  387. clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
  388. sync();
  389. }
  390. #ifndef CONFIG_DM_ETH
  391. static int fm_eth_open(struct eth_device *dev, struct bd_info *bd)
  392. #else
  393. static int fm_eth_open(struct udevice *dev)
  394. #endif
  395. {
  396. #ifndef CONFIG_DM_ETH
  397. struct fm_eth *fm_eth = dev->priv;
  398. #else
  399. struct eth_pdata *pdata = dev_get_plat(dev);
  400. struct fm_eth *fm_eth = dev_get_priv(dev);
  401. #endif
  402. unsigned char *enetaddr;
  403. struct fsl_enet_mac *mac;
  404. #ifdef CONFIG_PHYLIB
  405. int ret;
  406. #endif
  407. mac = fm_eth->mac;
  408. #ifndef CONFIG_DM_ETH
  409. enetaddr = &dev->enetaddr[0];
  410. #else
  411. enetaddr = pdata->enetaddr;
  412. #endif
  413. /* setup the MAC address */
  414. if (enetaddr[0] & 0x01) {
  415. printf("%s: MacAddress is multicast address\n", __func__);
  416. enetaddr[0] = 0;
  417. enetaddr[5] = fm_eth->num;
  418. }
  419. mac->set_mac_addr(mac, enetaddr);
  420. /* enable bmi Rx port */
  421. setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
  422. /* enable MAC rx/tx port */
  423. mac->enable_mac(mac);
  424. /* enable bmi Tx port */
  425. setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
  426. /* re-enable transmission of frame */
  427. fmc_tx_port_graceful_stop_disable(fm_eth);
  428. #ifdef CONFIG_PHYLIB
  429. if (fm_eth->phydev) {
  430. ret = phy_startup(fm_eth->phydev);
  431. if (ret) {
  432. #ifndef CONFIG_DM_ETH
  433. printf("%s: Could not initialize\n",
  434. fm_eth->phydev->dev->name);
  435. #else
  436. printf("%s: Could not initialize\n", dev->name);
  437. #endif
  438. return ret;
  439. }
  440. } else {
  441. return 0;
  442. }
  443. #else
  444. fm_eth->phydev->speed = SPEED_1000;
  445. fm_eth->phydev->link = 1;
  446. fm_eth->phydev->duplex = DUPLEX_FULL;
  447. #endif
  448. /* set the MAC-PHY mode */
  449. mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
  450. debug("MAC IF mode %d, speed %d, link %d\n", fm_eth->enet_if,
  451. fm_eth->phydev->speed, fm_eth->phydev->link);
  452. if (!fm_eth->phydev->link)
  453. printf("%s: No link.\n", fm_eth->phydev->dev->name);
  454. return fm_eth->phydev->link ? 0 : -1;
  455. }
  456. #ifndef CONFIG_DM_ETH
  457. static void fm_eth_halt(struct eth_device *dev)
  458. #else
  459. static void fm_eth_halt(struct udevice *dev)
  460. #endif
  461. {
  462. struct fm_eth *fm_eth;
  463. struct fsl_enet_mac *mac;
  464. #ifndef CONFIG_DM_ETH
  465. fm_eth = (struct fm_eth *)dev->priv;
  466. #else
  467. fm_eth = dev_get_priv(dev);
  468. #endif
  469. mac = fm_eth->mac;
  470. /* graceful stop the transmission of frames */
  471. fmc_tx_port_graceful_stop_enable(fm_eth);
  472. /* disable bmi Tx port */
  473. bmi_tx_port_disable(fm_eth->tx_port);
  474. /* disable MAC rx/tx port */
  475. mac->disable_mac(mac);
  476. /* disable bmi Rx port */
  477. bmi_rx_port_disable(fm_eth->rx_port);
  478. #ifdef CONFIG_PHYLIB
  479. if (fm_eth->phydev)
  480. phy_shutdown(fm_eth->phydev);
  481. #endif
  482. }
  483. #ifndef CONFIG_DM_ETH
  484. static int fm_eth_send(struct eth_device *dev, void *buf, int len)
  485. #else
  486. static int fm_eth_send(struct udevice *dev, void *buf, int len)
  487. #endif
  488. {
  489. struct fm_eth *fm_eth;
  490. struct fm_port_global_pram *pram;
  491. struct fm_port_bd *txbd, *txbd_base;
  492. u16 offset_in;
  493. int i;
  494. #ifndef CONFIG_DM_ETH
  495. fm_eth = (struct fm_eth *)dev->priv;
  496. #else
  497. fm_eth = dev_get_priv(dev);
  498. #endif
  499. pram = fm_eth->tx_pram;
  500. txbd = fm_eth->cur_txbd;
  501. /* find one empty TxBD */
  502. for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
  503. udelay(100);
  504. if (i > 0x1000) {
  505. printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
  506. dev->name, muram_readw(&txbd->status));
  507. return 0;
  508. }
  509. }
  510. /* setup TxBD */
  511. muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf)));
  512. out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf)));
  513. muram_writew(&txbd->len, len);
  514. sync();
  515. muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
  516. sync();
  517. /* update TxQD, let RISC to send the packet */
  518. offset_in = muram_readw(&pram->txqd.offset_in);
  519. offset_in += sizeof(struct fm_port_bd);
  520. if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
  521. offset_in = 0;
  522. muram_writew(&pram->txqd.offset_in, offset_in);
  523. sync();
  524. /* wait for buffer to be transmitted */
  525. for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
  526. udelay(100);
  527. if (i > 0x10000) {
  528. printf("%s: Tx error, txbd->status = 0x%x\n",
  529. dev->name, muram_readw(&txbd->status));
  530. return 0;
  531. }
  532. }
  533. /* advance the TxBD */
  534. txbd++;
  535. txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
  536. if (txbd >= (txbd_base + TX_BD_RING_SIZE))
  537. txbd = txbd_base;
  538. /* update current txbd */
  539. fm_eth->cur_txbd = (void *)txbd;
  540. return 1;
  541. }
  542. static struct fm_port_bd *fm_eth_free_one(struct fm_eth *fm_eth,
  543. struct fm_port_bd *rxbd)
  544. {
  545. struct fm_port_global_pram *pram;
  546. struct fm_port_bd *rxbd_base;
  547. u16 offset_out;
  548. pram = fm_eth->rx_pram;
  549. /* clear the RxBDs */
  550. muram_writew(&rxbd->status, RxBD_EMPTY);
  551. muram_writew(&rxbd->len, 0);
  552. sync();
  553. /* advance RxBD */
  554. rxbd++;
  555. rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
  556. if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
  557. rxbd = rxbd_base;
  558. /* update RxQD */
  559. offset_out = muram_readw(&pram->rxqd.offset_out);
  560. offset_out += sizeof(struct fm_port_bd);
  561. if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
  562. offset_out = 0;
  563. muram_writew(&pram->rxqd.offset_out, offset_out);
  564. sync();
  565. return rxbd;
  566. }
  567. #ifndef CONFIG_DM_ETH
  568. static int fm_eth_recv(struct eth_device *dev)
  569. #else
  570. static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  571. #endif
  572. {
  573. struct fm_eth *fm_eth;
  574. struct fm_port_bd *rxbd;
  575. u32 buf_lo, buf_hi;
  576. u16 status, len;
  577. int ret = -1;
  578. u8 *data;
  579. #ifndef CONFIG_DM_ETH
  580. fm_eth = (struct fm_eth *)dev->priv;
  581. #else
  582. fm_eth = dev_get_priv(dev);
  583. #endif
  584. rxbd = fm_eth->cur_rxbd;
  585. status = muram_readw(&rxbd->status);
  586. while (!(status & RxBD_EMPTY)) {
  587. if (!(status & RxBD_ERROR)) {
  588. buf_hi = muram_readw(&rxbd->buf_ptr_hi);
  589. buf_lo = in_be32(&rxbd->buf_ptr_lo);
  590. data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
  591. len = muram_readw(&rxbd->len);
  592. #ifndef CONFIG_DM_ETH
  593. net_process_received_packet(data, len);
  594. #else
  595. *packetp = data;
  596. return len;
  597. #endif
  598. } else {
  599. printf("%s: Rx error\n", dev->name);
  600. ret = 0;
  601. }
  602. /* free current bd, advance to next one */
  603. rxbd = fm_eth_free_one(fm_eth, rxbd);
  604. /* read next status */
  605. status = muram_readw(&rxbd->status);
  606. }
  607. fm_eth->cur_rxbd = (void *)rxbd;
  608. return ret;
  609. }
  610. #ifdef CONFIG_DM_ETH
  611. static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
  612. {
  613. struct fm_eth *fm_eth = (struct fm_eth *)dev_get_priv(dev);
  614. fm_eth->cur_rxbd = fm_eth_free_one(fm_eth, fm_eth->cur_rxbd);
  615. return 0;
  616. }
  617. #endif /* CONFIG_DM_ETH */
  618. #ifndef CONFIG_DM_ETH
  619. static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
  620. {
  621. struct fsl_enet_mac *mac;
  622. int num;
  623. void *base, *phyregs = NULL;
  624. num = fm_eth->num;
  625. #ifdef CONFIG_SYS_FMAN_V3
  626. #ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
  627. if (fm_eth->type == FM_ETH_10G_E) {
  628. /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
  629. * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
  630. * 10GEC1 uses mEMAC1 on T1024.
  631. * so it needs to change the num.
  632. */
  633. if (fm_eth->num >= 2)
  634. num -= 2;
  635. else
  636. num += 8;
  637. }
  638. #endif
  639. base = &reg->memac[num].fm_memac;
  640. phyregs = &reg->memac[num].fm_memac_mdio;
  641. #else
  642. /* Get the mac registers base address */
  643. if (fm_eth->type == FM_ETH_1G_E) {
  644. base = &reg->mac_1g[num].fm_dtesc;
  645. phyregs = &reg->mac_1g[num].fm_mdio.miimcfg;
  646. } else {
  647. base = &reg->mac_10g[num].fm_10gec;
  648. phyregs = &reg->mac_10g[num].fm_10gec_mdio;
  649. }
  650. #endif
  651. /* alloc mac controller */
  652. mac = malloc(sizeof(struct fsl_enet_mac));
  653. if (!mac)
  654. return -ENOMEM;
  655. memset(mac, 0, sizeof(struct fsl_enet_mac));
  656. /* save the mac to fm_eth struct */
  657. fm_eth->mac = mac;
  658. #ifdef CONFIG_SYS_FMAN_V3
  659. init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
  660. #else
  661. if (fm_eth->type == FM_ETH_1G_E)
  662. init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
  663. else
  664. init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
  665. #endif
  666. return 0;
  667. }
  668. #else /* CONFIG_DM_ETH */
  669. static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg)
  670. {
  671. #ifndef CONFIG_SYS_FMAN_V3
  672. void *mdio;
  673. #endif
  674. fm_eth->mac = kzalloc(sizeof(*fm_eth->mac), GFP_KERNEL);
  675. if (!fm_eth->mac)
  676. return -ENOMEM;
  677. #ifndef CONFIG_SYS_FMAN_V3
  678. mdio = fman_mdio(fm_eth->dev->parent, fm_eth->mac_type, fm_eth->num);
  679. debug("MDIO %d @ %p\n", fm_eth->num, mdio);
  680. #endif
  681. switch (fm_eth->mac_type) {
  682. #ifdef CONFIG_SYS_FMAN_V3
  683. case FM_MEMAC:
  684. init_memac(fm_eth->mac, reg, NULL, MAX_RXBUF_LEN);
  685. break;
  686. #else
  687. case FM_DTSEC:
  688. init_dtsec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
  689. break;
  690. case FM_TGEC:
  691. init_tgec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
  692. break;
  693. #endif
  694. }
  695. return 0;
  696. }
  697. #endif /* CONFIG_DM_ETH */
  698. static int init_phy(struct fm_eth *fm_eth)
  699. {
  700. #ifdef CONFIG_PHYLIB
  701. u32 supported = PHY_GBIT_FEATURES;
  702. #ifndef CONFIG_DM_ETH
  703. struct phy_device *phydev = NULL;
  704. #endif
  705. if (fm_eth->type == FM_ETH_10G_E)
  706. supported = PHY_10G_FEATURES;
  707. if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
  708. supported |= SUPPORTED_2500baseX_Full;
  709. #endif
  710. if (fm_eth->type == FM_ETH_1G_E)
  711. dtsec_init_phy(fm_eth);
  712. #ifdef CONFIG_DM_ETH
  713. #ifdef CONFIG_PHYLIB
  714. #ifdef CONFIG_DM_MDIO
  715. fm_eth->phydev = dm_eth_phy_connect(fm_eth->dev);
  716. if (!fm_eth->phydev)
  717. return -ENODEV;
  718. #endif
  719. fm_eth->phydev->advertising &= supported;
  720. fm_eth->phydev->supported &= supported;
  721. phy_config(fm_eth->phydev);
  722. #endif
  723. #else /* CONFIG_DM_ETH */
  724. #ifdef CONFIG_PHYLIB
  725. if (fm_eth->bus) {
  726. phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, fm_eth->dev,
  727. fm_eth->enet_if);
  728. if (!phydev) {
  729. printf("Failed to connect\n");
  730. return -1;
  731. }
  732. } else {
  733. return 0;
  734. }
  735. if (fm_eth->type == FM_ETH_1G_E) {
  736. supported = (SUPPORTED_10baseT_Half |
  737. SUPPORTED_10baseT_Full |
  738. SUPPORTED_100baseT_Half |
  739. SUPPORTED_100baseT_Full |
  740. SUPPORTED_1000baseT_Full);
  741. } else {
  742. supported = SUPPORTED_10000baseT_Full;
  743. if (tgec_is_fibre(fm_eth))
  744. phydev->port = PORT_FIBRE;
  745. }
  746. phydev->supported &= supported;
  747. phydev->advertising = phydev->supported;
  748. fm_eth->phydev = phydev;
  749. phy_config(phydev);
  750. #endif
  751. #endif /* CONFIG_DM_ETH */
  752. return 0;
  753. }
  754. #ifndef CONFIG_DM_ETH
  755. int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
  756. {
  757. struct eth_device *dev;
  758. struct fm_eth *fm_eth;
  759. int i, num = info->num;
  760. int ret;
  761. /* alloc eth device */
  762. dev = (struct eth_device *)malloc(sizeof(struct eth_device));
  763. if (!dev)
  764. return -ENOMEM;
  765. memset(dev, 0, sizeof(struct eth_device));
  766. /* alloc the FMan ethernet private struct */
  767. fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
  768. if (!fm_eth)
  769. return -ENOMEM;
  770. memset(fm_eth, 0, sizeof(struct fm_eth));
  771. /* save off some things we need from the info struct */
  772. fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
  773. fm_eth->num = num;
  774. fm_eth->type = info->type;
  775. fm_eth->rx_port = (void *)&reg->port[info->rx_port_id - 1].fm_bmi;
  776. fm_eth->tx_port = (void *)&reg->port[info->tx_port_id - 1].fm_bmi;
  777. /* set the ethernet max receive length */
  778. fm_eth->max_rx_len = MAX_RXBUF_LEN;
  779. /* init global mac structure */
  780. ret = fm_eth_init_mac(fm_eth, reg);
  781. if (ret)
  782. return ret;
  783. /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
  784. if (fm_eth->type == FM_ETH_1G_E)
  785. sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
  786. else
  787. sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
  788. devlist[num_controllers++] = dev;
  789. dev->iobase = 0;
  790. dev->priv = (void *)fm_eth;
  791. dev->init = fm_eth_open;
  792. dev->halt = fm_eth_halt;
  793. dev->send = fm_eth_send;
  794. dev->recv = fm_eth_recv;
  795. fm_eth->dev = dev;
  796. fm_eth->bus = info->bus;
  797. fm_eth->phyaddr = info->phy_addr;
  798. fm_eth->enet_if = info->enet_if;
  799. /* startup the FM im */
  800. ret = fm_eth_startup(fm_eth);
  801. if (ret)
  802. return ret;
  803. init_phy(fm_eth);
  804. /* clear the ethernet address */
  805. for (i = 0; i < 6; i++)
  806. dev->enetaddr[i] = 0;
  807. eth_register(dev);
  808. return 0;
  809. }
  810. #else /* CONFIG_DM_ETH */
  811. #ifdef CONFIG_PHYLIB
  812. phy_interface_t fman_read_sys_if(struct udevice *dev)
  813. {
  814. const char *if_str;
  815. if_str = ofnode_read_string(dev_ofnode(dev), "phy-connection-type");
  816. debug("MAC system interface mode %s\n", if_str);
  817. return phy_get_interface_by_name(if_str);
  818. }
  819. #endif
  820. static int fm_eth_bind(struct udevice *dev)
  821. {
  822. char mac_name[11];
  823. u32 fm, num;
  824. if (ofnode_read_u32(ofnode_get_parent(dev_ofnode(dev)), "cell-index", &fm)) {
  825. printf("FMan node property cell-index missing\n");
  826. return -EINVAL;
  827. }
  828. if (dev && dev_read_u32(dev, "cell-index", &num)) {
  829. printf("FMan MAC node property cell-index missing\n");
  830. return -EINVAL;
  831. }
  832. sprintf(mac_name, "fm%d-mac%d", fm + 1, num + 1);
  833. device_set_name(dev, mac_name);
  834. debug("%s - binding %s\n", __func__, mac_name);
  835. return 0;
  836. }
  837. static struct udevice *fm_get_internal_mdio(struct udevice *dev)
  838. {
  839. struct ofnode_phandle_args phandle = {.node = ofnode_null()};
  840. struct udevice *mdiodev;
  841. if (dev_read_phandle_with_args(dev, "pcsphy-handle", NULL,
  842. 0, 0, &phandle) ||
  843. !ofnode_valid(phandle.node)) {
  844. if (dev_read_phandle_with_args(dev, "tbi-handle", NULL,
  845. 0, 0, &phandle) ||
  846. !ofnode_valid(phandle.node)) {
  847. printf("Issue reading pcsphy-handle/tbi-handle for MAC %s\n",
  848. dev->name);
  849. return NULL;
  850. }
  851. }
  852. if (uclass_get_device_by_ofnode(UCLASS_MDIO,
  853. ofnode_get_parent(phandle.node),
  854. &mdiodev)) {
  855. printf("can't find MDIO bus for node %s\n",
  856. ofnode_get_name(ofnode_get_parent(phandle.node)));
  857. return NULL;
  858. }
  859. debug("Found internal MDIO bus %p\n", mdiodev);
  860. return mdiodev;
  861. }
  862. static int fm_eth_probe(struct udevice *dev)
  863. {
  864. struct fm_eth *fm_eth = (struct fm_eth *)dev_get_priv(dev);
  865. struct ofnode_phandle_args args;
  866. void *reg;
  867. int ret, index;
  868. debug("%s enter for dev %p fm_eth %p - %s\n", __func__, dev, fm_eth,
  869. (dev) ? dev->name : "-");
  870. if (fm_eth->dev) {
  871. printf("%s already probed, exit\n", (dev) ? dev->name : "-");
  872. return 0;
  873. }
  874. fm_eth->dev = dev;
  875. fm_eth->fm_index = fman_id(dev->parent);
  876. reg = (void *)(uintptr_t)dev_read_addr(dev);
  877. fm_eth->mac_type = dev_get_driver_data(dev);
  878. #ifdef CONFIG_PHYLIB
  879. fm_eth->enet_if = fman_read_sys_if(dev);
  880. #else
  881. fm_eth->enet_if = PHY_INTERFACE_MODE_SGMII;
  882. printf("%s: warning - unable to determine interface type\n", __func__);
  883. #endif
  884. switch (fm_eth->mac_type) {
  885. #ifndef CONFIG_SYS_FMAN_V3
  886. case FM_TGEC:
  887. fm_eth->type = FM_ETH_10G_E;
  888. break;
  889. case FM_DTSEC:
  890. #else
  891. case FM_MEMAC:
  892. /* default to 1G, 10G is indicated by port property in dts */
  893. #endif
  894. fm_eth->type = FM_ETH_1G_E;
  895. break;
  896. }
  897. if (dev_read_u32(dev, "cell-index", &fm_eth->num)) {
  898. printf("FMan MAC node property cell-index missing\n");
  899. return -EINVAL;
  900. }
  901. if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
  902. 0, 0, &args))
  903. goto ports_ref_failure;
  904. index = ofnode_read_u32_default(args.node, "cell-index", 0);
  905. if (index <= 0)
  906. goto ports_ref_failure;
  907. fm_eth->rx_port = fman_port(dev->parent, index);
  908. if (ofnode_read_bool(args.node, "fsl,fman-10g-port"))
  909. fm_eth->type = FM_ETH_10G_E;
  910. if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
  911. 0, 1, &args))
  912. goto ports_ref_failure;
  913. index = ofnode_read_u32_default(args.node, "cell-index", 0);
  914. if (index <= 0)
  915. goto ports_ref_failure;
  916. fm_eth->tx_port = fman_port(dev->parent, index);
  917. /* set the ethernet max receive length */
  918. fm_eth->max_rx_len = MAX_RXBUF_LEN;
  919. switch (fm_eth->enet_if) {
  920. case PHY_INTERFACE_MODE_QSGMII:
  921. /* all PCS blocks are accessed on one controller */
  922. if (fm_eth->num != 0)
  923. break;
  924. case PHY_INTERFACE_MODE_SGMII:
  925. case PHY_INTERFACE_MODE_SGMII_2500:
  926. fm_eth->pcs_mdio = fm_get_internal_mdio(dev);
  927. break;
  928. default:
  929. break;
  930. }
  931. /* init global mac structure */
  932. ret = fm_eth_init_mac(fm_eth, reg);
  933. if (ret)
  934. return ret;
  935. /* startup the FM im */
  936. ret = fm_eth_startup(fm_eth);
  937. if (!ret)
  938. ret = init_phy(fm_eth);
  939. return ret;
  940. ports_ref_failure:
  941. printf("Issue reading fsl,fman-ports for MAC %s\n", dev->name);
  942. return -ENOENT;
  943. }
  944. static int fm_eth_remove(struct udevice *dev)
  945. {
  946. return 0;
  947. }
  948. static const struct eth_ops fm_eth_ops = {
  949. .start = fm_eth_open,
  950. .send = fm_eth_send,
  951. .recv = fm_eth_recv,
  952. .free_pkt = fm_eth_free_pkt,
  953. .stop = fm_eth_halt,
  954. };
  955. static const struct udevice_id fm_eth_ids[] = {
  956. #ifdef CONFIG_SYS_FMAN_V3
  957. { .compatible = "fsl,fman-memac", .data = FM_MEMAC },
  958. #else
  959. { .compatible = "fsl,fman-dtsec", .data = FM_DTSEC },
  960. { .compatible = "fsl,fman-xgec", .data = FM_TGEC },
  961. #endif
  962. {}
  963. };
  964. U_BOOT_DRIVER(eth_fman) = {
  965. .name = "eth_fman",
  966. .id = UCLASS_ETH,
  967. .of_match = fm_eth_ids,
  968. .bind = fm_eth_bind,
  969. .probe = fm_eth_probe,
  970. .remove = fm_eth_remove,
  971. .ops = &fm_eth_ops,
  972. .priv_auto = sizeof(struct fm_eth),
  973. .plat_auto = sizeof(struct eth_pdata),
  974. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  975. };
  976. #endif /* CONFIG_DM_ETH */