fec_mxc.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
  4. * (C) Copyright 2008 Armadeus Systems, nc
  5. * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
  6. * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  7. * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
  8. *
  9. * (C) Copyright 2003
  10. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  11. *
  12. * This file is based on mpc4200fec.h
  13. * (C) Copyright Motorola, Inc., 2000
  14. */
  15. #ifndef __FEC_MXC_H
  16. #define __FEC_MXC_H
  17. #include <clk.h>
  18. /* Layout description of the FEC */
  19. struct ethernet_regs {
  20. /* [10:2]addr = 00 */
  21. /* Control and status Registers (offset 000-1FF) */
  22. uint32_t res0[1]; /* MBAR_ETH + 0x000 */
  23. uint32_t ievent; /* MBAR_ETH + 0x004 */
  24. uint32_t imask; /* MBAR_ETH + 0x008 */
  25. uint32_t res1[1]; /* MBAR_ETH + 0x00C */
  26. uint32_t r_des_active; /* MBAR_ETH + 0x010 */
  27. uint32_t x_des_active; /* MBAR_ETH + 0x014 */
  28. uint32_t res2[3]; /* MBAR_ETH + 0x018-20 */
  29. uint32_t ecntrl; /* MBAR_ETH + 0x024 */
  30. uint32_t res3[6]; /* MBAR_ETH + 0x028-03C */
  31. uint32_t mii_data; /* MBAR_ETH + 0x040 */
  32. uint32_t mii_speed; /* MBAR_ETH + 0x044 */
  33. uint32_t res4[7]; /* MBAR_ETH + 0x048-60 */
  34. uint32_t mib_control; /* MBAR_ETH + 0x064 */
  35. uint32_t res5[7]; /* MBAR_ETH + 0x068-80 */
  36. uint32_t r_cntrl; /* MBAR_ETH + 0x084 */
  37. uint32_t res6[15]; /* MBAR_ETH + 0x088-C0 */
  38. uint32_t x_cntrl; /* MBAR_ETH + 0x0C4 */
  39. uint32_t res7[7]; /* MBAR_ETH + 0x0C8-E0 */
  40. uint32_t paddr1; /* MBAR_ETH + 0x0E4 */
  41. uint32_t paddr2; /* MBAR_ETH + 0x0E8 */
  42. uint32_t op_pause; /* MBAR_ETH + 0x0EC */
  43. uint32_t res8[10]; /* MBAR_ETH + 0x0F0-114 */
  44. uint32_t iaddr1; /* MBAR_ETH + 0x118 */
  45. uint32_t iaddr2; /* MBAR_ETH + 0x11C */
  46. uint32_t gaddr1; /* MBAR_ETH + 0x120 */
  47. uint32_t gaddr2; /* MBAR_ETH + 0x124 */
  48. uint32_t res9[7]; /* MBAR_ETH + 0x128-140 */
  49. uint32_t x_wmrk; /* MBAR_ETH + 0x144 */
  50. uint32_t res10[1]; /* MBAR_ETH + 0x148 */
  51. uint32_t r_bound; /* MBAR_ETH + 0x14C */
  52. uint32_t r_fstart; /* MBAR_ETH + 0x150 */
  53. uint32_t res11[11]; /* MBAR_ETH + 0x154-17C */
  54. uint32_t erdsr; /* MBAR_ETH + 0x180 */
  55. uint32_t etdsr; /* MBAR_ETH + 0x184 */
  56. uint32_t emrbr; /* MBAR_ETH + 0x188 */
  57. uint32_t res12[29]; /* MBAR_ETH + 0x18C-1FC */
  58. /* MIB COUNTERS (Offset 200-2FF) */
  59. uint32_t rmon_t_drop; /* MBAR_ETH + 0x200 */
  60. uint32_t rmon_t_packets; /* MBAR_ETH + 0x204 */
  61. uint32_t rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */
  62. uint32_t rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */
  63. uint32_t rmon_t_crc_align; /* MBAR_ETH + 0x210 */
  64. uint32_t rmon_t_undersize; /* MBAR_ETH + 0x214 */
  65. uint32_t rmon_t_oversize; /* MBAR_ETH + 0x218 */
  66. uint32_t rmon_t_frag; /* MBAR_ETH + 0x21C */
  67. uint32_t rmon_t_jab; /* MBAR_ETH + 0x220 */
  68. uint32_t rmon_t_col; /* MBAR_ETH + 0x224 */
  69. uint32_t rmon_t_p64; /* MBAR_ETH + 0x228 */
  70. uint32_t rmon_t_p65to127; /* MBAR_ETH + 0x22C */
  71. uint32_t rmon_t_p128to255; /* MBAR_ETH + 0x230 */
  72. uint32_t rmon_t_p256to511; /* MBAR_ETH + 0x234 */
  73. uint32_t rmon_t_p512to1023; /* MBAR_ETH + 0x238 */
  74. uint32_t rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */
  75. uint32_t rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */
  76. uint32_t rmon_t_octets; /* MBAR_ETH + 0x244 */
  77. uint32_t ieee_t_drop; /* MBAR_ETH + 0x248 */
  78. uint32_t ieee_t_frame_ok; /* MBAR_ETH + 0x24C */
  79. uint32_t ieee_t_1col; /* MBAR_ETH + 0x250 */
  80. uint32_t ieee_t_mcol; /* MBAR_ETH + 0x254 */
  81. uint32_t ieee_t_def; /* MBAR_ETH + 0x258 */
  82. uint32_t ieee_t_lcol; /* MBAR_ETH + 0x25C */
  83. uint32_t ieee_t_excol; /* MBAR_ETH + 0x260 */
  84. uint32_t ieee_t_macerr; /* MBAR_ETH + 0x264 */
  85. uint32_t ieee_t_cserr; /* MBAR_ETH + 0x268 */
  86. uint32_t ieee_t_sqe; /* MBAR_ETH + 0x26C */
  87. uint32_t t_fdxfc; /* MBAR_ETH + 0x270 */
  88. uint32_t ieee_t_octets_ok; /* MBAR_ETH + 0x274 */
  89. uint32_t res13[2]; /* MBAR_ETH + 0x278-27C */
  90. uint32_t rmon_r_drop; /* MBAR_ETH + 0x280 */
  91. uint32_t rmon_r_packets; /* MBAR_ETH + 0x284 */
  92. uint32_t rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */
  93. uint32_t rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */
  94. uint32_t rmon_r_crc_align; /* MBAR_ETH + 0x290 */
  95. uint32_t rmon_r_undersize; /* MBAR_ETH + 0x294 */
  96. uint32_t rmon_r_oversize; /* MBAR_ETH + 0x298 */
  97. uint32_t rmon_r_frag; /* MBAR_ETH + 0x29C */
  98. uint32_t rmon_r_jab; /* MBAR_ETH + 0x2A0 */
  99. uint32_t rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */
  100. uint32_t rmon_r_p64; /* MBAR_ETH + 0x2A8 */
  101. uint32_t rmon_r_p65to127; /* MBAR_ETH + 0x2AC */
  102. uint32_t rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */
  103. uint32_t rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */
  104. uint32_t rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */
  105. uint32_t rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */
  106. uint32_t rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */
  107. uint32_t rmon_r_octets; /* MBAR_ETH + 0x2C4 */
  108. uint32_t ieee_r_drop; /* MBAR_ETH + 0x2C8 */
  109. uint32_t ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */
  110. uint32_t ieee_r_crc; /* MBAR_ETH + 0x2D0 */
  111. uint32_t ieee_r_align; /* MBAR_ETH + 0x2D4 */
  112. uint32_t r_macerr; /* MBAR_ETH + 0x2D8 */
  113. uint32_t r_fdxfc; /* MBAR_ETH + 0x2DC */
  114. uint32_t ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */
  115. uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */
  116. #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
  117. uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */
  118. uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */
  119. uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */
  120. uint16_t res16[3]; /* MBAR_ETH + 0x30a-30e */
  121. uint32_t res17[60]; /* MBAR_ETH + 0x300-3FF */
  122. #else
  123. uint32_t res15[64]; /* MBAR_ETH + 0x300-3FF */
  124. #endif
  125. };
  126. #define FEC_IEVENT_HBERR 0x80000000
  127. #define FEC_IEVENT_BABR 0x40000000
  128. #define FEC_IEVENT_BABT 0x20000000
  129. #define FEC_IEVENT_GRA 0x10000000
  130. #define FEC_IEVENT_TXF 0x08000000
  131. #define FEC_IEVENT_TXB 0x04000000
  132. #define FEC_IEVENT_RXF 0x02000000
  133. #define FEC_IEVENT_RXB 0x01000000
  134. #define FEC_IEVENT_MII 0x00800000
  135. #define FEC_IEVENT_EBERR 0x00400000
  136. #define FEC_IEVENT_LC 0x00200000
  137. #define FEC_IEVENT_RL 0x00100000
  138. #define FEC_IEVENT_UN 0x00080000
  139. #define FEC_IMASK_HBERR 0x80000000
  140. #define FEC_IMASK_BABR 0x40000000
  141. #define FEC_IMASKT_BABT 0x20000000
  142. #define FEC_IMASK_GRA 0x10000000
  143. #define FEC_IMASKT_TXF 0x08000000
  144. #define FEC_IMASK_TXB 0x04000000
  145. #define FEC_IMASKT_RXF 0x02000000
  146. #define FEC_IMASK_RXB 0x01000000
  147. #define FEC_IMASK_MII 0x00800000
  148. #define FEC_IMASK_EBERR 0x00400000
  149. #define FEC_IMASK_LC 0x00200000
  150. #define FEC_IMASKT_RL 0x00100000
  151. #define FEC_IMASK_UN 0x00080000
  152. #define FEC_RCNTRL_MAX_FL_SHIFT 16
  153. #define FEC_RCNTRL_LOOP 0x00000001
  154. #define FEC_RCNTRL_DRT 0x00000002
  155. #define FEC_RCNTRL_MII_MODE 0x00000004
  156. #define FEC_RCNTRL_PROM 0x00000008
  157. #define FEC_RCNTRL_BC_REJ 0x00000010
  158. #define FEC_RCNTRL_FCE 0x00000020
  159. #define FEC_RCNTRL_RGMII 0x00000040
  160. #define FEC_RCNTRL_RMII 0x00000100
  161. #define FEC_RCNTRL_RMII_10T 0x00000200
  162. #define FEC_TCNTRL_GTS 0x00000001
  163. #define FEC_TCNTRL_HBC 0x00000002
  164. #define FEC_TCNTRL_FDEN 0x00000004
  165. #define FEC_TCNTRL_TFC_PAUSE 0x00000008
  166. #define FEC_TCNTRL_RFC_PAUSE 0x00000010
  167. #define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */
  168. #define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */
  169. #define FEC_ECNTRL_SPEED 0x00000020
  170. #define FEC_ECNTRL_DBSWAP 0x00000100
  171. #define FEC_ECNTRL_TXC_DLY 0x00010000 /* TXC delayed */
  172. #define FEC_ECNTRL_RXC_DLY 0x00020000 /* RXC delayed */
  173. #define FEC_X_WMRK_STRFWD 0x00000100
  174. #define FEC_X_DES_ACTIVE_TDAR 0x01000000
  175. #define FEC_R_DES_ACTIVE_RDAR 0x01000000
  176. #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
  177. /* defines for MIIGSK */
  178. /* RMII frequency control: 0=50MHz, 1=5MHz */
  179. #define MIIGSK_CFGR_FRCONT (1 << 6)
  180. /* loopback mode */
  181. #define MIIGSK_CFGR_LBMODE (1 << 4)
  182. /* echo mode */
  183. #define MIIGSK_CFGR_EMODE (1 << 3)
  184. /* MII gasket mode field */
  185. #define MIIGSK_CFGR_IF_MODE_MASK (3 << 0)
  186. /* MMI/7-Wire mode */
  187. #define MIIGSK_CFGR_IF_MODE_MII (0 << 0)
  188. /* RMII mode */
  189. #define MIIGSK_CFGR_IF_MODE_RMII (1 << 0)
  190. /* reflects MIIGSK Enable bit (RO) */
  191. #define MIIGSK_ENR_READY (1 << 2)
  192. /* enable MIGSK (set by default) */
  193. #define MIIGSK_ENR_EN (1 << 1)
  194. #endif
  195. /**
  196. * @brief Receive & Transmit Buffer Descriptor definitions
  197. *
  198. * Note: The first BD must be aligned (see DB_ALIGNMENT)
  199. */
  200. struct fec_bd {
  201. uint16_t data_length; /* payload's length in bytes */
  202. uint16_t status; /* BD's staus (see datasheet) */
  203. uint32_t data_pointer; /* payload's buffer address */
  204. };
  205. /* Supported phy types on this platform */
  206. enum xceiver_type {
  207. SEVENWIRE, /* 7-wire */
  208. MII10, /* MII 10Mbps */
  209. MII100, /* MII 100Mbps */
  210. RMII, /* RMII */
  211. RGMII, /* RGMII */
  212. };
  213. /* @brief i.MX27-FEC private structure */
  214. struct fec_priv {
  215. struct ethernet_regs *eth; /* pointer to register'S base */
  216. enum xceiver_type xcv_type; /* transceiver type */
  217. struct fec_bd *rbd_base; /* RBD ring */
  218. int rbd_index; /* next receive BD to read */
  219. struct fec_bd *tbd_base; /* TBD ring */
  220. int tbd_index; /* next transmit BD to write */
  221. struct bd_info *bd;
  222. uint8_t *tdb_ptr;
  223. int dev_id;
  224. struct mii_dev *bus;
  225. #ifdef CONFIG_PHYLIB
  226. struct phy_device *phydev;
  227. ofnode phy_of_node;
  228. #else
  229. int phy_id;
  230. int (*mii_postcall)(int);
  231. #endif
  232. #ifdef CONFIG_DM_REGULATOR
  233. struct udevice *phy_supply;
  234. #endif
  235. #if CONFIG_IS_ENABLED(DM_GPIO)
  236. struct gpio_desc phy_reset_gpio;
  237. uint32_t reset_delay;
  238. uint32_t reset_post_delay;
  239. #endif
  240. #ifdef CONFIG_DM_ETH
  241. u32 interface;
  242. #endif
  243. struct clk ipg_clk;
  244. struct clk ahb_clk;
  245. struct clk clk_enet_out;
  246. struct clk clk_ref;
  247. struct clk clk_ptp;
  248. u32 clk_rate;
  249. char promisc;
  250. };
  251. /**
  252. * @brief Numbers of buffer descriptors for receiving
  253. *
  254. * The number defines the stocked memory buffers for the receiving task.
  255. * Larger values makes no sense in this limited environment.
  256. */
  257. #define FEC_RBD_NUM 64
  258. /**
  259. * @brief Define the ethernet packet size limit in memory
  260. *
  261. * Note: Do not shrink this number. This will force the FEC to spread larger
  262. * frames in more than one BD. This is nothing to worry about, but the current
  263. * driver can't handle it.
  264. */
  265. #define FEC_MAX_PKT_SIZE 1536
  266. /* Receive BD status bits */
  267. #define FEC_RBD_EMPTY 0x8000 /* Receive BD status: Buffer is empty */
  268. #define FEC_RBD_WRAP 0x2000 /* Receive BD status: Last BD in ring */
  269. /* Receive BD status: Buffer is last in frame (useless here!) */
  270. #define FEC_RBD_LAST 0x0800
  271. #define FEC_RBD_MISS 0x0100 /* Receive BD status: Miss bit for prom mode */
  272. /* Receive BD status: The received frame is broadcast frame */
  273. #define FEC_RBD_BC 0x0080
  274. /* Receive BD status: The received frame is multicast frame */
  275. #define FEC_RBD_MC 0x0040
  276. #define FEC_RBD_LG 0x0020 /* Receive BD status: Frame length violation */
  277. #define FEC_RBD_NO 0x0010 /* Receive BD status: Nonoctet align frame */
  278. #define FEC_RBD_CR 0x0004 /* Receive BD status: CRC error */
  279. #define FEC_RBD_OV 0x0002 /* Receive BD status: Receive FIFO overrun */
  280. #define FEC_RBD_TR 0x0001 /* Receive BD status: Frame is truncated */
  281. #define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
  282. FEC_RBD_OV | FEC_RBD_TR)
  283. /* Transmit BD status bits */
  284. #define FEC_TBD_READY 0x8000 /* Tansmit BD status: Buffer is ready */
  285. #define FEC_TBD_WRAP 0x2000 /* Tansmit BD status: Mark as last BD in ring */
  286. #define FEC_TBD_LAST 0x0800 /* Tansmit BD status: Buffer is last in frame */
  287. #define FEC_TBD_TC 0x0400 /* Tansmit BD status: Transmit the CRC */
  288. #define FEC_TBD_ABC 0x0200 /* Tansmit BD status: Append bad CRC */
  289. /* MII-related definitios */
  290. #define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
  291. #define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
  292. #define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
  293. #define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
  294. #define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
  295. #define FEC_MII_DATA_TA 0x00020000 /* Turnaround */
  296. #define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
  297. #define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
  298. #define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
  299. #endif /* __FEC_MXC_H */