fec_mxc.c 40 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
  4. * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
  5. * (C) Copyright 2008 Armadeus Systems nc
  6. * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  7. * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <dm.h>
  12. #include <env.h>
  13. #include <log.h>
  14. #include <malloc.h>
  15. #include <memalign.h>
  16. #include <miiphy.h>
  17. #include <net.h>
  18. #include <netdev.h>
  19. #include <asm/cache.h>
  20. #include <asm/global_data.h>
  21. #include <linux/delay.h>
  22. #include <power/regulator.h>
  23. #include <asm/io.h>
  24. #include <linux/errno.h>
  25. #include <linux/compiler.h>
  26. #include <asm/arch/clock.h>
  27. #include <asm/arch/imx-regs.h>
  28. #include <asm/mach-imx/sys_proto.h>
  29. #include <asm-generic/gpio.h>
  30. #include "fec_mxc.h"
  31. #include <eth_phy.h>
  32. DECLARE_GLOBAL_DATA_PTR;
  33. /*
  34. * Timeout the transfer after 5 mS. This is usually a bit more, since
  35. * the code in the tightloops this timeout is used in adds some overhead.
  36. */
  37. #define FEC_XFER_TIMEOUT 5000
  38. /*
  39. * The standard 32-byte DMA alignment does not work on mx6solox, which requires
  40. * 64-byte alignment in the DMA RX FEC buffer.
  41. * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
  42. * satisfies the alignment on other SoCs (32-bytes)
  43. */
  44. #define FEC_DMA_RX_MINALIGN 64
  45. #ifndef CONFIG_MII
  46. #error "CONFIG_MII has to be defined!"
  47. #endif
  48. #ifndef CONFIG_FEC_XCV_TYPE
  49. #define CONFIG_FEC_XCV_TYPE MII100
  50. #endif
  51. /*
  52. * The i.MX28 operates with packets in big endian. We need to swap them before
  53. * sending and after receiving.
  54. */
  55. #ifdef CONFIG_MX28
  56. #define CONFIG_FEC_MXC_SWAP_PACKET
  57. #endif
  58. #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
  59. /* Check various alignment issues at compile time */
  60. #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
  61. #error "ARCH_DMA_MINALIGN must be multiple of 16!"
  62. #endif
  63. #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
  64. (PKTALIGN % ARCH_DMA_MINALIGN != 0))
  65. #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
  66. #endif
  67. #undef DEBUG
  68. #ifdef CONFIG_FEC_MXC_SWAP_PACKET
  69. static void swap_packet(uint32_t *packet, int length)
  70. {
  71. int i;
  72. for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
  73. packet[i] = __swab32(packet[i]);
  74. }
  75. #endif
  76. /* MII-interface related functions */
  77. static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
  78. uint8_t regaddr)
  79. {
  80. uint32_t reg; /* convenient holder for the PHY register */
  81. uint32_t phy; /* convenient holder for the PHY */
  82. uint32_t start;
  83. int val;
  84. /*
  85. * reading from any PHY's register is done by properly
  86. * programming the FEC's MII data register.
  87. */
  88. writel(FEC_IEVENT_MII, &eth->ievent);
  89. reg = regaddr << FEC_MII_DATA_RA_SHIFT;
  90. phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
  91. writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
  92. phy | reg, &eth->mii_data);
  93. /* wait for the related interrupt */
  94. start = get_timer(0);
  95. while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
  96. if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
  97. printf("Read MDIO failed...\n");
  98. return -1;
  99. }
  100. }
  101. /* clear mii interrupt bit */
  102. writel(FEC_IEVENT_MII, &eth->ievent);
  103. /* it's now safe to read the PHY's register */
  104. val = (unsigned short)readl(&eth->mii_data);
  105. debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
  106. regaddr, val);
  107. return val;
  108. }
  109. #ifndef imx_get_fecclk
  110. u32 __weak imx_get_fecclk(void)
  111. {
  112. return 0;
  113. }
  114. #endif
  115. static int fec_get_clk_rate(void *udev, int idx)
  116. {
  117. struct fec_priv *fec;
  118. struct udevice *dev;
  119. int ret;
  120. if (IS_ENABLED(CONFIG_IMX8) ||
  121. CONFIG_IS_ENABLED(CLK_CCF)) {
  122. dev = udev;
  123. if (!dev) {
  124. ret = uclass_get_device_by_seq(UCLASS_ETH, idx, &dev);
  125. if (ret < 0) {
  126. debug("Can't get FEC udev: %d\n", ret);
  127. return ret;
  128. }
  129. }
  130. fec = dev_get_priv(dev);
  131. if (fec)
  132. return fec->clk_rate;
  133. return -EINVAL;
  134. } else {
  135. return imx_get_fecclk();
  136. }
  137. }
  138. static void fec_mii_setspeed(struct ethernet_regs *eth)
  139. {
  140. /*
  141. * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
  142. * and do not drop the Preamble.
  143. *
  144. * The i.MX28 and i.MX6 types have another field in the MSCR (aka
  145. * MII_SPEED) register that defines the MDIO output hold time. Earlier
  146. * versions are RAZ there, so just ignore the difference and write the
  147. * register always.
  148. * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
  149. * HOLDTIME + 1 is the number of clk cycles the fec is holding the
  150. * output.
  151. * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
  152. * Given that ceil(clkrate / 5000000) <= 64, the calculation for
  153. * holdtime cannot result in a value greater than 3.
  154. */
  155. u32 pclk;
  156. u32 speed;
  157. u32 hold;
  158. int ret;
  159. ret = fec_get_clk_rate(NULL, 0);
  160. if (ret < 0) {
  161. printf("Can't find FEC0 clk rate: %d\n", ret);
  162. return;
  163. }
  164. pclk = ret;
  165. speed = DIV_ROUND_UP(pclk, 5000000);
  166. hold = DIV_ROUND_UP(pclk, 100000000) - 1;
  167. #ifdef FEC_QUIRK_ENET_MAC
  168. speed--;
  169. #endif
  170. writel(speed << 1 | hold << 8, &eth->mii_speed);
  171. debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));
  172. }
  173. static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
  174. uint8_t regaddr, uint16_t data)
  175. {
  176. uint32_t reg; /* convenient holder for the PHY register */
  177. uint32_t phy; /* convenient holder for the PHY */
  178. uint32_t start;
  179. reg = regaddr << FEC_MII_DATA_RA_SHIFT;
  180. phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
  181. writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
  182. FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);
  183. /* wait for the MII interrupt */
  184. start = get_timer(0);
  185. while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
  186. if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
  187. printf("Write MDIO failed...\n");
  188. return -1;
  189. }
  190. }
  191. /* clear MII interrupt bit */
  192. writel(FEC_IEVENT_MII, &eth->ievent);
  193. debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
  194. regaddr, data);
  195. return 0;
  196. }
  197. static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
  198. int regaddr)
  199. {
  200. return fec_mdio_read(bus->priv, phyaddr, regaddr);
  201. }
  202. static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
  203. int regaddr, u16 data)
  204. {
  205. return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
  206. }
  207. #ifndef CONFIG_PHYLIB
  208. static int miiphy_restart_aneg(struct eth_device *dev)
  209. {
  210. int ret = 0;
  211. #if !defined(CONFIG_FEC_MXC_NO_ANEG)
  212. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  213. struct ethernet_regs *eth = fec->bus->priv;
  214. /*
  215. * Wake up from sleep if necessary
  216. * Reset PHY, then delay 300ns
  217. */
  218. #ifdef CONFIG_MX27
  219. fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
  220. #endif
  221. fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
  222. udelay(1000);
  223. /* Set the auto-negotiation advertisement register bits */
  224. fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
  225. LPA_100FULL | LPA_100HALF | LPA_10FULL |
  226. LPA_10HALF | PHY_ANLPAR_PSB_802_3);
  227. fec_mdio_write(eth, fec->phy_id, MII_BMCR,
  228. BMCR_ANENABLE | BMCR_ANRESTART);
  229. if (fec->mii_postcall)
  230. ret = fec->mii_postcall(fec->phy_id);
  231. #endif
  232. return ret;
  233. }
  234. #ifndef CONFIG_FEC_FIXED_SPEED
  235. static int miiphy_wait_aneg(struct eth_device *dev)
  236. {
  237. uint32_t start;
  238. int status;
  239. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  240. struct ethernet_regs *eth = fec->bus->priv;
  241. /* Wait for AN completion */
  242. start = get_timer(0);
  243. do {
  244. if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
  245. printf("%s: Autonegotiation timeout\n", dev->name);
  246. return -1;
  247. }
  248. status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
  249. if (status < 0) {
  250. printf("%s: Autonegotiation failed. status: %d\n",
  251. dev->name, status);
  252. return -1;
  253. }
  254. } while (!(status & BMSR_LSTATUS));
  255. return 0;
  256. }
  257. #endif /* CONFIG_FEC_FIXED_SPEED */
  258. #endif
  259. static int fec_rx_task_enable(struct fec_priv *fec)
  260. {
  261. writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
  262. return 0;
  263. }
  264. static int fec_rx_task_disable(struct fec_priv *fec)
  265. {
  266. return 0;
  267. }
  268. static int fec_tx_task_enable(struct fec_priv *fec)
  269. {
  270. writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
  271. return 0;
  272. }
  273. static int fec_tx_task_disable(struct fec_priv *fec)
  274. {
  275. return 0;
  276. }
  277. /**
  278. * Initialize receive task's buffer descriptors
  279. * @param[in] fec all we know about the device yet
  280. * @param[in] count receive buffer count to be allocated
  281. * @param[in] dsize desired size of each receive buffer
  282. * @return 0 on success
  283. *
  284. * Init all RX descriptors to default values.
  285. */
  286. static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
  287. {
  288. uint32_t size;
  289. ulong data;
  290. int i;
  291. /*
  292. * Reload the RX descriptors with default values and wipe
  293. * the RX buffers.
  294. */
  295. size = roundup(dsize, ARCH_DMA_MINALIGN);
  296. for (i = 0; i < count; i++) {
  297. data = fec->rbd_base[i].data_pointer;
  298. memset((void *)data, 0, dsize);
  299. flush_dcache_range(data, data + size);
  300. fec->rbd_base[i].status = FEC_RBD_EMPTY;
  301. fec->rbd_base[i].data_length = 0;
  302. }
  303. /* Mark the last RBD to close the ring. */
  304. fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
  305. fec->rbd_index = 0;
  306. flush_dcache_range((ulong)fec->rbd_base,
  307. (ulong)fec->rbd_base + size);
  308. }
  309. /**
  310. * Initialize transmit task's buffer descriptors
  311. * @param[in] fec all we know about the device yet
  312. *
  313. * Transmit buffers are created externally. We only have to init the BDs here.\n
  314. * Note: There is a race condition in the hardware. When only one BD is in
  315. * use it must be marked with the WRAP bit to use it for every transmitt.
  316. * This bit in combination with the READY bit results into double transmit
  317. * of each data buffer. It seems the state machine checks READY earlier then
  318. * resetting it after the first transfer.
  319. * Using two BDs solves this issue.
  320. */
  321. static void fec_tbd_init(struct fec_priv *fec)
  322. {
  323. ulong addr = (ulong)fec->tbd_base;
  324. unsigned size = roundup(2 * sizeof(struct fec_bd),
  325. ARCH_DMA_MINALIGN);
  326. memset(fec->tbd_base, 0, size);
  327. fec->tbd_base[0].status = 0;
  328. fec->tbd_base[1].status = FEC_TBD_WRAP;
  329. fec->tbd_index = 0;
  330. flush_dcache_range(addr, addr + size);
  331. }
  332. /**
  333. * Mark the given read buffer descriptor as free
  334. * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
  335. * @param[in] prbd buffer descriptor to mark free again
  336. */
  337. static void fec_rbd_clean(int last, struct fec_bd *prbd)
  338. {
  339. unsigned short flags = FEC_RBD_EMPTY;
  340. if (last)
  341. flags |= FEC_RBD_WRAP;
  342. writew(flags, &prbd->status);
  343. writew(0, &prbd->data_length);
  344. }
  345. static int fec_get_hwaddr(int dev_id, unsigned char *mac)
  346. {
  347. imx_get_mac_from_fuse(dev_id, mac);
  348. return !is_valid_ethaddr(mac);
  349. }
  350. #ifdef CONFIG_DM_ETH
  351. static int fecmxc_set_hwaddr(struct udevice *dev)
  352. #else
  353. static int fec_set_hwaddr(struct eth_device *dev)
  354. #endif
  355. {
  356. #ifdef CONFIG_DM_ETH
  357. struct fec_priv *fec = dev_get_priv(dev);
  358. struct eth_pdata *pdata = dev_get_plat(dev);
  359. uchar *mac = pdata->enetaddr;
  360. #else
  361. uchar *mac = dev->enetaddr;
  362. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  363. #endif
  364. writel(0, &fec->eth->iaddr1);
  365. writel(0, &fec->eth->iaddr2);
  366. writel(0, &fec->eth->gaddr1);
  367. writel(0, &fec->eth->gaddr2);
  368. /* Set physical address */
  369. writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
  370. &fec->eth->paddr1);
  371. writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
  372. return 0;
  373. }
  374. /* Do initial configuration of the FEC registers */
  375. static void fec_reg_setup(struct fec_priv *fec)
  376. {
  377. uint32_t rcntrl;
  378. /* Set interrupt mask register */
  379. writel(0x00000000, &fec->eth->imask);
  380. /* Clear FEC-Lite interrupt event register(IEVENT) */
  381. writel(0xffffffff, &fec->eth->ievent);
  382. /* Set FEC-Lite receive control register(R_CNTRL): */
  383. /* Start with frame length = 1518, common for all modes. */
  384. rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
  385. if (fec->xcv_type != SEVENWIRE) /* xMII modes */
  386. rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
  387. if (fec->xcv_type == RGMII)
  388. rcntrl |= FEC_RCNTRL_RGMII;
  389. else if (fec->xcv_type == RMII)
  390. rcntrl |= FEC_RCNTRL_RMII;
  391. if (fec->promisc)
  392. rcntrl |= 0x8;
  393. writel(rcntrl, &fec->eth->r_cntrl);
  394. }
  395. /**
  396. * Start the FEC engine
  397. * @param[in] dev Our device to handle
  398. */
  399. #ifdef CONFIG_DM_ETH
  400. static int fec_open(struct udevice *dev)
  401. #else
  402. static int fec_open(struct eth_device *edev)
  403. #endif
  404. {
  405. #ifdef CONFIG_DM_ETH
  406. struct fec_priv *fec = dev_get_priv(dev);
  407. #else
  408. struct fec_priv *fec = (struct fec_priv *)edev->priv;
  409. #endif
  410. int speed;
  411. ulong addr, size;
  412. int i;
  413. debug("fec_open: fec_open(dev)\n");
  414. /* full-duplex, heartbeat disabled */
  415. writel(1 << 2, &fec->eth->x_cntrl);
  416. fec->rbd_index = 0;
  417. /* Invalidate all descriptors */
  418. for (i = 0; i < FEC_RBD_NUM - 1; i++)
  419. fec_rbd_clean(0, &fec->rbd_base[i]);
  420. fec_rbd_clean(1, &fec->rbd_base[i]);
  421. /* Flush the descriptors into RAM */
  422. size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
  423. ARCH_DMA_MINALIGN);
  424. addr = (ulong)fec->rbd_base;
  425. flush_dcache_range(addr, addr + size);
  426. #ifdef FEC_QUIRK_ENET_MAC
  427. /* Enable ENET HW endian SWAP */
  428. writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
  429. &fec->eth->ecntrl);
  430. /* Enable ENET store and forward mode */
  431. writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
  432. &fec->eth->x_wmrk);
  433. #endif
  434. /* Enable FEC-Lite controller */
  435. writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
  436. &fec->eth->ecntrl);
  437. #ifdef FEC_ENET_ENABLE_TXC_DELAY
  438. writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_TXC_DLY,
  439. &fec->eth->ecntrl);
  440. #endif
  441. #ifdef FEC_ENET_ENABLE_RXC_DELAY
  442. writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RXC_DLY,
  443. &fec->eth->ecntrl);
  444. #endif
  445. #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
  446. udelay(100);
  447. /* setup the MII gasket for RMII mode */
  448. /* disable the gasket */
  449. writew(0, &fec->eth->miigsk_enr);
  450. /* wait for the gasket to be disabled */
  451. while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
  452. udelay(2);
  453. /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
  454. writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
  455. /* re-enable the gasket */
  456. writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
  457. /* wait until MII gasket is ready */
  458. int max_loops = 10;
  459. while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
  460. if (--max_loops <= 0) {
  461. printf("WAIT for MII Gasket ready timed out\n");
  462. break;
  463. }
  464. }
  465. #endif
  466. #ifdef CONFIG_PHYLIB
  467. {
  468. /* Start up the PHY */
  469. int ret = phy_startup(fec->phydev);
  470. if (ret) {
  471. printf("Could not initialize PHY %s\n",
  472. fec->phydev->dev->name);
  473. return ret;
  474. }
  475. speed = fec->phydev->speed;
  476. }
  477. #elif CONFIG_FEC_FIXED_SPEED
  478. speed = CONFIG_FEC_FIXED_SPEED;
  479. #else
  480. miiphy_wait_aneg(edev);
  481. speed = miiphy_speed(edev->name, fec->phy_id);
  482. miiphy_duplex(edev->name, fec->phy_id);
  483. #endif
  484. #ifdef FEC_QUIRK_ENET_MAC
  485. {
  486. u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
  487. u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
  488. if (speed == _1000BASET)
  489. ecr |= FEC_ECNTRL_SPEED;
  490. else if (speed != _100BASET)
  491. rcr |= FEC_RCNTRL_RMII_10T;
  492. writel(ecr, &fec->eth->ecntrl);
  493. writel(rcr, &fec->eth->r_cntrl);
  494. }
  495. #endif
  496. debug("%s:Speed=%i\n", __func__, speed);
  497. /* Enable SmartDMA receive task */
  498. fec_rx_task_enable(fec);
  499. udelay(100000);
  500. return 0;
  501. }
  502. #ifdef CONFIG_DM_ETH
  503. static int fecmxc_init(struct udevice *dev)
  504. #else
  505. static int fec_init(struct eth_device *dev, struct bd_info *bd)
  506. #endif
  507. {
  508. #ifdef CONFIG_DM_ETH
  509. struct fec_priv *fec = dev_get_priv(dev);
  510. #else
  511. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  512. #endif
  513. u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
  514. u8 *i;
  515. ulong addr;
  516. /* Initialize MAC address */
  517. #ifdef CONFIG_DM_ETH
  518. fecmxc_set_hwaddr(dev);
  519. #else
  520. fec_set_hwaddr(dev);
  521. #endif
  522. /* Setup transmit descriptors, there are two in total. */
  523. fec_tbd_init(fec);
  524. /* Setup receive descriptors. */
  525. fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
  526. fec_reg_setup(fec);
  527. if (fec->xcv_type != SEVENWIRE)
  528. fec_mii_setspeed(fec->bus->priv);
  529. /* Set Opcode/Pause Duration Register */
  530. writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
  531. writel(0x2, &fec->eth->x_wmrk);
  532. /* Set multicast address filter */
  533. writel(0x00000000, &fec->eth->gaddr1);
  534. writel(0x00000000, &fec->eth->gaddr2);
  535. /* Do not access reserved register */
  536. if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp()) {
  537. /* clear MIB RAM */
  538. for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
  539. writel(0, i);
  540. /* FIFO receive start register */
  541. writel(0x520, &fec->eth->r_fstart);
  542. }
  543. /* size and address of each buffer */
  544. writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
  545. addr = (ulong)fec->tbd_base;
  546. writel((uint32_t)addr, &fec->eth->etdsr);
  547. addr = (ulong)fec->rbd_base;
  548. writel((uint32_t)addr, &fec->eth->erdsr);
  549. #ifndef CONFIG_PHYLIB
  550. if (fec->xcv_type != SEVENWIRE)
  551. miiphy_restart_aneg(dev);
  552. #endif
  553. fec_open(dev);
  554. return 0;
  555. }
  556. /**
  557. * Halt the FEC engine
  558. * @param[in] dev Our device to handle
  559. */
  560. #ifdef CONFIG_DM_ETH
  561. static void fecmxc_halt(struct udevice *dev)
  562. #else
  563. static void fec_halt(struct eth_device *dev)
  564. #endif
  565. {
  566. #ifdef CONFIG_DM_ETH
  567. struct fec_priv *fec = dev_get_priv(dev);
  568. #else
  569. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  570. #endif
  571. int counter = 0xffff;
  572. /* issue graceful stop command to the FEC transmitter if necessary */
  573. writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
  574. &fec->eth->x_cntrl);
  575. debug("eth_halt: wait for stop regs\n");
  576. /* wait for graceful stop to register */
  577. while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
  578. udelay(1);
  579. /* Disable SmartDMA tasks */
  580. fec_tx_task_disable(fec);
  581. fec_rx_task_disable(fec);
  582. /*
  583. * Disable the Ethernet Controller
  584. * Note: this will also reset the BD index counter!
  585. */
  586. writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
  587. &fec->eth->ecntrl);
  588. fec->rbd_index = 0;
  589. fec->tbd_index = 0;
  590. debug("eth_halt: done\n");
  591. }
  592. /**
  593. * Transmit one frame
  594. * @param[in] dev Our ethernet device to handle
  595. * @param[in] packet Pointer to the data to be transmitted
  596. * @param[in] length Data count in bytes
  597. * @return 0 on success
  598. */
  599. #ifdef CONFIG_DM_ETH
  600. static int fecmxc_send(struct udevice *dev, void *packet, int length)
  601. #else
  602. static int fec_send(struct eth_device *dev, void *packet, int length)
  603. #endif
  604. {
  605. unsigned int status;
  606. u32 size;
  607. ulong addr, end;
  608. int timeout = FEC_XFER_TIMEOUT;
  609. int ret = 0;
  610. /*
  611. * This routine transmits one frame. This routine only accepts
  612. * 6-byte Ethernet addresses.
  613. */
  614. #ifdef CONFIG_DM_ETH
  615. struct fec_priv *fec = dev_get_priv(dev);
  616. #else
  617. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  618. #endif
  619. /*
  620. * Check for valid length of data.
  621. */
  622. if ((length > 1500) || (length <= 0)) {
  623. printf("Payload (%d) too large\n", length);
  624. return -1;
  625. }
  626. /*
  627. * Setup the transmit buffer. We are always using the first buffer for
  628. * transmission, the second will be empty and only used to stop the DMA
  629. * engine. We also flush the packet to RAM here to avoid cache trouble.
  630. */
  631. #ifdef CONFIG_FEC_MXC_SWAP_PACKET
  632. swap_packet((uint32_t *)packet, length);
  633. #endif
  634. addr = (ulong)packet;
  635. end = roundup(addr + length, ARCH_DMA_MINALIGN);
  636. addr &= ~(ARCH_DMA_MINALIGN - 1);
  637. flush_dcache_range(addr, end);
  638. writew(length, &fec->tbd_base[fec->tbd_index].data_length);
  639. writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
  640. /*
  641. * update BD's status now
  642. * This block:
  643. * - is always the last in a chain (means no chain)
  644. * - should transmitt the CRC
  645. * - might be the last BD in the list, so the address counter should
  646. * wrap (-> keep the WRAP flag)
  647. */
  648. status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
  649. status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
  650. writew(status, &fec->tbd_base[fec->tbd_index].status);
  651. /*
  652. * Flush data cache. This code flushes both TX descriptors to RAM.
  653. * After this code, the descriptors will be safely in RAM and we
  654. * can start DMA.
  655. */
  656. size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
  657. addr = (ulong)fec->tbd_base;
  658. flush_dcache_range(addr, addr + size);
  659. /*
  660. * Below we read the DMA descriptor's last four bytes back from the
  661. * DRAM. This is important in order to make sure that all WRITE
  662. * operations on the bus that were triggered by previous cache FLUSH
  663. * have completed.
  664. *
  665. * Otherwise, on MX28, it is possible to observe a corruption of the
  666. * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
  667. * for the bus structure of MX28. The scenario is as follows:
  668. *
  669. * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
  670. * to DRAM due to flush_dcache_range()
  671. * 2) ARM core writes the FEC registers via AHB_ARB2
  672. * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
  673. *
  674. * Note that 2) does sometimes finish before 1) due to reordering of
  675. * WRITE accesses on the AHB bus, therefore triggering 3) before the
  676. * DMA descriptor is fully written into DRAM. This results in occasional
  677. * corruption of the DMA descriptor.
  678. */
  679. readl(addr + size - 4);
  680. /* Enable SmartDMA transmit task */
  681. fec_tx_task_enable(fec);
  682. /*
  683. * Wait until frame is sent. On each turn of the wait cycle, we must
  684. * invalidate data cache to see what's really in RAM. Also, we need
  685. * barrier here.
  686. */
  687. while (--timeout) {
  688. if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
  689. break;
  690. }
  691. if (!timeout) {
  692. ret = -EINVAL;
  693. goto out;
  694. }
  695. /*
  696. * The TDAR bit is cleared when the descriptors are all out from TX
  697. * but on mx6solox we noticed that the READY bit is still not cleared
  698. * right after TDAR.
  699. * These are two distinct signals, and in IC simulation, we found that
  700. * TDAR always gets cleared prior than the READY bit of last BD becomes
  701. * cleared.
  702. * In mx6solox, we use a later version of FEC IP. It looks like that
  703. * this intrinsic behaviour of TDAR bit has changed in this newer FEC
  704. * version.
  705. *
  706. * Fix this by polling the READY bit of BD after the TDAR polling,
  707. * which covers the mx6solox case and does not harm the other SoCs.
  708. */
  709. timeout = FEC_XFER_TIMEOUT;
  710. while (--timeout) {
  711. invalidate_dcache_range(addr, addr + size);
  712. if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
  713. FEC_TBD_READY))
  714. break;
  715. }
  716. if (!timeout)
  717. ret = -EINVAL;
  718. out:
  719. debug("fec_send: status 0x%x index %d ret %i\n",
  720. readw(&fec->tbd_base[fec->tbd_index].status),
  721. fec->tbd_index, ret);
  722. /* for next transmission use the other buffer */
  723. if (fec->tbd_index)
  724. fec->tbd_index = 0;
  725. else
  726. fec->tbd_index = 1;
  727. return ret;
  728. }
  729. /**
  730. * Pull one frame from the card
  731. * @param[in] dev Our ethernet device to handle
  732. * @return Length of packet read
  733. */
  734. #ifdef CONFIG_DM_ETH
  735. static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
  736. #else
  737. static int fec_recv(struct eth_device *dev)
  738. #endif
  739. {
  740. #ifdef CONFIG_DM_ETH
  741. struct fec_priv *fec = dev_get_priv(dev);
  742. #else
  743. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  744. #endif
  745. struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
  746. unsigned long ievent;
  747. int frame_length, len = 0;
  748. uint16_t bd_status;
  749. ulong addr, size, end;
  750. int i;
  751. #ifdef CONFIG_DM_ETH
  752. *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
  753. if (*packetp == 0) {
  754. printf("%s: error allocating packetp\n", __func__);
  755. return -ENOMEM;
  756. }
  757. #else
  758. ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
  759. #endif
  760. /* Check if any critical events have happened */
  761. ievent = readl(&fec->eth->ievent);
  762. writel(ievent, &fec->eth->ievent);
  763. debug("fec_recv: ievent 0x%lx\n", ievent);
  764. if (ievent & FEC_IEVENT_BABR) {
  765. #ifdef CONFIG_DM_ETH
  766. fecmxc_halt(dev);
  767. fecmxc_init(dev);
  768. #else
  769. fec_halt(dev);
  770. fec_init(dev, fec->bd);
  771. #endif
  772. printf("some error: 0x%08lx\n", ievent);
  773. return 0;
  774. }
  775. if (ievent & FEC_IEVENT_HBERR) {
  776. /* Heartbeat error */
  777. writel(0x00000001 | readl(&fec->eth->x_cntrl),
  778. &fec->eth->x_cntrl);
  779. }
  780. if (ievent & FEC_IEVENT_GRA) {
  781. /* Graceful stop complete */
  782. if (readl(&fec->eth->x_cntrl) & 0x00000001) {
  783. #ifdef CONFIG_DM_ETH
  784. fecmxc_halt(dev);
  785. #else
  786. fec_halt(dev);
  787. #endif
  788. writel(~0x00000001 & readl(&fec->eth->x_cntrl),
  789. &fec->eth->x_cntrl);
  790. #ifdef CONFIG_DM_ETH
  791. fecmxc_init(dev);
  792. #else
  793. fec_init(dev, fec->bd);
  794. #endif
  795. }
  796. }
  797. /*
  798. * Read the buffer status. Before the status can be read, the data cache
  799. * must be invalidated, because the data in RAM might have been changed
  800. * by DMA. The descriptors are properly aligned to cachelines so there's
  801. * no need to worry they'd overlap.
  802. *
  803. * WARNING: By invalidating the descriptor here, we also invalidate
  804. * the descriptors surrounding this one. Therefore we can NOT change the
  805. * contents of this descriptor nor the surrounding ones. The problem is
  806. * that in order to mark the descriptor as processed, we need to change
  807. * the descriptor. The solution is to mark the whole cache line when all
  808. * descriptors in the cache line are processed.
  809. */
  810. addr = (ulong)rbd;
  811. addr &= ~(ARCH_DMA_MINALIGN - 1);
  812. size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
  813. invalidate_dcache_range(addr, addr + size);
  814. bd_status = readw(&rbd->status);
  815. debug("fec_recv: status 0x%x\n", bd_status);
  816. if (!(bd_status & FEC_RBD_EMPTY)) {
  817. if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
  818. ((readw(&rbd->data_length) - 4) > 14)) {
  819. /* Get buffer address and size */
  820. addr = readl(&rbd->data_pointer);
  821. frame_length = readw(&rbd->data_length) - 4;
  822. /* Invalidate data cache over the buffer */
  823. end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
  824. addr &= ~(ARCH_DMA_MINALIGN - 1);
  825. invalidate_dcache_range(addr, end);
  826. /* Fill the buffer and pass it to upper layers */
  827. #ifdef CONFIG_FEC_MXC_SWAP_PACKET
  828. swap_packet((uint32_t *)addr, frame_length);
  829. #endif
  830. #ifdef CONFIG_DM_ETH
  831. memcpy(*packetp, (char *)addr, frame_length);
  832. #else
  833. memcpy(buff, (char *)addr, frame_length);
  834. net_process_received_packet(buff, frame_length);
  835. #endif
  836. len = frame_length;
  837. } else {
  838. if (bd_status & FEC_RBD_ERR)
  839. debug("error frame: 0x%08lx 0x%08x\n",
  840. addr, bd_status);
  841. }
  842. /*
  843. * Free the current buffer, restart the engine and move forward
  844. * to the next buffer. Here we check if the whole cacheline of
  845. * descriptors was already processed and if so, we mark it free
  846. * as whole.
  847. */
  848. size = RXDESC_PER_CACHELINE - 1;
  849. if ((fec->rbd_index & size) == size) {
  850. i = fec->rbd_index - size;
  851. addr = (ulong)&fec->rbd_base[i];
  852. for (; i <= fec->rbd_index ; i++) {
  853. fec_rbd_clean(i == (FEC_RBD_NUM - 1),
  854. &fec->rbd_base[i]);
  855. }
  856. flush_dcache_range(addr,
  857. addr + ARCH_DMA_MINALIGN);
  858. }
  859. fec_rx_task_enable(fec);
  860. fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
  861. }
  862. debug("fec_recv: stop\n");
  863. return len;
  864. }
  865. static void fec_set_dev_name(char *dest, int dev_id)
  866. {
  867. sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
  868. }
  869. static int fec_alloc_descs(struct fec_priv *fec)
  870. {
  871. unsigned int size;
  872. int i;
  873. uint8_t *data;
  874. ulong addr;
  875. /* Allocate TX descriptors. */
  876. size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
  877. fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
  878. if (!fec->tbd_base)
  879. goto err_tx;
  880. /* Allocate RX descriptors. */
  881. size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
  882. fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
  883. if (!fec->rbd_base)
  884. goto err_rx;
  885. memset(fec->rbd_base, 0, size);
  886. /* Allocate RX buffers. */
  887. /* Maximum RX buffer size. */
  888. size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
  889. for (i = 0; i < FEC_RBD_NUM; i++) {
  890. data = memalign(FEC_DMA_RX_MINALIGN, size);
  891. if (!data) {
  892. printf("%s: error allocating rxbuf %d\n", __func__, i);
  893. goto err_ring;
  894. }
  895. memset(data, 0, size);
  896. addr = (ulong)data;
  897. fec->rbd_base[i].data_pointer = (uint32_t)addr;
  898. fec->rbd_base[i].status = FEC_RBD_EMPTY;
  899. fec->rbd_base[i].data_length = 0;
  900. /* Flush the buffer to memory. */
  901. flush_dcache_range(addr, addr + size);
  902. }
  903. /* Mark the last RBD to close the ring. */
  904. fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
  905. fec->rbd_index = 0;
  906. fec->tbd_index = 0;
  907. return 0;
  908. err_ring:
  909. for (; i >= 0; i--) {
  910. addr = fec->rbd_base[i].data_pointer;
  911. free((void *)addr);
  912. }
  913. free(fec->rbd_base);
  914. err_rx:
  915. free(fec->tbd_base);
  916. err_tx:
  917. return -ENOMEM;
  918. }
  919. static void fec_free_descs(struct fec_priv *fec)
  920. {
  921. int i;
  922. ulong addr;
  923. for (i = 0; i < FEC_RBD_NUM; i++) {
  924. addr = fec->rbd_base[i].data_pointer;
  925. free((void *)addr);
  926. }
  927. free(fec->rbd_base);
  928. free(fec->tbd_base);
  929. }
  930. struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
  931. {
  932. struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
  933. struct mii_dev *bus;
  934. int ret;
  935. bus = mdio_alloc();
  936. if (!bus) {
  937. printf("mdio_alloc failed\n");
  938. return NULL;
  939. }
  940. bus->read = fec_phy_read;
  941. bus->write = fec_phy_write;
  942. bus->priv = eth;
  943. fec_set_dev_name(bus->name, dev_id);
  944. ret = mdio_register(bus);
  945. if (ret) {
  946. printf("mdio_register failed\n");
  947. free(bus);
  948. return NULL;
  949. }
  950. fec_mii_setspeed(eth);
  951. return bus;
  952. }
  953. #ifndef CONFIG_DM_ETH
  954. #ifdef CONFIG_PHYLIB
  955. int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr,
  956. struct mii_dev *bus, struct phy_device *phydev)
  957. #else
  958. static int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr,
  959. struct mii_dev *bus, int phy_id)
  960. #endif
  961. {
  962. struct eth_device *edev;
  963. struct fec_priv *fec;
  964. unsigned char ethaddr[6];
  965. char mac[16];
  966. uint32_t start;
  967. int ret = 0;
  968. /* create and fill edev struct */
  969. edev = (struct eth_device *)malloc(sizeof(struct eth_device));
  970. if (!edev) {
  971. puts("fec_mxc: not enough malloc memory for eth_device\n");
  972. ret = -ENOMEM;
  973. goto err1;
  974. }
  975. fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
  976. if (!fec) {
  977. puts("fec_mxc: not enough malloc memory for fec_priv\n");
  978. ret = -ENOMEM;
  979. goto err2;
  980. }
  981. memset(edev, 0, sizeof(*edev));
  982. memset(fec, 0, sizeof(*fec));
  983. ret = fec_alloc_descs(fec);
  984. if (ret)
  985. goto err3;
  986. edev->priv = fec;
  987. edev->init = fec_init;
  988. edev->send = fec_send;
  989. edev->recv = fec_recv;
  990. edev->halt = fec_halt;
  991. edev->write_hwaddr = fec_set_hwaddr;
  992. fec->eth = (struct ethernet_regs *)(ulong)base_addr;
  993. fec->bd = bd;
  994. fec->xcv_type = CONFIG_FEC_XCV_TYPE;
  995. /* Reset chip. */
  996. writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
  997. start = get_timer(0);
  998. while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
  999. if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
  1000. printf("FEC MXC: Timeout resetting chip\n");
  1001. goto err4;
  1002. }
  1003. udelay(10);
  1004. }
  1005. fec_reg_setup(fec);
  1006. fec_set_dev_name(edev->name, dev_id);
  1007. fec->dev_id = (dev_id == -1) ? 0 : dev_id;
  1008. fec->bus = bus;
  1009. fec_mii_setspeed(bus->priv);
  1010. #ifdef CONFIG_PHYLIB
  1011. fec->phydev = phydev;
  1012. phy_connect_dev(phydev, edev);
  1013. /* Configure phy */
  1014. phy_config(phydev);
  1015. #else
  1016. fec->phy_id = phy_id;
  1017. #endif
  1018. eth_register(edev);
  1019. /* only support one eth device, the index number pointed by dev_id */
  1020. edev->index = fec->dev_id;
  1021. if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
  1022. debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
  1023. memcpy(edev->enetaddr, ethaddr, 6);
  1024. if (fec->dev_id)
  1025. sprintf(mac, "eth%daddr", fec->dev_id);
  1026. else
  1027. strcpy(mac, "ethaddr");
  1028. if (!env_get(mac))
  1029. eth_env_set_enetaddr(mac, ethaddr);
  1030. }
  1031. return ret;
  1032. err4:
  1033. fec_free_descs(fec);
  1034. err3:
  1035. free(fec);
  1036. err2:
  1037. free(edev);
  1038. err1:
  1039. return ret;
  1040. }
  1041. int fecmxc_initialize_multi(struct bd_info *bd, int dev_id, int phy_id,
  1042. uint32_t addr)
  1043. {
  1044. uint32_t base_mii;
  1045. struct mii_dev *bus = NULL;
  1046. #ifdef CONFIG_PHYLIB
  1047. struct phy_device *phydev = NULL;
  1048. #endif
  1049. int ret;
  1050. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  1051. if (enet_fused((ulong)addr)) {
  1052. printf("SoC fuse indicates Ethernet@0x%x is unavailable.\n", addr);
  1053. return -ENODEV;
  1054. }
  1055. }
  1056. #ifdef CONFIG_FEC_MXC_MDIO_BASE
  1057. /*
  1058. * The i.MX28 has two ethernet interfaces, but they are not equal.
  1059. * Only the first one can access the MDIO bus.
  1060. */
  1061. base_mii = CONFIG_FEC_MXC_MDIO_BASE;
  1062. #else
  1063. base_mii = addr;
  1064. #endif
  1065. debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
  1066. bus = fec_get_miibus(base_mii, dev_id);
  1067. if (!bus)
  1068. return -ENOMEM;
  1069. #ifdef CONFIG_PHYLIB
  1070. phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
  1071. if (!phydev) {
  1072. mdio_unregister(bus);
  1073. free(bus);
  1074. return -ENOMEM;
  1075. }
  1076. ret = fec_probe(bd, dev_id, addr, bus, phydev);
  1077. #else
  1078. ret = fec_probe(bd, dev_id, addr, bus, phy_id);
  1079. #endif
  1080. if (ret) {
  1081. #ifdef CONFIG_PHYLIB
  1082. free(phydev);
  1083. #endif
  1084. mdio_unregister(bus);
  1085. free(bus);
  1086. }
  1087. return ret;
  1088. }
  1089. #ifdef CONFIG_FEC_MXC_PHYADDR
  1090. int fecmxc_initialize(struct bd_info *bd)
  1091. {
  1092. return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
  1093. IMX_FEC_BASE);
  1094. }
  1095. #endif
  1096. #ifndef CONFIG_PHYLIB
  1097. int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
  1098. {
  1099. struct fec_priv *fec = (struct fec_priv *)dev->priv;
  1100. fec->mii_postcall = cb;
  1101. return 0;
  1102. }
  1103. #endif
  1104. #else
  1105. static int fecmxc_read_rom_hwaddr(struct udevice *dev)
  1106. {
  1107. struct fec_priv *priv = dev_get_priv(dev);
  1108. struct eth_pdata *pdata = dev_get_plat(dev);
  1109. return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
  1110. }
  1111. static int fecmxc_set_promisc(struct udevice *dev, bool enable)
  1112. {
  1113. struct fec_priv *priv = dev_get_priv(dev);
  1114. priv->promisc = enable;
  1115. return 0;
  1116. }
  1117. static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
  1118. {
  1119. if (packet)
  1120. free(packet);
  1121. return 0;
  1122. }
  1123. static const struct eth_ops fecmxc_ops = {
  1124. .start = fecmxc_init,
  1125. .send = fecmxc_send,
  1126. .recv = fecmxc_recv,
  1127. .free_pkt = fecmxc_free_pkt,
  1128. .stop = fecmxc_halt,
  1129. .write_hwaddr = fecmxc_set_hwaddr,
  1130. .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
  1131. .set_promisc = fecmxc_set_promisc,
  1132. };
  1133. static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
  1134. {
  1135. struct ofnode_phandle_args phandle_args;
  1136. int reg, ret;
  1137. ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
  1138. &phandle_args);
  1139. if (ret) {
  1140. priv->phy_of_node = ofnode_find_subnode(dev_ofnode(dev),
  1141. "fixed-link");
  1142. if (ofnode_valid(priv->phy_of_node))
  1143. return 0;
  1144. debug("Failed to find phy-handle (err = %d)\n", ret);
  1145. return ret;
  1146. }
  1147. if (!ofnode_is_available(phandle_args.node))
  1148. return -ENOENT;
  1149. priv->phy_of_node = phandle_args.node;
  1150. reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
  1151. return reg;
  1152. }
  1153. static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
  1154. {
  1155. struct phy_device *phydev;
  1156. int addr;
  1157. addr = device_get_phy_addr(priv, dev);
  1158. #ifdef CONFIG_FEC_MXC_PHYADDR
  1159. addr = CONFIG_FEC_MXC_PHYADDR;
  1160. #endif
  1161. phydev = phy_connect(priv->bus, addr, dev, priv->interface);
  1162. if (!phydev)
  1163. return -ENODEV;
  1164. priv->phydev = phydev;
  1165. priv->phydev->node = priv->phy_of_node;
  1166. phy_config(phydev);
  1167. return 0;
  1168. }
  1169. #if CONFIG_IS_ENABLED(DM_GPIO)
  1170. /* FEC GPIO reset */
  1171. static void fec_gpio_reset(struct fec_priv *priv)
  1172. {
  1173. debug("fec_gpio_reset: fec_gpio_reset(dev)\n");
  1174. if (dm_gpio_is_valid(&priv->phy_reset_gpio)) {
  1175. dm_gpio_set_value(&priv->phy_reset_gpio, 1);
  1176. mdelay(priv->reset_delay);
  1177. dm_gpio_set_value(&priv->phy_reset_gpio, 0);
  1178. if (priv->reset_post_delay)
  1179. mdelay(priv->reset_post_delay);
  1180. }
  1181. }
  1182. #endif
  1183. static int fecmxc_probe(struct udevice *dev)
  1184. {
  1185. bool dm_mii_bus = true;
  1186. struct eth_pdata *pdata = dev_get_plat(dev);
  1187. struct fec_priv *priv = dev_get_priv(dev);
  1188. struct mii_dev *bus = NULL;
  1189. uint32_t start;
  1190. int ret;
  1191. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  1192. if (enet_fused((ulong)priv->eth)) {
  1193. printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth);
  1194. return -ENODEV;
  1195. }
  1196. }
  1197. if (IS_ENABLED(CONFIG_IMX8)) {
  1198. ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
  1199. if (ret < 0) {
  1200. debug("Can't get FEC ipg clk: %d\n", ret);
  1201. return ret;
  1202. }
  1203. ret = clk_enable(&priv->ipg_clk);
  1204. if (ret < 0) {
  1205. debug("Can't enable FEC ipg clk: %d\n", ret);
  1206. return ret;
  1207. }
  1208. priv->clk_rate = clk_get_rate(&priv->ipg_clk);
  1209. } else if (CONFIG_IS_ENABLED(CLK_CCF)) {
  1210. ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
  1211. if (ret < 0) {
  1212. debug("Can't get FEC ipg clk: %d\n", ret);
  1213. return ret;
  1214. }
  1215. ret = clk_enable(&priv->ipg_clk);
  1216. if(ret)
  1217. return ret;
  1218. ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
  1219. if (ret < 0) {
  1220. debug("Can't get FEC ahb clk: %d\n", ret);
  1221. return ret;
  1222. }
  1223. ret = clk_enable(&priv->ahb_clk);
  1224. if (ret)
  1225. return ret;
  1226. ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out);
  1227. if (!ret) {
  1228. ret = clk_enable(&priv->clk_enet_out);
  1229. if (ret)
  1230. return ret;
  1231. }
  1232. ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
  1233. if (!ret) {
  1234. ret = clk_enable(&priv->clk_ref);
  1235. if (ret)
  1236. return ret;
  1237. }
  1238. ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp);
  1239. if (!ret) {
  1240. ret = clk_enable(&priv->clk_ptp);
  1241. if (ret)
  1242. return ret;
  1243. }
  1244. priv->clk_rate = clk_get_rate(&priv->ipg_clk);
  1245. }
  1246. ret = fec_alloc_descs(priv);
  1247. if (ret)
  1248. return ret;
  1249. #ifdef CONFIG_DM_REGULATOR
  1250. if (priv->phy_supply) {
  1251. ret = regulator_set_enable(priv->phy_supply, true);
  1252. if (ret) {
  1253. printf("%s: Error enabling phy supply\n", dev->name);
  1254. return ret;
  1255. }
  1256. }
  1257. #endif
  1258. #if CONFIG_IS_ENABLED(DM_GPIO)
  1259. fec_gpio_reset(priv);
  1260. #endif
  1261. /* Reset chip. */
  1262. writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
  1263. &priv->eth->ecntrl);
  1264. start = get_timer(0);
  1265. while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
  1266. if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
  1267. printf("FEC MXC: Timeout reseting chip\n");
  1268. goto err_timeout;
  1269. }
  1270. udelay(10);
  1271. }
  1272. fec_reg_setup(priv);
  1273. priv->dev_id = dev_seq(dev);
  1274. #ifdef CONFIG_DM_ETH_PHY
  1275. bus = eth_phy_get_mdio_bus(dev);
  1276. #endif
  1277. if (!bus) {
  1278. dm_mii_bus = false;
  1279. #ifdef CONFIG_FEC_MXC_MDIO_BASE
  1280. bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE,
  1281. dev_seq(dev));
  1282. #else
  1283. bus = fec_get_miibus((ulong)priv->eth, dev_seq(dev));
  1284. #endif
  1285. }
  1286. if (!bus) {
  1287. ret = -ENOMEM;
  1288. goto err_mii;
  1289. }
  1290. #ifdef CONFIG_DM_ETH_PHY
  1291. eth_phy_set_mdio_bus(dev, bus);
  1292. #endif
  1293. priv->bus = bus;
  1294. priv->interface = pdata->phy_interface;
  1295. switch (priv->interface) {
  1296. case PHY_INTERFACE_MODE_MII:
  1297. priv->xcv_type = MII100;
  1298. break;
  1299. case PHY_INTERFACE_MODE_RMII:
  1300. priv->xcv_type = RMII;
  1301. break;
  1302. case PHY_INTERFACE_MODE_RGMII:
  1303. case PHY_INTERFACE_MODE_RGMII_ID:
  1304. case PHY_INTERFACE_MODE_RGMII_RXID:
  1305. case PHY_INTERFACE_MODE_RGMII_TXID:
  1306. priv->xcv_type = RGMII;
  1307. break;
  1308. default:
  1309. priv->xcv_type = CONFIG_FEC_XCV_TYPE;
  1310. printf("Unsupported interface type %d defaulting to %d\n",
  1311. priv->interface, priv->xcv_type);
  1312. break;
  1313. }
  1314. ret = fec_phy_init(priv, dev);
  1315. if (ret)
  1316. goto err_phy;
  1317. return 0;
  1318. err_phy:
  1319. if (!dm_mii_bus) {
  1320. mdio_unregister(bus);
  1321. free(bus);
  1322. }
  1323. err_mii:
  1324. err_timeout:
  1325. fec_free_descs(priv);
  1326. return ret;
  1327. }
  1328. static int fecmxc_remove(struct udevice *dev)
  1329. {
  1330. struct fec_priv *priv = dev_get_priv(dev);
  1331. free(priv->phydev);
  1332. fec_free_descs(priv);
  1333. mdio_unregister(priv->bus);
  1334. mdio_free(priv->bus);
  1335. #ifdef CONFIG_DM_REGULATOR
  1336. if (priv->phy_supply)
  1337. regulator_set_enable(priv->phy_supply, false);
  1338. #endif
  1339. return 0;
  1340. }
  1341. static int fecmxc_of_to_plat(struct udevice *dev)
  1342. {
  1343. int ret = 0;
  1344. struct eth_pdata *pdata = dev_get_plat(dev);
  1345. struct fec_priv *priv = dev_get_priv(dev);
  1346. const char *phy_mode;
  1347. pdata->iobase = dev_read_addr(dev);
  1348. priv->eth = (struct ethernet_regs *)pdata->iobase;
  1349. pdata->phy_interface = -1;
  1350. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  1351. NULL);
  1352. if (phy_mode)
  1353. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  1354. if (pdata->phy_interface == -1) {
  1355. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  1356. return -EINVAL;
  1357. }
  1358. #ifdef CONFIG_DM_REGULATOR
  1359. device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
  1360. #endif
  1361. #if CONFIG_IS_ENABLED(DM_GPIO)
  1362. ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
  1363. &priv->phy_reset_gpio, GPIOD_IS_OUT);
  1364. if (ret < 0)
  1365. return 0; /* property is optional, don't return error! */
  1366. priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1);
  1367. if (priv->reset_delay > 1000) {
  1368. printf("FEC MXC: phy reset duration should be <= 1000ms\n");
  1369. /* property value wrong, use default value */
  1370. priv->reset_delay = 1;
  1371. }
  1372. priv->reset_post_delay = dev_read_u32_default(dev,
  1373. "phy-reset-post-delay",
  1374. 0);
  1375. if (priv->reset_post_delay > 1000) {
  1376. printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
  1377. /* property value wrong, use default value */
  1378. priv->reset_post_delay = 0;
  1379. }
  1380. #endif
  1381. return 0;
  1382. }
  1383. static const struct udevice_id fecmxc_ids[] = {
  1384. { .compatible = "fsl,imx28-fec" },
  1385. { .compatible = "fsl,imx6q-fec" },
  1386. { .compatible = "fsl,imx6sl-fec" },
  1387. { .compatible = "fsl,imx6sx-fec" },
  1388. { .compatible = "fsl,imx6ul-fec" },
  1389. { .compatible = "fsl,imx53-fec" },
  1390. { .compatible = "fsl,imx7d-fec" },
  1391. { .compatible = "fsl,mvf600-fec" },
  1392. { }
  1393. };
  1394. U_BOOT_DRIVER(fecmxc_gem) = {
  1395. .name = "fecmxc",
  1396. .id = UCLASS_ETH,
  1397. .of_match = fecmxc_ids,
  1398. .of_to_plat = fecmxc_of_to_plat,
  1399. .probe = fecmxc_probe,
  1400. .remove = fecmxc_remove,
  1401. .ops = &fecmxc_ops,
  1402. .priv_auto = sizeof(struct fec_priv),
  1403. .plat_auto = sizeof(struct eth_pdata),
  1404. };
  1405. #endif