dwmac_meson8b.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2021 BayLibre, SAS
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <dm.h>
  8. #include <phy.h>
  9. #include "designware.h"
  10. #include <dm/device_compat.h>
  11. #include <linux/err.h>
  12. #define ETH_REG_0 0x0
  13. #define ETH_REG_1 0x4
  14. #define ETH_REG_2 0x18
  15. #define ETH_REG_3 0x1c
  16. #define GX_ETH_REG_0_PHY_INTF BIT(0)
  17. #define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
  18. #define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
  19. #define GX_ETH_REG_0_PHY_CLK_EN BIT(10)
  20. #define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11)
  21. #define GX_ETH_REG_0_CLK_EN BIT(12)
  22. #define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0)
  23. #define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2)
  24. #define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
  25. #define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
  26. #define AXG_ETH_REG_0_PHY_CLK_EN BIT(10)
  27. #define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11)
  28. #define AXG_ETH_REG_0_CLK_EN BIT(12)
  29. struct dwmac_meson8b_plat {
  30. struct dw_eth_pdata dw_eth_pdata;
  31. int (*dwmac_setup)(struct udevice *dev, struct eth_pdata *edata);
  32. void *regs;
  33. };
  34. static int dwmac_meson8b_of_to_plat(struct udevice *dev)
  35. {
  36. struct dwmac_meson8b_plat *pdata = dev_get_plat(dev);
  37. pdata->regs = (void *)dev_read_addr_index(dev, 1);
  38. if ((fdt_addr_t)pdata->regs == FDT_ADDR_T_NONE)
  39. return -EINVAL;
  40. pdata->dwmac_setup = (void *)dev_get_driver_data(dev);
  41. if (!pdata->dwmac_setup)
  42. return -EINVAL;
  43. return designware_eth_of_to_plat(dev);
  44. }
  45. static int dwmac_setup_axg(struct udevice *dev, struct eth_pdata *edata)
  46. {
  47. struct dwmac_meson8b_plat *plat = dev_get_plat(dev);
  48. switch (edata->phy_interface) {
  49. case PHY_INTERFACE_MODE_RGMII:
  50. case PHY_INTERFACE_MODE_RGMII_ID:
  51. /* Set RGMII mode */
  52. setbits_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
  53. AXG_ETH_REG_0_TX_PHASE(1) |
  54. AXG_ETH_REG_0_TX_RATIO(4) |
  55. AXG_ETH_REG_0_PHY_CLK_EN |
  56. AXG_ETH_REG_0_CLK_EN);
  57. break;
  58. case PHY_INTERFACE_MODE_RGMII_RXID:
  59. case PHY_INTERFACE_MODE_RGMII_TXID:
  60. /* TOFIX: handle amlogic,tx-delay-ns & rx-internal-delay-ps from DT */
  61. setbits_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
  62. AXG_ETH_REG_0_TX_RATIO(4) |
  63. AXG_ETH_REG_0_PHY_CLK_EN |
  64. AXG_ETH_REG_0_CLK_EN);
  65. break;
  66. case PHY_INTERFACE_MODE_RMII:
  67. /* Set RMII mode */
  68. out_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
  69. AXG_ETH_REG_0_INVERT_RMII_CLK |
  70. AXG_ETH_REG_0_CLK_EN);
  71. break;
  72. default:
  73. dev_err(dev, "Unsupported PHY mode\n");
  74. return -EINVAL;
  75. }
  76. return 0;
  77. }
  78. static int dwmac_setup_gx(struct udevice *dev, struct eth_pdata *edata)
  79. {
  80. struct dwmac_meson8b_plat *plat = dev_get_plat(dev);
  81. switch (edata->phy_interface) {
  82. case PHY_INTERFACE_MODE_RGMII:
  83. case PHY_INTERFACE_MODE_RGMII_ID:
  84. /* Set RGMII mode */
  85. setbits_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
  86. GX_ETH_REG_0_TX_PHASE(1) |
  87. GX_ETH_REG_0_TX_RATIO(4) |
  88. GX_ETH_REG_0_PHY_CLK_EN |
  89. GX_ETH_REG_0_CLK_EN);
  90. break;
  91. case PHY_INTERFACE_MODE_RGMII_RXID:
  92. case PHY_INTERFACE_MODE_RGMII_TXID:
  93. /* TOFIX: handle amlogic,tx-delay-ns & rx-internal-delay-ps from DT */
  94. setbits_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
  95. GX_ETH_REG_0_TX_RATIO(4) |
  96. GX_ETH_REG_0_PHY_CLK_EN |
  97. GX_ETH_REG_0_CLK_EN);
  98. break;
  99. case PHY_INTERFACE_MODE_RMII:
  100. /* Set RMII mode */
  101. out_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
  102. GX_ETH_REG_0_CLK_EN);
  103. if (!IS_ENABLED(CONFIG_MESON_GXBB))
  104. writel(0x10110181, plat->regs + ETH_REG_2);
  105. break;
  106. default:
  107. dev_err(dev, "Unsupported PHY mode\n");
  108. return -EINVAL;
  109. }
  110. return 0;
  111. }
  112. static int dwmac_meson8b_probe(struct udevice *dev)
  113. {
  114. struct dwmac_meson8b_plat *pdata = dev_get_plat(dev);
  115. struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata;
  116. int ret;
  117. ret = pdata->dwmac_setup(dev, edata);
  118. if (ret)
  119. return ret;
  120. return designware_eth_probe(dev);
  121. }
  122. static const struct udevice_id dwmac_meson8b_ids[] = {
  123. { .compatible = "amlogic,meson-gxbb-dwmac", .data = (ulong)dwmac_setup_gx },
  124. { .compatible = "amlogic,meson-g12a-dwmac", .data = (ulong)dwmac_setup_axg },
  125. { .compatible = "amlogic,meson-axg-dwmac", .data = (ulong)dwmac_setup_axg },
  126. { }
  127. };
  128. U_BOOT_DRIVER(dwmac_meson8b) = {
  129. .name = "dwmac_meson8b",
  130. .id = UCLASS_ETH,
  131. .of_match = dwmac_meson8b_ids,
  132. .of_to_plat = dwmac_meson8b_of_to_plat,
  133. .probe = dwmac_meson8b_probe,
  134. .ops = &designware_eth_ops,
  135. .priv_auto = sizeof(struct dw_eth_dev),
  136. .plat_auto = sizeof(struct dwmac_meson8b_plat),
  137. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  138. };