dnet.c 9.7 KB

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  1. /*
  2. * Dave Ethernet Controller driver
  3. *
  4. * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <common.h>
  11. #include <log.h>
  12. #include <linux/delay.h>
  13. #ifndef CONFIG_DNET_AUTONEG_TIMEOUT
  14. #define CONFIG_DNET_AUTONEG_TIMEOUT 5000000 /* default value */
  15. #endif
  16. #include <net.h>
  17. #include <malloc.h>
  18. #include <linux/mii.h>
  19. #include <miiphy.h>
  20. #include <asm/io.h>
  21. #include <asm/unaligned.h>
  22. #include "dnet.h"
  23. struct dnet_device {
  24. struct dnet_registers *regs;
  25. const struct device *dev;
  26. struct eth_device netdev;
  27. unsigned short phy_addr;
  28. };
  29. /* get struct dnet_device from given struct netdev */
  30. #define to_dnet(_nd) container_of(_nd, struct dnet_device, netdev)
  31. /* function for reading internal MAC register */
  32. u16 dnet_readw_mac(struct dnet_device *dnet, u16 reg)
  33. {
  34. u16 data_read;
  35. /* issue a read */
  36. writel(reg, &dnet->regs->MACREG_ADDR);
  37. /* since a read/write op to the MAC is very slow,
  38. * we must wait before reading the data */
  39. udelay(1);
  40. /* read data read from the MAC register */
  41. data_read = readl(&dnet->regs->MACREG_DATA);
  42. /* all done */
  43. return data_read;
  44. }
  45. /* function for writing internal MAC register */
  46. void dnet_writew_mac(struct dnet_device *dnet, u16 reg, u16 val)
  47. {
  48. /* load data to write */
  49. writel(val, &dnet->regs->MACREG_DATA);
  50. /* issue a write */
  51. writel(reg | DNET_INTERNAL_WRITE, &dnet->regs->MACREG_ADDR);
  52. /* since a read/write op to the MAC is very slow,
  53. * we must wait before exiting */
  54. udelay(1);
  55. }
  56. static void dnet_mdio_write(struct dnet_device *dnet, u8 reg, u16 value)
  57. {
  58. u16 tmp;
  59. debug(DRIVERNAME "dnet_mdio_write %02x:%02x <- %04x\n",
  60. dnet->phy_addr, reg, value);
  61. while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
  62. DNET_INTERNAL_GMII_MNG_CMD_FIN))
  63. ;
  64. /* prepare for a write operation */
  65. tmp = (1 << 13);
  66. /* only 5 bits allowed for register offset */
  67. reg &= 0x1f;
  68. /* prepare reg_value for a write */
  69. tmp |= (dnet->phy_addr << 8);
  70. tmp |= reg;
  71. /* write data to write first */
  72. dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG, value);
  73. /* write control word */
  74. dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp);
  75. while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
  76. DNET_INTERNAL_GMII_MNG_CMD_FIN))
  77. ;
  78. }
  79. static u16 dnet_mdio_read(struct dnet_device *dnet, u8 reg)
  80. {
  81. u16 value;
  82. while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
  83. DNET_INTERNAL_GMII_MNG_CMD_FIN))
  84. ;
  85. /* only 5 bits allowed for register offset*/
  86. reg &= 0x1f;
  87. /* prepare reg_value for a read */
  88. value = (dnet->phy_addr << 8);
  89. value |= reg;
  90. /* write control word */
  91. dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, value);
  92. /* wait for end of transfer */
  93. while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
  94. DNET_INTERNAL_GMII_MNG_CMD_FIN))
  95. ;
  96. value = dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG);
  97. debug(DRIVERNAME "dnet_mdio_read %02x:%02x <- %04x\n",
  98. dnet->phy_addr, reg, value);
  99. return value;
  100. }
  101. static int dnet_send(struct eth_device *netdev, void *packet, int length)
  102. {
  103. struct dnet_device *dnet = to_dnet(netdev);
  104. int i, wrsz;
  105. unsigned int *bufp;
  106. unsigned int tx_cmd;
  107. debug(DRIVERNAME "[%s] Sending %u bytes\n", __func__, length);
  108. bufp = (unsigned int *) (((u32)packet) & 0xFFFFFFFC);
  109. wrsz = (u32)length + 3;
  110. wrsz += ((u32)packet) & 0x3;
  111. wrsz >>= 2;
  112. tx_cmd = ((((unsigned int)(packet)) & 0x03) << 16) | (u32)length;
  113. /* check if there is enough room for the current frame */
  114. if (wrsz < (DNET_FIFO_SIZE - readl(&dnet->regs->TX_FIFO_WCNT))) {
  115. for (i = 0; i < wrsz; i++)
  116. writel(*bufp++, &dnet->regs->TX_DATA_FIFO);
  117. /*
  118. * inform MAC that a packet's written and ready
  119. * to be shipped out
  120. */
  121. writel(tx_cmd, &dnet->regs->TX_LEN_FIFO);
  122. } else {
  123. printf(DRIVERNAME "No free space (actual %d, required %d "
  124. "(words))\n", DNET_FIFO_SIZE -
  125. readl(&dnet->regs->TX_FIFO_WCNT), wrsz);
  126. }
  127. /* No one cares anyway */
  128. return 0;
  129. }
  130. static int dnet_recv(struct eth_device *netdev)
  131. {
  132. struct dnet_device *dnet = to_dnet(netdev);
  133. unsigned int *data_ptr;
  134. int pkt_len, poll, i;
  135. u32 cmd_word;
  136. debug("Waiting for pkt (polling)\n");
  137. poll = 50;
  138. while ((readl(&dnet->regs->RX_FIFO_WCNT) >> 16) == 0) {
  139. udelay(10); /* wait 10 usec */
  140. if (--poll == 0)
  141. return 0; /* no pkt available */
  142. }
  143. cmd_word = readl(&dnet->regs->RX_LEN_FIFO);
  144. pkt_len = cmd_word & 0xFFFF;
  145. debug("Got pkt with size %d bytes\n", pkt_len);
  146. if (cmd_word & 0xDF180000)
  147. printf("%s packet receive error %x\n", __func__, cmd_word);
  148. data_ptr = (unsigned int *)net_rx_packets[0];
  149. for (i = 0; i < (pkt_len + 3) >> 2; i++)
  150. *data_ptr++ = readl(&dnet->regs->RX_DATA_FIFO);
  151. /* ok + 5 ?? */
  152. net_process_received_packet(net_rx_packets[0], pkt_len + 5);
  153. return 0;
  154. }
  155. static void dnet_set_hwaddr(struct eth_device *netdev)
  156. {
  157. struct dnet_device *dnet = to_dnet(netdev);
  158. u16 tmp;
  159. tmp = get_unaligned_be16(netdev->enetaddr);
  160. dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_0_REG, tmp);
  161. tmp = get_unaligned_be16(&netdev->enetaddr[2]);
  162. dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_1_REG, tmp);
  163. tmp = get_unaligned_be16(&netdev->enetaddr[4]);
  164. dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_2_REG, tmp);
  165. }
  166. static void dnet_phy_reset(struct dnet_device *dnet)
  167. {
  168. struct eth_device *netdev = &dnet->netdev;
  169. int i;
  170. u16 status, adv;
  171. adv = ADVERTISE_CSMA | ADVERTISE_ALL;
  172. dnet_mdio_write(dnet, MII_ADVERTISE, adv);
  173. printf("%s: Starting autonegotiation...\n", netdev->name);
  174. dnet_mdio_write(dnet, MII_BMCR, (BMCR_ANENABLE
  175. | BMCR_ANRESTART));
  176. for (i = 0; i < CONFIG_DNET_AUTONEG_TIMEOUT / 100; i++) {
  177. status = dnet_mdio_read(dnet, MII_BMSR);
  178. if (status & BMSR_ANEGCOMPLETE)
  179. break;
  180. udelay(100);
  181. }
  182. if (status & BMSR_ANEGCOMPLETE)
  183. printf("%s: Autonegotiation complete\n", netdev->name);
  184. else
  185. printf("%s: Autonegotiation timed out (status=0x%04x)\n",
  186. netdev->name, status);
  187. }
  188. static int dnet_phy_init(struct dnet_device *dnet)
  189. {
  190. struct eth_device *netdev = &dnet->netdev;
  191. u16 phy_id, status, adv, lpa;
  192. int media, speed, duplex;
  193. int i;
  194. u32 ctl_reg;
  195. /* Find a PHY */
  196. for (i = 0; i < 32; i++) {
  197. dnet->phy_addr = i;
  198. phy_id = dnet_mdio_read(dnet, MII_PHYSID1);
  199. if (phy_id != 0xffff) {
  200. /* ok we found it */
  201. printf("Found PHY at address %d PHYID (%04x:%04x)\n",
  202. i, phy_id,
  203. dnet_mdio_read(dnet, MII_PHYSID2));
  204. break;
  205. }
  206. }
  207. /* Check if the PHY is up to snuff... */
  208. phy_id = dnet_mdio_read(dnet, MII_PHYSID1);
  209. if (phy_id == 0xffff) {
  210. printf("%s: No PHY present\n", netdev->name);
  211. return -1;
  212. }
  213. status = dnet_mdio_read(dnet, MII_BMSR);
  214. if (!(status & BMSR_LSTATUS)) {
  215. /* Try to re-negotiate if we don't have link already. */
  216. dnet_phy_reset(dnet);
  217. for (i = 0; i < CONFIG_DNET_AUTONEG_TIMEOUT / 100; i++) {
  218. status = dnet_mdio_read(dnet, MII_BMSR);
  219. if (status & BMSR_LSTATUS)
  220. break;
  221. udelay(100);
  222. }
  223. }
  224. if (!(status & BMSR_LSTATUS)) {
  225. printf("%s: link down (status: 0x%04x)\n",
  226. netdev->name, status);
  227. return -1;
  228. } else {
  229. adv = dnet_mdio_read(dnet, MII_ADVERTISE);
  230. lpa = dnet_mdio_read(dnet, MII_LPA);
  231. media = mii_nway_result(lpa & adv);
  232. speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
  233. ? 1 : 0);
  234. duplex = (media & ADVERTISE_FULL) ? 1 : 0;
  235. /* 1000BaseT ethernet is not supported */
  236. printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
  237. netdev->name,
  238. speed ? "100" : "10",
  239. duplex ? "full" : "half",
  240. lpa);
  241. ctl_reg = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG);
  242. if (duplex)
  243. ctl_reg &= ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP);
  244. else
  245. ctl_reg |= DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP;
  246. dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg);
  247. return 0;
  248. }
  249. }
  250. static int dnet_init(struct eth_device *netdev, struct bd_info *bd)
  251. {
  252. struct dnet_device *dnet = to_dnet(netdev);
  253. u32 config;
  254. /*
  255. * dnet_halt should have been called at some point before now,
  256. * so we'll assume the controller is idle.
  257. */
  258. /* set hardware address */
  259. dnet_set_hwaddr(netdev);
  260. if (dnet_phy_init(dnet) < 0)
  261. return -1;
  262. /* flush rx/tx fifos */
  263. writel(DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH,
  264. &dnet->regs->SYS_CTL);
  265. udelay(1000);
  266. writel(0, &dnet->regs->SYS_CTL);
  267. config = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG);
  268. config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE |
  269. DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST |
  270. DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL |
  271. DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS;
  272. dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, config);
  273. /* Enable TX and RX */
  274. dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG,
  275. DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN);
  276. return 0;
  277. }
  278. static void dnet_halt(struct eth_device *netdev)
  279. {
  280. struct dnet_device *dnet = to_dnet(netdev);
  281. /* Disable TX and RX */
  282. dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG, 0);
  283. }
  284. int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr)
  285. {
  286. struct dnet_device *dnet;
  287. struct eth_device *netdev;
  288. unsigned int dev_capa;
  289. dnet = malloc(sizeof(struct dnet_device));
  290. if (!dnet) {
  291. printf("Error: Failed to allocate memory for DNET%d\n", id);
  292. return -1;
  293. }
  294. memset(dnet, 0, sizeof(struct dnet_device));
  295. netdev = &dnet->netdev;
  296. dnet->regs = (struct dnet_registers *)regs;
  297. dnet->phy_addr = phy_addr;
  298. sprintf(netdev->name, "dnet%d", id);
  299. netdev->init = dnet_init;
  300. netdev->halt = dnet_halt;
  301. netdev->send = dnet_send;
  302. netdev->recv = dnet_recv;
  303. dev_capa = readl(&dnet->regs->VERCAPS) & 0xFFFF;
  304. debug("%s: has %smdio, %sirq, %sgigabit, %sdma \n", netdev->name,
  305. (dev_capa & DNET_HAS_MDIO) ? "" : "no ",
  306. (dev_capa & DNET_HAS_IRQ) ? "" : "no ",
  307. (dev_capa & DNET_HAS_GIGABIT) ? "" : "no ",
  308. (dev_capa & DNET_HAS_DMA) ? "" : "no ");
  309. eth_register(netdev);
  310. return 0;
  311. }