designware.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. */
  6. /*
  7. * Designware ethernet IP driver for U-Boot
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <cpu_func.h>
  12. #include <dm.h>
  13. #include <errno.h>
  14. #include <log.h>
  15. #include <miiphy.h>
  16. #include <malloc.h>
  17. #include <net.h>
  18. #include <pci.h>
  19. #include <reset.h>
  20. #include <asm/cache.h>
  21. #include <dm/device_compat.h>
  22. #include <dm/device-internal.h>
  23. #include <dm/devres.h>
  24. #include <dm/lists.h>
  25. #include <linux/compiler.h>
  26. #include <linux/delay.h>
  27. #include <linux/err.h>
  28. #include <linux/kernel.h>
  29. #include <asm/io.h>
  30. #include <power/regulator.h>
  31. #include "designware.h"
  32. static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  33. {
  34. #ifdef CONFIG_DM_ETH
  35. struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
  36. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  37. #else
  38. struct eth_mac_regs *mac_p = bus->priv;
  39. #endif
  40. ulong start;
  41. u16 miiaddr;
  42. int timeout = CONFIG_MDIO_TIMEOUT;
  43. miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
  44. ((reg << MIIREGSHIFT) & MII_REGMSK);
  45. writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
  46. start = get_timer(0);
  47. while (get_timer(start) < timeout) {
  48. if (!(readl(&mac_p->miiaddr) & MII_BUSY))
  49. return readl(&mac_p->miidata);
  50. udelay(10);
  51. };
  52. return -ETIMEDOUT;
  53. }
  54. static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  55. u16 val)
  56. {
  57. #ifdef CONFIG_DM_ETH
  58. struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
  59. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  60. #else
  61. struct eth_mac_regs *mac_p = bus->priv;
  62. #endif
  63. ulong start;
  64. u16 miiaddr;
  65. int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
  66. writel(val, &mac_p->miidata);
  67. miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
  68. ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
  69. writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
  70. start = get_timer(0);
  71. while (get_timer(start) < timeout) {
  72. if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
  73. ret = 0;
  74. break;
  75. }
  76. udelay(10);
  77. };
  78. return ret;
  79. }
  80. #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
  81. static int __dw_mdio_reset(struct udevice *dev)
  82. {
  83. struct dw_eth_dev *priv = dev_get_priv(dev);
  84. struct dw_eth_pdata *pdata = dev_get_plat(dev);
  85. int ret;
  86. if (!dm_gpio_is_valid(&priv->reset_gpio))
  87. return 0;
  88. /* reset the phy */
  89. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  90. if (ret)
  91. return ret;
  92. udelay(pdata->reset_delays[0]);
  93. ret = dm_gpio_set_value(&priv->reset_gpio, 1);
  94. if (ret)
  95. return ret;
  96. udelay(pdata->reset_delays[1]);
  97. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  98. if (ret)
  99. return ret;
  100. udelay(pdata->reset_delays[2]);
  101. return 0;
  102. }
  103. static int dw_mdio_reset(struct mii_dev *bus)
  104. {
  105. struct udevice *dev = bus->priv;
  106. return __dw_mdio_reset(dev);
  107. }
  108. #endif
  109. #if IS_ENABLED(CONFIG_DM_MDIO)
  110. int designware_eth_mdio_read(struct udevice *mdio_dev, int addr, int devad, int reg)
  111. {
  112. struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
  113. return dw_mdio_read(pdata->mii_bus, addr, devad, reg);
  114. }
  115. int designware_eth_mdio_write(struct udevice *mdio_dev, int addr, int devad, int reg, u16 val)
  116. {
  117. struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
  118. return dw_mdio_write(pdata->mii_bus, addr, devad, reg, val);
  119. }
  120. #if CONFIG_IS_ENABLED(DM_GPIO)
  121. int designware_eth_mdio_reset(struct udevice *mdio_dev)
  122. {
  123. struct mdio_perdev_priv *mdio_pdata = dev_get_uclass_priv(mdio_dev);
  124. struct udevice *dev = mdio_pdata->mii_bus->priv;
  125. return __dw_mdio_reset(dev->parent);
  126. }
  127. #endif
  128. static const struct mdio_ops designware_eth_mdio_ops = {
  129. .read = designware_eth_mdio_read,
  130. .write = designware_eth_mdio_write,
  131. #if CONFIG_IS_ENABLED(DM_GPIO)
  132. .reset = designware_eth_mdio_reset,
  133. #endif
  134. };
  135. static int designware_eth_mdio_probe(struct udevice *dev)
  136. {
  137. /* Use the priv data of parent */
  138. dev_set_priv(dev, dev_get_priv(dev->parent));
  139. return 0;
  140. }
  141. U_BOOT_DRIVER(designware_eth_mdio) = {
  142. .name = "eth_designware_mdio",
  143. .id = UCLASS_MDIO,
  144. .probe = designware_eth_mdio_probe,
  145. .ops = &designware_eth_mdio_ops,
  146. .plat_auto = sizeof(struct mdio_perdev_priv),
  147. };
  148. #endif
  149. static int dw_mdio_init(const char *name, void *priv)
  150. {
  151. struct mii_dev *bus = mdio_alloc();
  152. if (!bus) {
  153. printf("Failed to allocate MDIO bus\n");
  154. return -ENOMEM;
  155. }
  156. bus->read = dw_mdio_read;
  157. bus->write = dw_mdio_write;
  158. snprintf(bus->name, sizeof(bus->name), "%s", name);
  159. #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
  160. bus->reset = dw_mdio_reset;
  161. #endif
  162. bus->priv = priv;
  163. return mdio_register(bus);
  164. }
  165. #if IS_ENABLED(CONFIG_DM_MDIO)
  166. static int dw_dm_mdio_init(const char *name, void *priv)
  167. {
  168. struct udevice *dev = priv;
  169. ofnode node;
  170. int ret;
  171. ofnode_for_each_subnode(node, dev_ofnode(dev)) {
  172. const char *subnode_name = ofnode_get_name(node);
  173. struct udevice *mdiodev;
  174. if (strcmp(subnode_name, "mdio"))
  175. continue;
  176. ret = device_bind_driver_to_node(dev, "eth_designware_mdio",
  177. subnode_name, node, &mdiodev);
  178. if (ret)
  179. debug("%s: not able to bind mdio device node\n", __func__);
  180. return 0;
  181. }
  182. printf("%s: mdio node is missing, registering legacy mdio bus", __func__);
  183. return dw_mdio_init(name, priv);
  184. }
  185. #endif
  186. static void tx_descs_init(struct dw_eth_dev *priv)
  187. {
  188. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  189. struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
  190. char *txbuffs = &priv->txbuffs[0];
  191. struct dmamacdescr *desc_p;
  192. u32 idx;
  193. for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
  194. desc_p = &desc_table_p[idx];
  195. desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
  196. desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
  197. #if defined(CONFIG_DW_ALTDESCRIPTOR)
  198. desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
  199. DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
  200. DESC_TXSTS_TXCHECKINSCTRL |
  201. DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
  202. desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
  203. desc_p->dmamac_cntl = 0;
  204. desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
  205. #else
  206. desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
  207. desc_p->txrx_status = 0;
  208. #endif
  209. }
  210. /* Correcting the last pointer of the chain */
  211. desc_p->dmamac_next = (ulong)&desc_table_p[0];
  212. /* Flush all Tx buffer descriptors at once */
  213. flush_dcache_range((ulong)priv->tx_mac_descrtable,
  214. (ulong)priv->tx_mac_descrtable +
  215. sizeof(priv->tx_mac_descrtable));
  216. writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
  217. priv->tx_currdescnum = 0;
  218. }
  219. static void rx_descs_init(struct dw_eth_dev *priv)
  220. {
  221. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  222. struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
  223. char *rxbuffs = &priv->rxbuffs[0];
  224. struct dmamacdescr *desc_p;
  225. u32 idx;
  226. /* Before passing buffers to GMAC we need to make sure zeros
  227. * written there right after "priv" structure allocation were
  228. * flushed into RAM.
  229. * Otherwise there's a chance to get some of them flushed in RAM when
  230. * GMAC is already pushing data to RAM via DMA. This way incoming from
  231. * GMAC data will be corrupted. */
  232. flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
  233. for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
  234. desc_p = &desc_table_p[idx];
  235. desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
  236. desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
  237. desc_p->dmamac_cntl =
  238. (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
  239. DESC_RXCTRL_RXCHAIN;
  240. desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
  241. }
  242. /* Correcting the last pointer of the chain */
  243. desc_p->dmamac_next = (ulong)&desc_table_p[0];
  244. /* Flush all Rx buffer descriptors at once */
  245. flush_dcache_range((ulong)priv->rx_mac_descrtable,
  246. (ulong)priv->rx_mac_descrtable +
  247. sizeof(priv->rx_mac_descrtable));
  248. writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
  249. priv->rx_currdescnum = 0;
  250. }
  251. static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
  252. {
  253. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  254. u32 macid_lo, macid_hi;
  255. macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
  256. (mac_id[3] << 24);
  257. macid_hi = mac_id[4] + (mac_id[5] << 8);
  258. writel(macid_hi, &mac_p->macaddr0hi);
  259. writel(macid_lo, &mac_p->macaddr0lo);
  260. return 0;
  261. }
  262. static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
  263. struct phy_device *phydev)
  264. {
  265. u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
  266. if (!phydev->link) {
  267. printf("%s: No link.\n", phydev->dev->name);
  268. return 0;
  269. }
  270. if (phydev->speed != 1000)
  271. conf |= MII_PORTSELECT;
  272. else
  273. conf &= ~MII_PORTSELECT;
  274. if (phydev->speed == 100)
  275. conf |= FES_100;
  276. if (phydev->duplex)
  277. conf |= FULLDPLXMODE;
  278. writel(conf, &mac_p->conf);
  279. printf("Speed: %d, %s duplex%s\n", phydev->speed,
  280. (phydev->duplex) ? "full" : "half",
  281. (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
  282. return 0;
  283. }
  284. static void _dw_eth_halt(struct dw_eth_dev *priv)
  285. {
  286. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  287. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  288. writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
  289. writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
  290. phy_shutdown(priv->phydev);
  291. }
  292. int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
  293. {
  294. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  295. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  296. unsigned int start;
  297. int ret;
  298. writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
  299. /*
  300. * When a MII PHY is used, we must set the PS bit for the DMA
  301. * reset to succeed.
  302. */
  303. if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
  304. writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
  305. else
  306. writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
  307. start = get_timer(0);
  308. while (readl(&dma_p->busmode) & DMAMAC_SRST) {
  309. if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
  310. printf("DMA reset timeout\n");
  311. return -ETIMEDOUT;
  312. }
  313. mdelay(100);
  314. };
  315. /*
  316. * Soft reset above clears HW address registers.
  317. * So we have to set it here once again.
  318. */
  319. _dw_write_hwaddr(priv, enetaddr);
  320. rx_descs_init(priv);
  321. tx_descs_init(priv);
  322. writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
  323. #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
  324. writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
  325. &dma_p->opmode);
  326. #else
  327. writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
  328. &dma_p->opmode);
  329. #endif
  330. writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
  331. #ifdef CONFIG_DW_AXI_BURST_LEN
  332. writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
  333. #endif
  334. /* Start up the PHY */
  335. ret = phy_startup(priv->phydev);
  336. if (ret) {
  337. printf("Could not initialize PHY %s\n",
  338. priv->phydev->dev->name);
  339. return ret;
  340. }
  341. ret = dw_adjust_link(priv, mac_p, priv->phydev);
  342. if (ret)
  343. return ret;
  344. return 0;
  345. }
  346. int designware_eth_enable(struct dw_eth_dev *priv)
  347. {
  348. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  349. if (!priv->phydev->link)
  350. return -EIO;
  351. writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
  352. return 0;
  353. }
  354. #define ETH_ZLEN 60
  355. static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
  356. {
  357. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  358. u32 desc_num = priv->tx_currdescnum;
  359. struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
  360. ulong desc_start = (ulong)desc_p;
  361. ulong desc_end = desc_start +
  362. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  363. ulong data_start = desc_p->dmamac_addr;
  364. ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
  365. /*
  366. * Strictly we only need to invalidate the "txrx_status" field
  367. * for the following check, but on some platforms we cannot
  368. * invalidate only 4 bytes, so we flush the entire descriptor,
  369. * which is 16 bytes in total. This is safe because the
  370. * individual descriptors in the array are each aligned to
  371. * ARCH_DMA_MINALIGN and padded appropriately.
  372. */
  373. invalidate_dcache_range(desc_start, desc_end);
  374. /* Check if the descriptor is owned by CPU */
  375. if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
  376. printf("CPU not owner of tx frame\n");
  377. return -EPERM;
  378. }
  379. memcpy((void *)data_start, packet, length);
  380. if (length < ETH_ZLEN) {
  381. memset(&((char *)data_start)[length], 0, ETH_ZLEN - length);
  382. length = ETH_ZLEN;
  383. }
  384. /* Flush data to be sent */
  385. flush_dcache_range(data_start, data_end);
  386. #if defined(CONFIG_DW_ALTDESCRIPTOR)
  387. desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
  388. desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
  389. ((length << DESC_TXCTRL_SIZE1SHFT) &
  390. DESC_TXCTRL_SIZE1MASK);
  391. desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
  392. desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
  393. #else
  394. desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
  395. ((length << DESC_TXCTRL_SIZE1SHFT) &
  396. DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
  397. DESC_TXCTRL_TXFIRST;
  398. desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
  399. #endif
  400. /* Flush modified buffer descriptor */
  401. flush_dcache_range(desc_start, desc_end);
  402. /* Test the wrap-around condition. */
  403. if (++desc_num >= CONFIG_TX_DESCR_NUM)
  404. desc_num = 0;
  405. priv->tx_currdescnum = desc_num;
  406. /* Start the transmission */
  407. writel(POLL_DATA, &dma_p->txpolldemand);
  408. return 0;
  409. }
  410. static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
  411. {
  412. u32 status, desc_num = priv->rx_currdescnum;
  413. struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
  414. int length = -EAGAIN;
  415. ulong desc_start = (ulong)desc_p;
  416. ulong desc_end = desc_start +
  417. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  418. ulong data_start = desc_p->dmamac_addr;
  419. ulong data_end;
  420. /* Invalidate entire buffer descriptor */
  421. invalidate_dcache_range(desc_start, desc_end);
  422. status = desc_p->txrx_status;
  423. /* Check if the owner is the CPU */
  424. if (!(status & DESC_RXSTS_OWNBYDMA)) {
  425. length = (status & DESC_RXSTS_FRMLENMSK) >>
  426. DESC_RXSTS_FRMLENSHFT;
  427. /* Invalidate received data */
  428. data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
  429. invalidate_dcache_range(data_start, data_end);
  430. *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
  431. }
  432. return length;
  433. }
  434. static int _dw_free_pkt(struct dw_eth_dev *priv)
  435. {
  436. u32 desc_num = priv->rx_currdescnum;
  437. struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
  438. ulong desc_start = (ulong)desc_p;
  439. ulong desc_end = desc_start +
  440. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  441. /*
  442. * Make the current descriptor valid again and go to
  443. * the next one
  444. */
  445. desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
  446. /* Flush only status field - others weren't changed */
  447. flush_dcache_range(desc_start, desc_end);
  448. /* Test the wrap-around condition. */
  449. if (++desc_num >= CONFIG_RX_DESCR_NUM)
  450. desc_num = 0;
  451. priv->rx_currdescnum = desc_num;
  452. return 0;
  453. }
  454. static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
  455. {
  456. struct phy_device *phydev;
  457. int ret;
  458. #if IS_ENABLED(CONFIG_DM_MDIO) && IS_ENABLED(CONFIG_DM_ETH)
  459. phydev = dm_eth_phy_connect(dev);
  460. if (!phydev)
  461. return -ENODEV;
  462. #else
  463. int phy_addr = -1;
  464. #ifdef CONFIG_PHY_ADDR
  465. phy_addr = CONFIG_PHY_ADDR;
  466. #endif
  467. phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface);
  468. if (!phydev)
  469. return -ENODEV;
  470. #endif
  471. phydev->supported &= PHY_GBIT_FEATURES;
  472. if (priv->max_speed) {
  473. ret = phy_set_supported(phydev, priv->max_speed);
  474. if (ret)
  475. return ret;
  476. }
  477. phydev->advertising = phydev->supported;
  478. priv->phydev = phydev;
  479. phy_config(phydev);
  480. return 0;
  481. }
  482. #ifndef CONFIG_DM_ETH
  483. static int dw_eth_init(struct eth_device *dev, struct bd_info *bis)
  484. {
  485. int ret;
  486. ret = designware_eth_init(dev->priv, dev->enetaddr);
  487. if (!ret)
  488. ret = designware_eth_enable(dev->priv);
  489. return ret;
  490. }
  491. static int dw_eth_send(struct eth_device *dev, void *packet, int length)
  492. {
  493. return _dw_eth_send(dev->priv, packet, length);
  494. }
  495. static int dw_eth_recv(struct eth_device *dev)
  496. {
  497. uchar *packet;
  498. int length;
  499. length = _dw_eth_recv(dev->priv, &packet);
  500. if (length == -EAGAIN)
  501. return 0;
  502. net_process_received_packet(packet, length);
  503. _dw_free_pkt(dev->priv);
  504. return 0;
  505. }
  506. static void dw_eth_halt(struct eth_device *dev)
  507. {
  508. return _dw_eth_halt(dev->priv);
  509. }
  510. static int dw_write_hwaddr(struct eth_device *dev)
  511. {
  512. return _dw_write_hwaddr(dev->priv, dev->enetaddr);
  513. }
  514. int designware_initialize(ulong base_addr, u32 interface)
  515. {
  516. struct eth_device *dev;
  517. struct dw_eth_dev *priv;
  518. dev = (struct eth_device *) malloc(sizeof(struct eth_device));
  519. if (!dev)
  520. return -ENOMEM;
  521. /*
  522. * Since the priv structure contains the descriptors which need a strict
  523. * buswidth alignment, memalign is used to allocate memory
  524. */
  525. priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
  526. sizeof(struct dw_eth_dev));
  527. if (!priv) {
  528. free(dev);
  529. return -ENOMEM;
  530. }
  531. if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
  532. printf("designware: buffers are outside DMA memory\n");
  533. return -EINVAL;
  534. }
  535. memset(dev, 0, sizeof(struct eth_device));
  536. memset(priv, 0, sizeof(struct dw_eth_dev));
  537. sprintf(dev->name, "dwmac.%lx", base_addr);
  538. dev->iobase = (int)base_addr;
  539. dev->priv = priv;
  540. priv->dev = dev;
  541. priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
  542. priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
  543. DW_DMA_BASE_OFFSET);
  544. dev->init = dw_eth_init;
  545. dev->send = dw_eth_send;
  546. dev->recv = dw_eth_recv;
  547. dev->halt = dw_eth_halt;
  548. dev->write_hwaddr = dw_write_hwaddr;
  549. eth_register(dev);
  550. priv->interface = interface;
  551. dw_mdio_init(dev->name, priv->mac_regs_p);
  552. priv->bus = miiphy_get_dev_by_name(dev->name);
  553. return dw_phy_init(priv, dev);
  554. }
  555. #endif
  556. #ifdef CONFIG_DM_ETH
  557. static int designware_eth_start(struct udevice *dev)
  558. {
  559. struct eth_pdata *pdata = dev_get_plat(dev);
  560. struct dw_eth_dev *priv = dev_get_priv(dev);
  561. int ret;
  562. ret = designware_eth_init(priv, pdata->enetaddr);
  563. if (ret)
  564. return ret;
  565. ret = designware_eth_enable(priv);
  566. if (ret)
  567. return ret;
  568. return 0;
  569. }
  570. int designware_eth_send(struct udevice *dev, void *packet, int length)
  571. {
  572. struct dw_eth_dev *priv = dev_get_priv(dev);
  573. return _dw_eth_send(priv, packet, length);
  574. }
  575. int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  576. {
  577. struct dw_eth_dev *priv = dev_get_priv(dev);
  578. return _dw_eth_recv(priv, packetp);
  579. }
  580. int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
  581. {
  582. struct dw_eth_dev *priv = dev_get_priv(dev);
  583. return _dw_free_pkt(priv);
  584. }
  585. void designware_eth_stop(struct udevice *dev)
  586. {
  587. struct dw_eth_dev *priv = dev_get_priv(dev);
  588. return _dw_eth_halt(priv);
  589. }
  590. int designware_eth_write_hwaddr(struct udevice *dev)
  591. {
  592. struct eth_pdata *pdata = dev_get_plat(dev);
  593. struct dw_eth_dev *priv = dev_get_priv(dev);
  594. return _dw_write_hwaddr(priv, pdata->enetaddr);
  595. }
  596. static int designware_eth_bind(struct udevice *dev)
  597. {
  598. if (IS_ENABLED(CONFIG_PCI)) {
  599. static int num_cards;
  600. char name[20];
  601. /* Create a unique device name for PCI type devices */
  602. if (device_is_on_pci_bus(dev)) {
  603. sprintf(name, "eth_designware#%u", num_cards++);
  604. device_set_name(dev, name);
  605. }
  606. }
  607. return 0;
  608. }
  609. int designware_eth_probe(struct udevice *dev)
  610. {
  611. struct eth_pdata *pdata = dev_get_plat(dev);
  612. struct dw_eth_dev *priv = dev_get_priv(dev);
  613. u32 iobase = pdata->iobase;
  614. ulong ioaddr;
  615. int ret, err;
  616. struct reset_ctl_bulk reset_bulk;
  617. #ifdef CONFIG_CLK
  618. int i, clock_nb;
  619. priv->clock_count = 0;
  620. clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells",
  621. 0);
  622. if (clock_nb > 0) {
  623. priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
  624. GFP_KERNEL);
  625. if (!priv->clocks)
  626. return -ENOMEM;
  627. for (i = 0; i < clock_nb; i++) {
  628. err = clk_get_by_index(dev, i, &priv->clocks[i]);
  629. if (err < 0)
  630. break;
  631. err = clk_enable(&priv->clocks[i]);
  632. if (err && err != -ENOSYS && err != -ENOTSUPP) {
  633. pr_err("failed to enable clock %d\n", i);
  634. clk_free(&priv->clocks[i]);
  635. goto clk_err;
  636. }
  637. priv->clock_count++;
  638. }
  639. } else if (clock_nb != -ENOENT) {
  640. pr_err("failed to get clock phandle(%d)\n", clock_nb);
  641. return clock_nb;
  642. }
  643. #endif
  644. #if defined(CONFIG_DM_REGULATOR)
  645. struct udevice *phy_supply;
  646. ret = device_get_supply_regulator(dev, "phy-supply",
  647. &phy_supply);
  648. if (ret) {
  649. debug("%s: No phy supply\n", dev->name);
  650. } else {
  651. ret = regulator_set_enable(phy_supply, true);
  652. if (ret) {
  653. puts("Error enabling phy supply\n");
  654. return ret;
  655. }
  656. }
  657. #endif
  658. ret = reset_get_bulk(dev, &reset_bulk);
  659. if (ret)
  660. dev_warn(dev, "Can't get reset: %d\n", ret);
  661. else
  662. reset_deassert_bulk(&reset_bulk);
  663. /*
  664. * If we are on PCI bus, either directly attached to a PCI root port,
  665. * or via a PCI bridge, fill in plat before we probe the hardware.
  666. */
  667. if (IS_ENABLED(CONFIG_PCI) && device_is_on_pci_bus(dev)) {
  668. dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
  669. iobase &= PCI_BASE_ADDRESS_MEM_MASK;
  670. iobase = dm_pci_mem_to_phys(dev, iobase);
  671. pdata->iobase = iobase;
  672. pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
  673. }
  674. debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
  675. ioaddr = iobase;
  676. priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
  677. priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
  678. priv->interface = pdata->phy_interface;
  679. priv->max_speed = pdata->max_speed;
  680. #if IS_ENABLED(CONFIG_DM_MDIO)
  681. ret = dw_dm_mdio_init(dev->name, dev);
  682. #else
  683. ret = dw_mdio_init(dev->name, dev);
  684. #endif
  685. if (ret) {
  686. err = ret;
  687. goto mdio_err;
  688. }
  689. priv->bus = miiphy_get_dev_by_name(dev->name);
  690. ret = dw_phy_init(priv, dev);
  691. debug("%s, ret=%d\n", __func__, ret);
  692. if (!ret)
  693. return 0;
  694. /* continue here for cleanup if no PHY found */
  695. err = ret;
  696. mdio_unregister(priv->bus);
  697. mdio_free(priv->bus);
  698. mdio_err:
  699. #ifdef CONFIG_CLK
  700. clk_err:
  701. ret = clk_release_all(priv->clocks, priv->clock_count);
  702. if (ret)
  703. pr_err("failed to disable all clocks\n");
  704. #endif
  705. return err;
  706. }
  707. static int designware_eth_remove(struct udevice *dev)
  708. {
  709. struct dw_eth_dev *priv = dev_get_priv(dev);
  710. free(priv->phydev);
  711. mdio_unregister(priv->bus);
  712. mdio_free(priv->bus);
  713. #ifdef CONFIG_CLK
  714. return clk_release_all(priv->clocks, priv->clock_count);
  715. #else
  716. return 0;
  717. #endif
  718. }
  719. const struct eth_ops designware_eth_ops = {
  720. .start = designware_eth_start,
  721. .send = designware_eth_send,
  722. .recv = designware_eth_recv,
  723. .free_pkt = designware_eth_free_pkt,
  724. .stop = designware_eth_stop,
  725. .write_hwaddr = designware_eth_write_hwaddr,
  726. };
  727. int designware_eth_of_to_plat(struct udevice *dev)
  728. {
  729. struct dw_eth_pdata *dw_pdata = dev_get_plat(dev);
  730. #if CONFIG_IS_ENABLED(DM_GPIO)
  731. struct dw_eth_dev *priv = dev_get_priv(dev);
  732. #endif
  733. struct eth_pdata *pdata = &dw_pdata->eth_pdata;
  734. const char *phy_mode;
  735. #if CONFIG_IS_ENABLED(DM_GPIO)
  736. int reset_flags = GPIOD_IS_OUT;
  737. #endif
  738. int ret = 0;
  739. pdata->iobase = dev_read_addr(dev);
  740. pdata->phy_interface = -1;
  741. phy_mode = dev_read_string(dev, "phy-mode");
  742. if (phy_mode)
  743. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  744. if (pdata->phy_interface == -1) {
  745. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  746. return -EINVAL;
  747. }
  748. pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
  749. #if CONFIG_IS_ENABLED(DM_GPIO)
  750. if (dev_read_bool(dev, "snps,reset-active-low"))
  751. reset_flags |= GPIOD_ACTIVE_LOW;
  752. ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
  753. &priv->reset_gpio, reset_flags);
  754. if (ret == 0) {
  755. ret = dev_read_u32_array(dev, "snps,reset-delays-us",
  756. dw_pdata->reset_delays, 3);
  757. } else if (ret == -ENOENT) {
  758. ret = 0;
  759. }
  760. #endif
  761. return ret;
  762. }
  763. static const struct udevice_id designware_eth_ids[] = {
  764. { .compatible = "allwinner,sun7i-a20-gmac" },
  765. { .compatible = "amlogic,meson6-dwmac" },
  766. { .compatible = "st,stm32-dwmac" },
  767. { .compatible = "snps,arc-dwmac-3.70a" },
  768. { }
  769. };
  770. U_BOOT_DRIVER(eth_designware) = {
  771. .name = "eth_designware",
  772. .id = UCLASS_ETH,
  773. .of_match = designware_eth_ids,
  774. .of_to_plat = designware_eth_of_to_plat,
  775. .bind = designware_eth_bind,
  776. .probe = designware_eth_probe,
  777. .remove = designware_eth_remove,
  778. .ops = &designware_eth_ops,
  779. .priv_auto = sizeof(struct dw_eth_dev),
  780. .plat_auto = sizeof(struct dw_eth_pdata),
  781. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  782. };
  783. static struct pci_device_id supported[] = {
  784. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
  785. { }
  786. };
  787. U_BOOT_PCI_DEVICE(eth_designware, supported);
  788. #endif