cs8900.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. #ifndef CS8900_H
  3. #define CS8900_H
  4. /*
  5. * Cirrus Logic CS8900A Ethernet
  6. *
  7. * (C) 2009 Ben Warren , biggerbadderben@gmail.com
  8. * Converted to use CONFIG_NET_MULTI API
  9. *
  10. * (C) Copyright 2002
  11. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  12. * Marius Groeger <mgroeger@sysgo.de>
  13. *
  14. * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
  15. *
  16. * This program is loaded into SRAM in bootstrap mode, where it waits
  17. * for commands on UART1 to read and write memory, jump to code etc.
  18. * A design goal for this program is to be entirely independent of the
  19. * target board. Anything with a CL-PS7111 or EP7211 should be able to run
  20. * this code in bootstrap mode. All the board specifics can be handled on
  21. * the host.
  22. */
  23. #include <asm/types.h>
  24. #include <config.h>
  25. #define CS8900_DRIVERNAME "CS8900"
  26. /* although the registers are 16 bit, they are 32-bit aligned on the
  27. EDB7111. so we have to read them as 32-bit registers and ignore the
  28. upper 16-bits. i'm not sure if this holds for the EDB7211. */
  29. #ifdef CONFIG_CS8900_BUS16
  30. /* 16 bit aligned registers, 16 bit wide */
  31. #define CS8900_REG u16
  32. #elif defined(CONFIG_CS8900_BUS32)
  33. /* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */
  34. #define CS8900_REG u32
  35. #else
  36. #error unknown bussize ...
  37. #endif
  38. struct cs8900_regs {
  39. CS8900_REG rtdata;
  40. CS8900_REG pad0;
  41. CS8900_REG txcmd;
  42. CS8900_REG txlen;
  43. CS8900_REG isq;
  44. CS8900_REG pptr;
  45. CS8900_REG pdata;
  46. };
  47. struct cs8900_priv {
  48. struct cs8900_regs *regs;
  49. };
  50. #define ISQ_RxEvent 0x04
  51. #define ISQ_TxEvent 0x08
  52. #define ISQ_BufEvent 0x0C
  53. #define ISQ_RxMissEvent 0x10
  54. #define ISQ_TxColEvent 0x12
  55. #define ISQ_EventMask 0x3F
  56. /* packet page register offsets */
  57. /* bus interface registers */
  58. #define PP_ChipID 0x0000 /* Chip identifier - must be 0x630E */
  59. #define PP_ChipRev 0x0002 /* Chip revision, model codes */
  60. #define PP_IntReg 0x0022 /* Interrupt configuration */
  61. #define PP_IntReg_IRQ0 0x0000 /* Use INTR0 pin */
  62. #define PP_IntReg_IRQ1 0x0001 /* Use INTR1 pin */
  63. #define PP_IntReg_IRQ2 0x0002 /* Use INTR2 pin */
  64. #define PP_IntReg_IRQ3 0x0003 /* Use INTR3 pin */
  65. /* status and control registers */
  66. #define PP_RxCFG 0x0102 /* Receiver configuration */
  67. #define PP_RxCFG_Skip1 0x0040 /* Skip (i.e. discard) current frame */
  68. #define PP_RxCFG_Stream 0x0080 /* Enable streaming mode */
  69. #define PP_RxCFG_RxOK 0x0100 /* RxOK interrupt enable */
  70. #define PP_RxCFG_RxDMAonly 0x0200 /* Use RxDMA for all frames */
  71. #define PP_RxCFG_AutoRxDMA 0x0400 /* Select RxDMA automatically */
  72. #define PP_RxCFG_BufferCRC 0x0800 /* Include CRC characters in frame */
  73. #define PP_RxCFG_CRC 0x1000 /* Enable interrupt on CRC error */
  74. #define PP_RxCFG_RUNT 0x2000 /* Enable interrupt on RUNT frames */
  75. #define PP_RxCFG_EXTRA 0x4000 /* Enable interrupt on frames with extra data */
  76. #define PP_RxCTL 0x0104 /* Receiver control */
  77. #define PP_RxCTL_IAHash 0x0040 /* Accept frames that match hash */
  78. #define PP_RxCTL_Promiscuous 0x0080 /* Accept any frame */
  79. #define PP_RxCTL_RxOK 0x0100 /* Accept well formed frames */
  80. #define PP_RxCTL_Multicast 0x0200 /* Accept multicast frames */
  81. #define PP_RxCTL_IA 0x0400 /* Accept frame that matches IA */
  82. #define PP_RxCTL_Broadcast 0x0800 /* Accept broadcast frames */
  83. #define PP_RxCTL_CRC 0x1000 /* Accept frames with bad CRC */
  84. #define PP_RxCTL_RUNT 0x2000 /* Accept runt frames */
  85. #define PP_RxCTL_EXTRA 0x4000 /* Accept frames that are too long */
  86. #define PP_TxCFG 0x0106 /* Transmit configuration */
  87. #define PP_TxCFG_CRS 0x0040 /* Enable interrupt on loss of carrier */
  88. #define PP_TxCFG_SQE 0x0080 /* Enable interrupt on Signal Quality Error */
  89. #define PP_TxCFG_TxOK 0x0100 /* Enable interrupt on successful xmits */
  90. #define PP_TxCFG_Late 0x0200 /* Enable interrupt on "out of window" */
  91. #define PP_TxCFG_Jabber 0x0400 /* Enable interrupt on jabber detect */
  92. #define PP_TxCFG_Collision 0x0800 /* Enable interrupt if collision */
  93. #define PP_TxCFG_16Collisions 0x8000 /* Enable interrupt if > 16 collisions */
  94. #define PP_TxCmd 0x0108 /* Transmit command status */
  95. #define PP_TxCmd_TxStart_5 0x0000 /* Start after 5 bytes in buffer */
  96. #define PP_TxCmd_TxStart_381 0x0040 /* Start after 381 bytes in buffer */
  97. #define PP_TxCmd_TxStart_1021 0x0080 /* Start after 1021 bytes in buffer */
  98. #define PP_TxCmd_TxStart_Full 0x00C0 /* Start after all bytes loaded */
  99. #define PP_TxCmd_Force 0x0100 /* Discard any pending packets */
  100. #define PP_TxCmd_OneCollision 0x0200 /* Abort after a single collision */
  101. #define PP_TxCmd_NoCRC 0x1000 /* Do not add CRC */
  102. #define PP_TxCmd_NoPad 0x2000 /* Do not pad short packets */
  103. #define PP_BufCFG 0x010A /* Buffer configuration */
  104. #define PP_BufCFG_SWI 0x0040 /* Force interrupt via software */
  105. #define PP_BufCFG_RxDMA 0x0080 /* Enable interrupt on Rx DMA */
  106. #define PP_BufCFG_TxRDY 0x0100 /* Enable interrupt when ready for Tx */
  107. #define PP_BufCFG_TxUE 0x0200 /* Enable interrupt in Tx underrun */
  108. #define PP_BufCFG_RxMiss 0x0400 /* Enable interrupt on missed Rx packets */
  109. #define PP_BufCFG_Rx128 0x0800 /* Enable Rx interrupt after 128 bytes */
  110. #define PP_BufCFG_TxCol 0x1000 /* Enable int on Tx collision ctr overflow */
  111. #define PP_BufCFG_Miss 0x2000 /* Enable int on Rx miss ctr overflow */
  112. #define PP_BufCFG_RxDest 0x8000 /* Enable int on Rx dest addr match */
  113. #define PP_LineCTL 0x0112 /* Line control */
  114. #define PP_LineCTL_Rx 0x0040 /* Enable receiver */
  115. #define PP_LineCTL_Tx 0x0080 /* Enable transmitter */
  116. #define PP_LineCTL_AUIonly 0x0100 /* AUI interface only */
  117. #define PP_LineCTL_AutoAUI10BT 0x0200 /* Autodetect AUI or 10BaseT interface */
  118. #define PP_LineCTL_ModBackoffE 0x0800 /* Enable modified backoff algorithm */
  119. #define PP_LineCTL_PolarityDis 0x1000 /* Disable Rx polarity autodetect */
  120. #define PP_LineCTL_2partDefDis 0x2000 /* Disable two-part defferal */
  121. #define PP_LineCTL_LoRxSquelch 0x4000 /* Reduce receiver squelch threshold */
  122. #define PP_SelfCTL 0x0114 /* Chip self control */
  123. #define PP_SelfCTL_Reset 0x0040 /* Self-clearing reset */
  124. #define PP_SelfCTL_SWSuspend 0x0100 /* Initiate suspend mode */
  125. #define PP_SelfCTL_HWSleepE 0x0200 /* Enable SLEEP input */
  126. #define PP_SelfCTL_HWStandbyE 0x0400 /* Enable standby mode */
  127. #define PP_SelfCTL_HC0E 0x1000 /* use HCB0 for LINK LED */
  128. #define PP_SelfCTL_HC1E 0x2000 /* use HCB1 for BSTATUS LED */
  129. #define PP_SelfCTL_HCB0 0x4000 /* control LINK LED if HC0E set */
  130. #define PP_SelfCTL_HCB1 0x8000 /* control BSTATUS LED if HC1E set */
  131. #define PP_BusCTL 0x0116 /* Bus control */
  132. #define PP_BusCTL_ResetRxDMA 0x0040 /* Reset RxDMA pointer */
  133. #define PP_BusCTL_DMAextend 0x0100 /* Extend DMA cycle */
  134. #define PP_BusCTL_UseSA 0x0200 /* Assert MEMCS16 on address decode */
  135. #define PP_BusCTL_MemoryE 0x0400 /* Enable memory mode */
  136. #define PP_BusCTL_DMAburst 0x0800 /* Limit DMA access burst */
  137. #define PP_BusCTL_IOCHRDYE 0x1000 /* Set IOCHRDY high impedence */
  138. #define PP_BusCTL_RxDMAsize 0x2000 /* Set DMA buffer size 64KB */
  139. #define PP_BusCTL_EnableIRQ 0x8000 /* Generate interrupt on interrupt event */
  140. #define PP_TestCTL 0x0118 /* Test control */
  141. #define PP_TestCTL_DisableLT 0x0080 /* Disable link status */
  142. #define PP_TestCTL_ENDECloop 0x0200 /* Internal loopback */
  143. #define PP_TestCTL_AUIloop 0x0400 /* AUI loopback */
  144. #define PP_TestCTL_DisBackoff 0x0800 /* Disable backoff algorithm */
  145. #define PP_TestCTL_FDX 0x4000 /* Enable full duplex mode */
  146. #define PP_ISQ 0x0120 /* Interrupt Status Queue */
  147. #define PP_RER 0x0124 /* Receive event */
  148. #define PP_RER_IAHash 0x0040 /* Frame hash match */
  149. #define PP_RER_Dribble 0x0080 /* Frame had 1-7 extra bits after last byte */
  150. #define PP_RER_RxOK 0x0100 /* Frame received with no errors */
  151. #define PP_RER_Hashed 0x0200 /* Frame address hashed OK */
  152. #define PP_RER_IA 0x0400 /* Frame address matched IA */
  153. #define PP_RER_Broadcast 0x0800 /* Broadcast frame */
  154. #define PP_RER_CRC 0x1000 /* Frame had CRC error */
  155. #define PP_RER_RUNT 0x2000 /* Runt frame */
  156. #define PP_RER_EXTRA 0x4000 /* Frame was too long */
  157. #define PP_TER 0x0128 /* Transmit event */
  158. #define PP_TER_CRS 0x0040 /* Carrier lost */
  159. #define PP_TER_SQE 0x0080 /* Signal Quality Error */
  160. #define PP_TER_TxOK 0x0100 /* Packet sent without error */
  161. #define PP_TER_Late 0x0200 /* Out of window */
  162. #define PP_TER_Jabber 0x0400 /* Stuck transmit? */
  163. #define PP_TER_NumCollisions 0x7800 /* Number of collisions */
  164. #define PP_TER_16Collisions 0x8000 /* > 16 collisions */
  165. #define PP_BER 0x012C /* Buffer event */
  166. #define PP_BER_SWint 0x0040 /* Software interrupt */
  167. #define PP_BER_RxDMAFrame 0x0080 /* Received framed DMAed */
  168. #define PP_BER_Rdy4Tx 0x0100 /* Ready for transmission */
  169. #define PP_BER_TxUnderrun 0x0200 /* Transmit underrun */
  170. #define PP_BER_RxMiss 0x0400 /* Received frame missed */
  171. #define PP_BER_Rx128 0x0800 /* 128 bytes received */
  172. #define PP_BER_RxDest 0x8000 /* Received framed passed address filter */
  173. #define PP_RxMiss 0x0130 /* Receiver miss counter */
  174. #define PP_TxCol 0x0132 /* Transmit collision counter */
  175. #define PP_LineSTAT 0x0134 /* Line status */
  176. #define PP_LineSTAT_LinkOK 0x0080 /* Line is connected and working */
  177. #define PP_LineSTAT_AUI 0x0100 /* Connected via AUI */
  178. #define PP_LineSTAT_10BT 0x0200 /* Connected via twisted pair */
  179. #define PP_LineSTAT_Polarity 0x1000 /* Line polarity OK (10BT only) */
  180. #define PP_LineSTAT_CRS 0x4000 /* Frame being received */
  181. #define PP_SelfSTAT 0x0136 /* Chip self status */
  182. #define PP_SelfSTAT_33VActive 0x0040 /* supply voltage is 3.3V */
  183. #define PP_SelfSTAT_InitD 0x0080 /* Chip initialization complete */
  184. #define PP_SelfSTAT_SIBSY 0x0100 /* EEPROM is busy */
  185. #define PP_SelfSTAT_EEPROM 0x0200 /* EEPROM present */
  186. #define PP_SelfSTAT_EEPROM_OK 0x0400 /* EEPROM checks out */
  187. #define PP_SelfSTAT_ELPresent 0x0800 /* External address latch logic available */
  188. #define PP_SelfSTAT_EEsize 0x1000 /* Size of EEPROM */
  189. #define PP_BusSTAT 0x0138 /* Bus status */
  190. #define PP_BusSTAT_TxBid 0x0080 /* Tx error */
  191. #define PP_BusSTAT_TxRDY 0x0100 /* Ready for Tx data */
  192. #define PP_TDR 0x013C /* AUI Time Domain Reflectometer */
  193. /* initiate transmit registers */
  194. #define PP_TxCommand 0x0144 /* Tx Command */
  195. #define PP_TxLength 0x0146 /* Tx Length */
  196. /* address filter registers */
  197. #define PP_LAF 0x0150 /* Logical address filter (6 bytes) */
  198. #define PP_IA 0x0158 /* Individual address (MAC) */
  199. /* EEPROM Kram */
  200. #define SI_BUSY 0x0100
  201. #define PP_EECMD 0x0040 /* NVR Interface Command register */
  202. #define PP_EEData 0x0042 /* NVR Interface Data Register */
  203. #define EEPROM_WRITE_EN 0x00F0
  204. #define EEPROM_WRITE_DIS 0x0000
  205. #define EEPROM_WRITE_CMD 0x0100
  206. #define EEPROM_READ_CMD 0x0200
  207. #define EEPROM_ERASE_CMD 0x0300
  208. /* Exported functions */
  209. int cs8900_e2prom_read(struct eth_device *dev, uchar, ushort *);
  210. int cs8900_e2prom_write(struct eth_device *dev, uchar, ushort);
  211. #endif /* CS8900_H */