cortina_ni.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2020 Cortina Access Inc.
  4. * Author: Aaron Tseng <aaron.tseng@cortina-access.com>
  5. *
  6. * Ethernet MAC Driver for all supported CAxxxx SoCs
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <malloc.h>
  11. #include <net.h>
  12. #include <miiphy.h>
  13. #include <env.h>
  14. #include <linux/delay.h>
  15. #include <linux/bitops.h>
  16. #include <u-boot/crc.h>
  17. #include <led.h>
  18. #include "cortina_ni.h"
  19. #define HEADER_A_SIZE 8
  20. enum ca_led_state_t {
  21. CA_LED_OFF = 0,
  22. CA_LED_ON = 1,
  23. };
  24. enum ca_port_t {
  25. NI_PORT_0 = 0,
  26. NI_PORT_1,
  27. NI_PORT_2,
  28. NI_PORT_3,
  29. NI_PORT_4,
  30. NI_PORT_5,
  31. NI_PORT_MAX,
  32. };
  33. static struct udevice *curr_dev;
  34. static u32 *ca_rdwrptr_adv_one(u32 *x, unsigned long base, unsigned long max)
  35. {
  36. if (x + 1 >= (u32 *)max)
  37. return (u32 *)base;
  38. else
  39. return (x + 1);
  40. }
  41. static void ca_reg_read(void *reg, u64 base, u64 offset)
  42. {
  43. u32 *val = (u32 *)reg;
  44. *val = readl(KSEG1_ATU_XLAT(base + offset));
  45. }
  46. static void ca_reg_write(void *reg, u64 base, u64 offset)
  47. {
  48. u32 val = *(u32 *)reg;
  49. writel(val, KSEG1_ATU_XLAT(base + offset));
  50. }
  51. static int ca_mdio_write_rgmii(u32 addr, u32 offset, u16 data)
  52. {
  53. /* up to 10000 cycles*/
  54. u32 loop_wait = __MDIO_ACCESS_TIMEOUT;
  55. struct PER_MDIO_ADDR_t mdio_addr;
  56. struct PER_MDIO_CTRL_t mdio_ctrl;
  57. struct cortina_ni_priv *priv = dev_get_priv(curr_dev);
  58. memset(&mdio_addr, 0, sizeof(mdio_addr));
  59. mdio_addr.mdio_addr = addr;
  60. mdio_addr.mdio_offset = offset;
  61. mdio_addr.mdio_rd_wr = __MDIO_WR_FLAG;
  62. ca_reg_write(&mdio_addr, (u64)priv->per_mdio_base_addr,
  63. PER_MDIO_ADDR_OFFSET);
  64. ca_reg_write(&data, (u64)priv->per_mdio_base_addr,
  65. PER_MDIO_WRDATA_OFFSET);
  66. memset(&mdio_ctrl, 0, sizeof(mdio_ctrl));
  67. mdio_ctrl.mdiostart = 1;
  68. ca_reg_write(&mdio_ctrl, (u64)priv->per_mdio_base_addr,
  69. PER_MDIO_CTRL_OFFSET);
  70. debug("%s: phy_addr=%d, offset=%d, data=0x%x\n",
  71. __func__, addr, offset, data);
  72. do {
  73. ca_reg_read(&mdio_ctrl, (u64)priv->per_mdio_base_addr,
  74. PER_MDIO_CTRL_OFFSET);
  75. if (mdio_ctrl.mdiodone) {
  76. ca_reg_write(&mdio_ctrl, (u64)priv->per_mdio_base_addr,
  77. PER_MDIO_CTRL_OFFSET);
  78. return 0;
  79. }
  80. } while (--loop_wait);
  81. printf("CA NI %s: PHY write timeout!!!\n", __func__);
  82. return -ETIMEDOUT;
  83. }
  84. int ca_mdio_write(u32 addr, u32 offset, u16 data)
  85. {
  86. u32 reg_addr, reg_val;
  87. struct NI_MDIO_OPER_T mdio_oper;
  88. /* support range: 1~31*/
  89. if (addr < CA_MDIO_ADDR_MIN || addr > CA_MDIO_ADDR_MAX)
  90. return -EINVAL;
  91. /* the phy addr 5 is connect to RGMII */
  92. if (addr >= 5)
  93. return ca_mdio_write_rgmii(addr, offset, data);
  94. memset(&mdio_oper, 0, sizeof(mdio_oper));
  95. mdio_oper.reg_off = offset;
  96. mdio_oper.phy_addr = addr;
  97. mdio_oper.reg_base = CA_NI_MDIO_REG_BASE;
  98. reg_val = data;
  99. memcpy(&reg_addr, &mdio_oper, sizeof(reg_addr));
  100. ca_reg_write(&reg_val, (u64)reg_addr, 0);
  101. return 0;
  102. }
  103. static int ca_mdio_read_rgmii(u32 addr, u32 offset, u16 *data)
  104. {
  105. u32 loop_wait = __MDIO_ACCESS_TIMEOUT;
  106. struct PER_MDIO_ADDR_t mdio_addr;
  107. struct PER_MDIO_CTRL_t mdio_ctrl;
  108. struct PER_MDIO_RDDATA_t read_data;
  109. struct cortina_ni_priv *priv = dev_get_priv(curr_dev);
  110. memset(&mdio_addr, 0, sizeof(mdio_addr));
  111. mdio_addr.mdio_addr = addr;
  112. mdio_addr.mdio_offset = offset;
  113. mdio_addr.mdio_rd_wr = __MDIO_RD_FLAG;
  114. ca_reg_write(&mdio_addr, (u64)priv->per_mdio_base_addr,
  115. PER_MDIO_ADDR_OFFSET);
  116. memset(&mdio_ctrl, 0, sizeof(mdio_ctrl));
  117. mdio_ctrl.mdiostart = 1;
  118. ca_reg_write(&mdio_ctrl, (u64)priv->per_mdio_base_addr,
  119. PER_MDIO_CTRL_OFFSET);
  120. do {
  121. ca_reg_read(&mdio_ctrl, (u64)priv->per_mdio_base_addr,
  122. PER_MDIO_CTRL_OFFSET);
  123. if (mdio_ctrl.mdiodone) {
  124. ca_reg_write(&mdio_ctrl, (u64)priv->per_mdio_base_addr,
  125. PER_MDIO_CTRL_OFFSET);
  126. ca_reg_read(&read_data, (u64)priv->per_mdio_base_addr,
  127. PER_MDIO_RDDATA_OFFSET);
  128. *data = read_data.mdio_rddata;
  129. return 0;
  130. }
  131. } while (--loop_wait);
  132. printf("CA NI %s: TIMEOUT!!\n", __func__);
  133. return -ETIMEDOUT;
  134. }
  135. int ca_mdio_read(u32 addr, u32 offset, u16 *data)
  136. {
  137. u32 reg_addr, reg_val;
  138. struct NI_MDIO_OPER_T mdio_oper;
  139. if (!data)
  140. return -EINVAL;
  141. /* support range: 1~31*/
  142. if (addr < CA_MDIO_ADDR_MIN || addr > CA_MDIO_ADDR_MAX)
  143. return -EINVAL;
  144. /* the phy addr 5 is connect to RGMII */
  145. if (addr >= 5)
  146. return ca_mdio_read_rgmii(addr, offset, data);
  147. memset(&mdio_oper, 0, sizeof(mdio_oper));
  148. mdio_oper.reg_off = offset;
  149. mdio_oper.phy_addr = addr;
  150. mdio_oper.reg_base = CA_NI_MDIO_REG_BASE;
  151. reg_val = *data;
  152. memcpy(&reg_addr, &mdio_oper, sizeof(reg_addr));
  153. ca_reg_read(&reg_val, (u64)reg_addr, 0);
  154. *data = reg_val;
  155. return 0;
  156. }
  157. int ca_miiphy_read(const char *devname, u8 addr, u8 reg, u16 *value)
  158. {
  159. return ca_mdio_read(addr, reg, value);
  160. }
  161. int ca_miiphy_write(const char *devname, u8 addr, u8 reg, u16 value)
  162. {
  163. return ca_mdio_write(addr, reg, value);
  164. }
  165. static int cortina_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  166. {
  167. u16 data;
  168. ca_mdio_read(addr, reg, &data);
  169. return data;
  170. }
  171. static int cortina_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  172. u16 val)
  173. {
  174. return ca_mdio_write(addr, reg, val);
  175. }
  176. static void ca_ni_setup_mac_addr(void)
  177. {
  178. u8 mac[6];
  179. struct NI_HV_GLB_MAC_ADDR_CFG0_t mac_addr_cfg0;
  180. struct NI_HV_GLB_MAC_ADDR_CFG1_t mac_addr_cfg1;
  181. struct NI_HV_PT_PORT_STATIC_CFG_t port_static_cfg;
  182. struct NI_HV_XRAM_CPUXRAM_CFG_t cpuxram_cfg;
  183. struct cortina_ni_priv *priv = dev_get_priv(curr_dev);
  184. /* parsing ethaddr and set to NI registers. */
  185. if (eth_env_get_enetaddr("ethaddr", mac)) {
  186. /* The complete MAC address consists of
  187. * {MAC_ADDR0_mac_addr0[0-3], MAC_ADDR1_mac_addr1[4],
  188. * PT_PORT_STATIC_CFG_mac_addr6[5]}.
  189. */
  190. mac_addr_cfg0.mac_addr0 = (mac[0] << 24) + (mac[1] << 16) +
  191. (mac[2] << 8) + mac[3];
  192. ca_reg_write(&mac_addr_cfg0, (u64)priv->ni_hv_base_addr,
  193. NI_HV_GLB_MAC_ADDR_CFG0_OFFSET);
  194. memset(&mac_addr_cfg1, 0, sizeof(mac_addr_cfg1));
  195. mac_addr_cfg1.mac_addr1 = mac[4];
  196. ca_reg_write(&mac_addr_cfg1, (u64)priv->ni_hv_base_addr,
  197. NI_HV_GLB_MAC_ADDR_CFG1_OFFSET);
  198. ca_reg_read(&port_static_cfg, (u64)priv->ni_hv_base_addr,
  199. NI_HV_PT_PORT_STATIC_CFG_OFFSET +
  200. (APB0_NI_HV_PT_STRIDE * priv->active_port));
  201. port_static_cfg.mac_addr6 = mac[5];
  202. ca_reg_write(&port_static_cfg, (u64)priv->ni_hv_base_addr,
  203. NI_HV_PT_PORT_STATIC_CFG_OFFSET +
  204. (APB0_NI_HV_PT_STRIDE * priv->active_port));
  205. /* received only Broadcast and Address matched packets */
  206. ca_reg_read(&cpuxram_cfg, (u64)priv->ni_hv_base_addr,
  207. NI_HV_XRAM_CPUXRAM_CFG_OFFSET);
  208. cpuxram_cfg.xram_mgmt_promisc_mode = 0;
  209. cpuxram_cfg.rx_0_cpu_pkt_dis = 0;
  210. cpuxram_cfg.tx_0_cpu_pkt_dis = 0;
  211. ca_reg_write(&cpuxram_cfg, (u64)priv->ni_hv_base_addr,
  212. NI_HV_XRAM_CPUXRAM_CFG_OFFSET);
  213. } else {
  214. /* received all packets(promiscuous mode) */
  215. ca_reg_read(&cpuxram_cfg, (u64)priv->ni_hv_base_addr,
  216. NI_HV_XRAM_CPUXRAM_CFG_OFFSET);
  217. cpuxram_cfg.xram_mgmt_promisc_mode = 3;
  218. cpuxram_cfg.rx_0_cpu_pkt_dis = 0;
  219. cpuxram_cfg.tx_0_cpu_pkt_dis = 0;
  220. ca_reg_write(&cpuxram_cfg, (u64)priv->ni_hv_base_addr,
  221. NI_HV_XRAM_CPUXRAM_CFG_OFFSET);
  222. }
  223. }
  224. static void ca_ni_enable_tx_rx(void)
  225. {
  226. struct NI_HV_PT_RXMAC_CFG_t rxmac_cfg;
  227. struct NI_HV_PT_TXMAC_CFG_t txmac_cfg;
  228. struct cortina_ni_priv *priv = dev_get_priv(curr_dev);
  229. /* Enable TX and RX functions */
  230. ca_reg_read(&rxmac_cfg, (u64)priv->ni_hv_base_addr,
  231. NI_HV_PT_RXMAC_CFG_OFFSET +
  232. (APB0_NI_HV_PT_STRIDE * priv->active_port));
  233. rxmac_cfg.rx_en = 1;
  234. ca_reg_write(&rxmac_cfg, (u64)priv->ni_hv_base_addr,
  235. NI_HV_PT_RXMAC_CFG_OFFSET +
  236. (APB0_NI_HV_PT_STRIDE * priv->active_port));
  237. ca_reg_read(&txmac_cfg, (u64)priv->ni_hv_base_addr,
  238. NI_HV_PT_TXMAC_CFG_OFFSET +
  239. (APB0_NI_HV_PT_STRIDE * priv->active_port));
  240. txmac_cfg.tx_en = 1;
  241. ca_reg_write(&txmac_cfg, (u64)priv->ni_hv_base_addr,
  242. NI_HV_PT_TXMAC_CFG_OFFSET +
  243. (APB0_NI_HV_PT_STRIDE * priv->active_port));
  244. }
  245. #define AUTO_SCAN_TIMEOUT 3000 /* 3 seconds */
  246. static int ca_ni_auto_scan_active_port(struct cortina_ni_priv *priv)
  247. {
  248. u8 i;
  249. u16 data;
  250. u32 start_time;
  251. start_time = get_timer(0);
  252. while (get_timer(start_time) < AUTO_SCAN_TIMEOUT) {
  253. for (i = 0; i < priv->valid_port_num; i++) {
  254. if (!priv->port_map[i].phy_addr)
  255. continue;
  256. ca_mdio_read(priv->port_map[i].phy_addr, 1, &data);
  257. if (data & 0x04) {
  258. priv->active_port = priv->port_map[i].port;
  259. return 0;
  260. }
  261. }
  262. }
  263. printf("CA NI %s: auto scan active_port timeout.\n", __func__);
  264. return -1;
  265. }
  266. static void ca_ni_led(int port, int status)
  267. {
  268. char label[10];
  269. struct udevice *led_dev;
  270. if (IS_ENABLED(CONFIG_LED_CORTINA)) {
  271. snprintf(label, sizeof(label), "led%d", port);
  272. debug("%s: set port %d led %s.\n",
  273. __func__, port, status ? "on" : "off");
  274. led_get_by_label(label, &led_dev);
  275. led_set_state(led_dev, status);
  276. }
  277. }
  278. static void ca_ni_reset(void)
  279. {
  280. int i;
  281. struct NI_HV_GLB_INIT_DONE_t init_done;
  282. struct NI_HV_GLB_INTF_RST_CONFIG_t intf_rst_config;
  283. struct NI_HV_GLB_STATIC_CFG_t static_cfg;
  284. struct GLOBAL_BLOCK_RESET_t glb_blk_reset;
  285. struct cortina_ni_priv *priv = dev_get_priv(curr_dev);
  286. /* NI global resets */
  287. ca_reg_read(&glb_blk_reset, (u64)priv->glb_base_addr,
  288. GLOBAL_BLOCK_RESET_OFFSET);
  289. glb_blk_reset.reset_ni = 1;
  290. ca_reg_write(&glb_blk_reset, (u64)priv->glb_base_addr,
  291. GLOBAL_BLOCK_RESET_OFFSET);
  292. /* Remove resets */
  293. glb_blk_reset.reset_ni = 0;
  294. ca_reg_write(&glb_blk_reset, (u64)priv->glb_base_addr,
  295. GLOBAL_BLOCK_RESET_OFFSET);
  296. /* check the ready bit of NI module */
  297. for (i = 0; i < NI_READ_POLL_COUNT; i++) {
  298. ca_reg_read(&init_done, (u64)priv->ni_hv_base_addr,
  299. NI_HV_GLB_INIT_DONE_OFFSET);
  300. if (init_done.ni_init_done)
  301. break;
  302. }
  303. if (i == NI_READ_POLL_COUNT) {
  304. printf("CA NI %s: NI init done not ready, init_done=0x%x!!!\n",
  305. __func__, init_done.ni_init_done);
  306. }
  307. ca_reg_read(&intf_rst_config, (u64)priv->ni_hv_base_addr,
  308. NI_HV_GLB_INTF_RST_CONFIG_OFFSET);
  309. switch (priv->active_port) {
  310. case NI_PORT_0:
  311. intf_rst_config.intf_rst_p0 = 0;
  312. intf_rst_config.mac_rx_rst_p0 = 0;
  313. intf_rst_config.mac_tx_rst_p0 = 0;
  314. break;
  315. case NI_PORT_1:
  316. intf_rst_config.intf_rst_p1 = 0;
  317. intf_rst_config.mac_rx_rst_p1 = 0;
  318. intf_rst_config.mac_tx_rst_p1 = 0;
  319. break;
  320. case NI_PORT_2:
  321. intf_rst_config.intf_rst_p2 = 0;
  322. intf_rst_config.mac_rx_rst_p2 = 0;
  323. intf_rst_config.mac_tx_rst_p2 = 0;
  324. break;
  325. case NI_PORT_3:
  326. intf_rst_config.intf_rst_p3 = 0;
  327. intf_rst_config.mac_tx_rst_p3 = 0;
  328. intf_rst_config.mac_rx_rst_p3 = 0;
  329. break;
  330. case NI_PORT_4:
  331. intf_rst_config.intf_rst_p4 = 0;
  332. intf_rst_config.mac_tx_rst_p4 = 0;
  333. intf_rst_config.mac_rx_rst_p4 = 0;
  334. break;
  335. }
  336. ca_reg_write(&intf_rst_config, (u64)priv->ni_hv_base_addr,
  337. NI_HV_GLB_INTF_RST_CONFIG_OFFSET);
  338. /* Only one GMAC can connect to CPU */
  339. ca_reg_read(&static_cfg, (u64)priv->ni_hv_base_addr,
  340. NI_HV_GLB_STATIC_CFG_OFFSET);
  341. static_cfg.port_to_cpu = priv->active_port;
  342. static_cfg.txmib_mode = 1;
  343. static_cfg.rxmib_mode = 1;
  344. ca_reg_write(&static_cfg, (u64)priv->ni_hv_base_addr,
  345. NI_HV_GLB_STATIC_CFG_OFFSET);
  346. }
  347. static void ca_internal_gphy_cal(struct cortina_ni_priv *priv)
  348. {
  349. int i, port, num;
  350. u32 reg_off, value;
  351. num = priv->gphy_num;
  352. for (port = 0; port < 4; port++) {
  353. for (i = 0; i < num; i++) {
  354. reg_off = priv->gphy_values[i].reg_off + (port * 0x80);
  355. value = priv->gphy_values[i].value;
  356. ca_reg_write(&value, reg_off, 0);
  357. mdelay(50);
  358. }
  359. }
  360. }
  361. static int ca_mdio_register(struct udevice *dev)
  362. {
  363. int ret;
  364. struct cortina_ni_priv *priv = dev_get_priv(dev);
  365. struct mii_dev *mdio_bus = mdio_alloc();
  366. if (!mdio_bus)
  367. return -ENOMEM;
  368. mdio_bus->read = cortina_mdio_read;
  369. mdio_bus->write = cortina_mdio_write;
  370. snprintf(mdio_bus->name, sizeof(mdio_bus->name), dev->name);
  371. mdio_bus->priv = (void *)priv;
  372. ret = mdio_register(mdio_bus);
  373. if (ret)
  374. return ret;
  375. priv->mdio_bus = mdio_bus;
  376. return 0;
  377. }
  378. static void ca_rgmii_init(struct cortina_ni_priv *priv)
  379. {
  380. struct GLOBAL_GLOBAL_CONFIG_t glb_config;
  381. struct GLOBAL_IO_DRIVE_CONTROL_t io_drive_control;
  382. /* Generating 25Mhz reference clock for switch */
  383. ca_reg_read(&glb_config, (u64)priv->glb_base_addr,
  384. GLOBAL_GLOBAL_CONFIG_OFFSET);
  385. glb_config.refclk_sel = 0x01;
  386. glb_config.ext_reset = 0x01;
  387. ca_reg_write(&glb_config, (u64)priv->glb_base_addr,
  388. GLOBAL_GLOBAL_CONFIG_OFFSET);
  389. mdelay(20);
  390. /* Do external reset */
  391. ca_reg_read(&glb_config, (u64)priv->glb_base_addr,
  392. GLOBAL_GLOBAL_CONFIG_OFFSET);
  393. glb_config.ext_reset = 0x0;
  394. ca_reg_write(&glb_config, (u64)priv->glb_base_addr,
  395. GLOBAL_GLOBAL_CONFIG_OFFSET);
  396. ca_reg_read(&io_drive_control, (u64)priv->glb_base_addr,
  397. GLOBAL_IO_DRIVE_CONTROL_OFFSET);
  398. io_drive_control.gmac_mode = 2;
  399. io_drive_control.gmac_dn = 1;
  400. io_drive_control.gmac_dp = 1;
  401. ca_reg_write(&io_drive_control, (u64)priv->glb_base_addr,
  402. GLOBAL_IO_DRIVE_CONTROL_OFFSET);
  403. }
  404. static int ca_phy_probe(struct udevice *dev)
  405. {
  406. int auto_scan_active_port = 0, tmp_port;
  407. char *buf;
  408. struct cortina_ni_priv *priv = dev_get_priv(dev);
  409. struct phy_device *int_phydev, *ext_phydev;
  410. /* Initialize internal phy device */
  411. int_phydev = phy_connect(priv->mdio_bus,
  412. priv->port_map[NI_PORT_3].phy_addr,
  413. dev, priv->phy_interface);
  414. if (int_phydev) {
  415. int_phydev->supported &= PHY_GBIT_FEATURES;
  416. int_phydev->advertising = int_phydev->supported;
  417. phy_config(int_phydev);
  418. } else {
  419. printf("CA NI %s: There is no internal phy device\n", __func__);
  420. }
  421. /* Initialize external phy device */
  422. ext_phydev = phy_connect(priv->mdio_bus,
  423. priv->port_map[NI_PORT_4].phy_addr,
  424. dev, priv->phy_interface);
  425. if (ext_phydev) {
  426. ext_phydev->supported &= PHY_GBIT_FEATURES;
  427. ext_phydev->advertising = int_phydev->supported;
  428. phy_config(ext_phydev);
  429. } else {
  430. printf("CA NI %s: There is no external phy device\n", __func__);
  431. }
  432. /* auto scan the first link up port as active_port */
  433. buf = env_get("auto_scan_active_port");
  434. if (buf != 0) {
  435. auto_scan_active_port = simple_strtoul(buf, NULL, 0);
  436. printf("CA NI %s: auto_scan_active_port=%d\n", __func__,
  437. auto_scan_active_port);
  438. }
  439. if (auto_scan_active_port) {
  440. ca_ni_auto_scan_active_port(priv);
  441. } else {
  442. buf = env_get("active_port");
  443. if (buf != 0) {
  444. tmp_port = simple_strtoul(buf, NULL, 0);
  445. if (tmp_port < 0 &&
  446. !(priv->valid_port_map && BIT(tmp_port))) {
  447. printf("CA NI ERROR: not support this port.");
  448. free(dev);
  449. free(priv);
  450. return 1;
  451. }
  452. priv->active_port = tmp_port;
  453. }
  454. }
  455. printf("CA NI %s: active_port=%d\n", __func__, priv->active_port);
  456. if (priv->active_port == NI_PORT_4)
  457. priv->phydev = ext_phydev;
  458. else
  459. priv->phydev = int_phydev;
  460. return 0;
  461. }
  462. static int cortina_eth_start(struct udevice *dev)
  463. {
  464. int ret;
  465. struct NI_HV_XRAM_CPUXRAM_ADRCFG_RX_t cpuxram_adrcfg_rx;
  466. struct NI_HV_XRAM_CPUXRAM_ADRCFG_TX_0_t cpuxram_adrcfg_tx;
  467. struct NI_HV_XRAM_CPUXRAM_CFG_t cpuxram_cfg;
  468. struct NI_HV_PT_PORT_STATIC_CFG_t port_static_cfg;
  469. struct NI_HV_PT_PORT_GLB_CFG_t port_glb_cfg;
  470. struct cortina_ni_priv *priv = dev_get_priv(dev);
  471. struct phy_device *phydev = priv->phydev;
  472. ret = phy_startup(priv->phydev);
  473. if (ret) {
  474. ca_ni_led(priv->active_port, CA_LED_OFF);
  475. printf("CA NI Could not initialize PHY %s, active_port=%d\n",
  476. priv->phydev->dev->name, priv->active_port);
  477. return ret;
  478. }
  479. if (!priv->phydev->link) {
  480. printf("CA NI %s: link down.\n", priv->phydev->dev->name);
  481. return 0;
  482. }
  483. ca_ni_led(priv->active_port, CA_LED_ON);
  484. printf("CA NI PHY ID 0x%08X %dMbps %s duplex\n",
  485. phydev->phy_id, phydev->speed,
  486. phydev->duplex == DUPLEX_HALF ? "half" : "full");
  487. /* RX XRAM ADDRESS CONFIG (start and end address) */
  488. memset(&cpuxram_adrcfg_rx, 0, sizeof(cpuxram_adrcfg_rx));
  489. cpuxram_adrcfg_rx.rx_top_addr = RX_TOP_ADDR;
  490. cpuxram_adrcfg_rx.rx_base_addr = RX_BASE_ADDR;
  491. ca_reg_write(&cpuxram_adrcfg_rx, (u64)priv->ni_hv_base_addr,
  492. NI_HV_XRAM_CPUXRAM_ADRCFG_RX_OFFSET);
  493. /* TX XRAM ADDRESS CONFIG (start and end address) */
  494. memset(&cpuxram_adrcfg_tx, 0, sizeof(cpuxram_adrcfg_tx));
  495. cpuxram_adrcfg_tx.tx_top_addr = TX_TOP_ADDR;
  496. cpuxram_adrcfg_tx.tx_base_addr = TX_BASE_ADDR;
  497. ca_reg_write(&cpuxram_adrcfg_tx, (u64)priv->ni_hv_base_addr,
  498. NI_HV_XRAM_CPUXRAM_ADRCFG_TX_0_OFFSET);
  499. /*
  500. * Configuration for Management Ethernet Interface:
  501. * - RGMII 1000 mode or RGMII 100 mode
  502. * - MAC mode
  503. */
  504. ca_reg_read(&port_static_cfg, (u64)priv->ni_hv_base_addr,
  505. NI_HV_PT_PORT_STATIC_CFG_OFFSET +
  506. (APB0_NI_HV_PT_STRIDE * priv->active_port));
  507. if (phydev->speed == SPEED_1000) {
  508. /* port 4 connects to RGMII PHY */
  509. if (phydev->addr == 5)
  510. port_static_cfg.int_cfg = GE_MAC_INTF_RGMII_1000;
  511. else
  512. port_static_cfg.int_cfg = GE_MAC_INTF_GMII;
  513. } else {
  514. /* port 4 connects to RGMII PHY */
  515. if (phydev->addr == 5)
  516. port_static_cfg.int_cfg = GE_MAC_INTF_RGMII_100;
  517. else
  518. port_static_cfg.int_cfg = GE_MAC_INTF_MII;
  519. }
  520. ca_reg_write(&port_static_cfg, (u64)priv->ni_hv_base_addr,
  521. NI_HV_PT_PORT_STATIC_CFG_OFFSET +
  522. (APB0_NI_HV_PT_STRIDE * priv->active_port));
  523. ca_reg_read(&port_glb_cfg, (u64)priv->ni_hv_base_addr,
  524. NI_HV_PT_PORT_GLB_CFG_OFFSET +
  525. (APB0_NI_HV_PT_STRIDE * priv->active_port));
  526. port_glb_cfg.speed = phydev->speed == SPEED_10 ? 1 : 0;
  527. port_glb_cfg.duplex = phydev->duplex == DUPLEX_HALF ? 1 : 0;
  528. ca_reg_write(&port_glb_cfg, (u64)priv->ni_hv_base_addr,
  529. NI_HV_PT_PORT_GLB_CFG_OFFSET +
  530. (APB0_NI_HV_PT_STRIDE * priv->active_port));
  531. /* Need to toggle the tx and rx cpu_pkt_dis bit */
  532. /* after changing Address config register. */
  533. ca_reg_read(&cpuxram_cfg, (u64)priv->ni_hv_base_addr,
  534. NI_HV_XRAM_CPUXRAM_CFG_OFFSET);
  535. cpuxram_cfg.rx_0_cpu_pkt_dis = 1;
  536. cpuxram_cfg.tx_0_cpu_pkt_dis = 1;
  537. ca_reg_write(&cpuxram_cfg, (u64)priv->ni_hv_base_addr,
  538. NI_HV_XRAM_CPUXRAM_CFG_OFFSET);
  539. ca_reg_read(&cpuxram_cfg, (u64)priv->ni_hv_base_addr,
  540. NI_HV_XRAM_CPUXRAM_CFG_OFFSET);
  541. cpuxram_cfg.rx_0_cpu_pkt_dis = 0;
  542. cpuxram_cfg.tx_0_cpu_pkt_dis = 0;
  543. ca_reg_write(&cpuxram_cfg, (u64)priv->ni_hv_base_addr,
  544. NI_HV_XRAM_CPUXRAM_CFG_OFFSET);
  545. ca_ni_enable_tx_rx();
  546. return 0;
  547. }
  548. /*********************************************
  549. * Packet receive routine from Management FE
  550. * Expects a previously allocated buffer and
  551. * fills the length
  552. * Retruns 0 on success -1 on failure
  553. *******************************************/
  554. static int cortina_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  555. {
  556. u8 *ptr;
  557. u32 next_link, pktlen = 0;
  558. u32 sw_rx_rd_ptr, hw_rx_wr_ptr, *rx_xram_ptr, *data_ptr;
  559. int loop, index = 0, blk_num;
  560. struct cortina_ni_priv *priv = dev_get_priv(dev);
  561. struct NI_HEADER_X_T header_x;
  562. struct NI_PACKET_STATUS packet_status;
  563. struct NI_HV_XRAM_CPUXRAM_CPU_STA_RX_0_t cpuxram_cpu_sta_rx;
  564. struct NI_HV_XRAM_CPUXRAM_CPU_CFG_RX_0_t cpuxram_cpu_cfg_rx;
  565. /* get the hw write pointer */
  566. memset(&cpuxram_cpu_sta_rx, 0, sizeof(cpuxram_cpu_sta_rx));
  567. ca_reg_read(&cpuxram_cpu_sta_rx, (u64)priv->ni_hv_base_addr,
  568. NI_HV_XRAM_CPUXRAM_CPU_STA_RX_0_OFFSET);
  569. hw_rx_wr_ptr = cpuxram_cpu_sta_rx.pkt_wr_ptr;
  570. /* get the sw read pointer */
  571. memset(&cpuxram_cpu_cfg_rx, 0, sizeof(cpuxram_cpu_cfg_rx));
  572. ca_reg_read(&cpuxram_cpu_cfg_rx, (u64)priv->ni_hv_base_addr,
  573. NI_HV_XRAM_CPUXRAM_CPU_CFG_RX_0_OFFSET);
  574. sw_rx_rd_ptr = cpuxram_cpu_cfg_rx.pkt_rd_ptr;
  575. debug("%s: NI_HV_XRAM_CPUXRAM_CPU_STA_RX_0 = 0x%p, ", __func__,
  576. priv->ni_hv_base_addr + NI_HV_XRAM_CPUXRAM_CPU_STA_RX_0_OFFSET);
  577. debug("NI_HV_XRAM_CPUXRAM_CPU_CFG_RX_0 = 0x%p\n",
  578. priv->ni_hv_base_addr + NI_HV_XRAM_CPUXRAM_CPU_CFG_RX_0_OFFSET);
  579. debug("%s : RX hw_wr_ptr = %d, sw_rd_ptr = %d\n",
  580. __func__, hw_rx_wr_ptr, sw_rx_rd_ptr);
  581. while (sw_rx_rd_ptr != hw_rx_wr_ptr) {
  582. /* Point to the absolute memory address of XRAM
  583. * where read pointer is
  584. */
  585. rx_xram_ptr = (u32 *)
  586. ((unsigned long)priv->ni_xram_base
  587. + sw_rx_rd_ptr * 8);
  588. /* Wrap around if required */
  589. if (rx_xram_ptr >= (u32 *)(unsigned long)priv->rx_xram_end_adr)
  590. rx_xram_ptr = (u32 *)
  591. (unsigned long)priv->rx_xram_base_adr;
  592. /* Checking header XR. Do not update the read pointer yet */
  593. /* skip unused 32-bit in Header XR */
  594. rx_xram_ptr = ca_rdwrptr_adv_one(rx_xram_ptr,
  595. priv->rx_xram_base_adr,
  596. priv->rx_xram_end_adr);
  597. memcpy(&header_x, rx_xram_ptr, sizeof(header_x));
  598. next_link = header_x.next_link;
  599. /* Header XR [31:0] */
  600. if (*rx_xram_ptr == 0xffffffff)
  601. printf("CA NI %s: XRAM Error !\n", __func__);
  602. debug("%s : RX next link 0x%x\n", __func__, next_link);
  603. debug("%s : bytes_valid %x\n", __func__, header_x.bytes_valid);
  604. if (header_x.ownership == 0) {
  605. /* point to Packet status [31:0] */
  606. rx_xram_ptr = ca_rdwrptr_adv_one(rx_xram_ptr,
  607. priv->rx_xram_base_adr,
  608. priv->rx_xram_end_adr);
  609. memcpy(&packet_status, rx_xram_ptr,
  610. sizeof(*rx_xram_ptr));
  611. if (packet_status.valid == 0) {
  612. debug("%s: Invalid Packet !!, ", __func__);
  613. debug("next_link=%d\n", next_link);
  614. /* Update the software read pointer */
  615. ca_reg_write(&next_link,
  616. (u64)priv->ni_hv_base_addr,
  617. NI_HV_XRAM_CPUXRAM_CPU_CFG_RX_0_OFFSET);
  618. return 0;
  619. }
  620. if (packet_status.drop ||
  621. packet_status.runt ||
  622. packet_status.oversize ||
  623. packet_status.jabber ||
  624. packet_status.crc_error ||
  625. packet_status.jumbo) {
  626. debug("%s: Error Packet!!, ", __func__);
  627. debug("next_link=%d\n", next_link);
  628. /* Update the software read pointer */
  629. ca_reg_write(&next_link,
  630. (u64)priv->ni_hv_base_addr,
  631. NI_HV_XRAM_CPUXRAM_CPU_CFG_RX_0_OFFSET);
  632. return 0;
  633. }
  634. /* check whether packet size is larger than 1514 */
  635. if (packet_status.packet_size > 1518) {
  636. debug("%s: Error Packet !! Packet size=%d, ",
  637. __func__, packet_status.packet_size);
  638. debug("larger than 1518, next_link=%d\n",
  639. next_link);
  640. /* Update the software read pointer */
  641. ca_reg_write(&next_link,
  642. (u64)priv->ni_hv_base_addr,
  643. NI_HV_XRAM_CPUXRAM_CPU_CFG_RX_0_OFFSET);
  644. return 0;
  645. }
  646. rx_xram_ptr = ca_rdwrptr_adv_one(rx_xram_ptr,
  647. priv->rx_xram_base_adr,
  648. priv->rx_xram_end_adr);
  649. pktlen = packet_status.packet_size;
  650. debug("%s : rx packet length = %d\n",
  651. __func__, packet_status.packet_size);
  652. rx_xram_ptr = ca_rdwrptr_adv_one(rx_xram_ptr,
  653. priv->rx_xram_base_adr,
  654. priv->rx_xram_end_adr);
  655. data_ptr = (u32 *)net_rx_packets[index];
  656. /* Read out the packet */
  657. /* Data is in little endian form in the XRAM */
  658. /* Send the packet to upper layer */
  659. debug("%s: packet data[]=", __func__);
  660. for (loop = 0; loop <= pktlen / 4; loop++) {
  661. ptr = (u8 *)rx_xram_ptr;
  662. if (loop < 10)
  663. debug("[0x%x]-[0x%x]-[0x%x]-[0x%x]",
  664. ptr[0], ptr[1], ptr[2], ptr[3]);
  665. *data_ptr++ = *rx_xram_ptr++;
  666. /* Wrap around if required */
  667. if (rx_xram_ptr >= (u32 *)
  668. (unsigned long)priv->rx_xram_end_adr) {
  669. rx_xram_ptr = (u32 *)(unsigned long)
  670. (priv->rx_xram_base_adr);
  671. }
  672. }
  673. debug("\n");
  674. net_process_received_packet(net_rx_packets[index],
  675. pktlen);
  676. if (++index >= PKTBUFSRX)
  677. index = 0;
  678. blk_num = net_rx_packets[index][0x2c] * 255 +
  679. net_rx_packets[index][0x2d];
  680. debug("%s: tftp block number=%d\n", __func__, blk_num);
  681. /* Update the software read pointer */
  682. ca_reg_write(&next_link,
  683. (u64)priv->ni_hv_base_addr,
  684. NI_HV_XRAM_CPUXRAM_CPU_CFG_RX_0_OFFSET);
  685. }
  686. /* get the hw write pointer */
  687. ca_reg_read(&cpuxram_cpu_sta_rx, (u64)priv->ni_hv_base_addr,
  688. NI_HV_XRAM_CPUXRAM_CPU_STA_RX_0_OFFSET);
  689. hw_rx_wr_ptr = cpuxram_cpu_sta_rx.pkt_wr_ptr;
  690. /* get the sw read pointer */
  691. ca_reg_read(&sw_rx_rd_ptr, (u64)priv->ni_hv_base_addr,
  692. NI_HV_XRAM_CPUXRAM_CPU_CFG_RX_0_OFFSET);
  693. }
  694. return 0;
  695. }
  696. static int cortina_eth_send(struct udevice *dev, void *packet, int length)
  697. {
  698. u32 hw_tx_rd_ptr = 0, sw_tx_wr_ptr = 0;
  699. u32 loop, new_pkt_len, ca_crc32;
  700. u32 *tx_xram_ptr, *data_ptr;
  701. u16 next_link = 0;
  702. u8 *ptr, *pkt_buf_ptr, valid_bytes = 0;
  703. int pad = 0;
  704. static u8 pkt_buf[2048];
  705. struct NI_HEADER_X_T hdr_xt;
  706. struct NI_HV_XRAM_CPUXRAM_CPU_CFG_TX_0_t cpuxram_cpu_cfg_tx;
  707. struct cortina_ni_priv *priv = dev_get_priv(dev);
  708. if (!packet || length > 2032)
  709. return -1;
  710. /* Get the hardware read pointer */
  711. ca_reg_read(&hw_tx_rd_ptr, (u64)priv->ni_hv_base_addr,
  712. NI_HV_XRAM_CPUXRAM_CPU_STAT_TX_0_OFFSET);
  713. /* Get the software write pointer */
  714. ca_reg_read(&sw_tx_wr_ptr, (u64)priv->ni_hv_base_addr,
  715. NI_HV_XRAM_CPUXRAM_CPU_CFG_TX_0_OFFSET);
  716. debug("%s: NI_HV_XRAM_CPUXRAM_CPU_STAT_TX_0=0x%p, ",
  717. __func__,
  718. KSEG1_ATU_XLAT(priv->ni_hv_base_addr +
  719. NI_HV_XRAM_CPUXRAM_CPU_STAT_TX_0_OFFSET));
  720. debug("NI_HV_XRAM_CPUXRAM_CPU_CFG_TX_0=0x%p\n",
  721. KSEG1_ATU_XLAT(priv->ni_hv_base_addr +
  722. NI_HV_XRAM_CPUXRAM_CPU_CFG_TX_0_OFFSET));
  723. debug("%s : hw_tx_rd_ptr = %d\n", __func__, hw_tx_rd_ptr);
  724. debug("%s : sw_tx_wr_ptr = %d\n", __func__, sw_tx_wr_ptr);
  725. if (hw_tx_rd_ptr != sw_tx_wr_ptr) {
  726. printf("CA NI %s: Tx FIFO is not available!\n", __func__);
  727. return 1;
  728. }
  729. /* a workaround on 2015/10/01
  730. * the packet size+CRC should be 8-byte alignment
  731. */
  732. if (((length + 4) % 8) != 0)
  733. length += (8 - ((length + 4) % 8));
  734. memset(pkt_buf, 0x00, sizeof(pkt_buf));
  735. /* add 8-byte header_A at the beginning of packet */
  736. memcpy(&pkt_buf[HEADER_A_SIZE], (const void *)packet, length);
  737. pad = 64 - (length + 4); /* if packet length < 60 */
  738. pad = (pad < 0) ? 0 : pad;
  739. debug("%s: length=%d, pad=%d\n", __func__, length, pad);
  740. new_pkt_len = length + pad; /* new packet length */
  741. pkt_buf_ptr = (u8 *)pkt_buf;
  742. /* Calculate the CRC32, skip 8-byte header_A */
  743. ca_crc32 = crc32(0, (u8 *)(pkt_buf_ptr + HEADER_A_SIZE), new_pkt_len);
  744. debug("%s: crc32 is 0x%x\n", __func__, ca_crc32);
  745. debug("%s: ~crc32 is 0x%x\n", __func__, ~ca_crc32);
  746. debug("%s: pkt len %d\n", __func__, new_pkt_len);
  747. /* should add 8-byte header_! */
  748. /* CRC will re-calculated by hardware */
  749. memcpy((pkt_buf_ptr + new_pkt_len + HEADER_A_SIZE),
  750. (u8 *)(&ca_crc32), sizeof(ca_crc32));
  751. new_pkt_len = new_pkt_len + 4; /* add CRC */
  752. valid_bytes = new_pkt_len % 8;
  753. valid_bytes = valid_bytes ? valid_bytes : 0;
  754. debug("%s: valid_bytes %d\n", __func__, valid_bytes);
  755. /* should add 8-byte headerA */
  756. next_link = sw_tx_wr_ptr +
  757. (new_pkt_len + 7 + HEADER_A_SIZE) / 8; /* for headr XT */
  758. /* add header */
  759. next_link = next_link + 1;
  760. /* Wrap around if required */
  761. if (next_link > priv->tx_xram_end) {
  762. next_link = priv->tx_xram_start +
  763. (next_link - (priv->tx_xram_end + 1));
  764. }
  765. debug("%s: TX next_link %x\n", __func__, next_link);
  766. memset(&hdr_xt, 0, sizeof(hdr_xt));
  767. hdr_xt.ownership = 1;
  768. hdr_xt.bytes_valid = valid_bytes;
  769. hdr_xt.next_link = next_link;
  770. tx_xram_ptr = (u32 *)((unsigned long)priv->ni_xram_base
  771. + sw_tx_wr_ptr * 8);
  772. /* Wrap around if required */
  773. if (tx_xram_ptr >= (u32 *)(unsigned long)priv->tx_xram_end_adr)
  774. tx_xram_ptr = (u32 *)(unsigned long)priv->tx_xram_base_adr;
  775. tx_xram_ptr = ca_rdwrptr_adv_one(tx_xram_ptr,
  776. priv->tx_xram_base_adr,
  777. priv->tx_xram_end_adr);
  778. memcpy(tx_xram_ptr, &hdr_xt, sizeof(*tx_xram_ptr));
  779. tx_xram_ptr = ca_rdwrptr_adv_one(tx_xram_ptr,
  780. priv->tx_xram_base_adr,
  781. priv->tx_xram_end_adr);
  782. /* Now to copy the data. The first byte on the line goes first */
  783. data_ptr = (u32 *)pkt_buf_ptr;
  784. debug("%s: packet data[]=", __func__);
  785. /* copy header_A to XRAM */
  786. for (loop = 0; loop <= (new_pkt_len + HEADER_A_SIZE) / 4; loop++) {
  787. ptr = (u8 *)data_ptr;
  788. if ((loop % 4) == 0)
  789. debug("\n");
  790. debug("[0x%x]-[0x%x]-[0x%x]-[0x%x]-",
  791. ptr[0], ptr[1], ptr[2], ptr[3]);
  792. *tx_xram_ptr = *data_ptr++;
  793. tx_xram_ptr = ca_rdwrptr_adv_one(tx_xram_ptr,
  794. priv->tx_xram_base_adr,
  795. priv->tx_xram_end_adr);
  796. }
  797. debug("\n");
  798. /* Publish the software write pointer */
  799. cpuxram_cpu_cfg_tx.pkt_wr_ptr = next_link;
  800. ca_reg_write(&cpuxram_cpu_cfg_tx,
  801. (u64)priv->ni_hv_base_addr,
  802. NI_HV_XRAM_CPUXRAM_CPU_CFG_TX_0_OFFSET);
  803. return 0;
  804. }
  805. static void cortina_eth_stop(struct udevice *netdev)
  806. {
  807. /* Nothing to do for now. */
  808. }
  809. static int cortina_eth_probe(struct udevice *dev)
  810. {
  811. int ret, reg_value;
  812. struct cortina_ni_priv *priv;
  813. priv = dev_get_priv(dev);
  814. priv->rx_xram_base_adr = priv->ni_xram_base + (RX_BASE_ADDR * 8);
  815. priv->rx_xram_end_adr = priv->ni_xram_base + ((RX_TOP_ADDR + 1) * 8);
  816. priv->rx_xram_start = RX_BASE_ADDR;
  817. priv->rx_xram_end = RX_TOP_ADDR;
  818. priv->tx_xram_base_adr = priv->ni_xram_base + (TX_BASE_ADDR * 8);
  819. priv->tx_xram_end_adr = priv->ni_xram_base + ((TX_TOP_ADDR + 1) * 8);
  820. priv->tx_xram_start = TX_BASE_ADDR;
  821. priv->tx_xram_end = TX_TOP_ADDR;
  822. curr_dev = dev;
  823. debug("%s: rx_base_addr:%x\t rx_top_addr %x\n",
  824. __func__, priv->rx_xram_start, priv->rx_xram_end);
  825. debug("%s: tx_base_addr:%x\t tx_top_addr %x\n",
  826. __func__, priv->tx_xram_start, priv->tx_xram_end);
  827. debug("%s: rx physical start address = %x end address = %x\n",
  828. __func__, priv->rx_xram_base_adr, priv->rx_xram_end_adr);
  829. debug("%s: tx physical start address = %x end address = %x\n",
  830. __func__, priv->tx_xram_base_adr, priv->tx_xram_end_adr);
  831. /* MDIO register */
  832. ret = ca_mdio_register(dev);
  833. if (ret)
  834. return ret;
  835. /* set MDIO pre-scale value */
  836. ca_reg_read(&reg_value, (u64)priv->per_mdio_base_addr,
  837. PER_MDIO_CFG_OFFSET);
  838. reg_value = reg_value | 0x00280000;
  839. ca_reg_write(&reg_value, (u64)priv->per_mdio_base_addr,
  840. PER_MDIO_CFG_OFFSET);
  841. ca_phy_probe(dev);
  842. priv->phydev->addr = priv->port_map[priv->active_port].phy_addr;
  843. ca_ni_led(priv->active_port, CA_LED_ON);
  844. ca_ni_reset();
  845. printf("CA NI %s: active_port=%d, phy_addr=%d\n",
  846. __func__, priv->active_port, priv->phydev->addr);
  847. printf("CA NI %s: phy_id=0x%x, phy_id & PHY_ID_MASK=0x%x\n", __func__,
  848. priv->phydev->phy_id, priv->phydev->phy_id & 0xFFFFFFF0);
  849. /* parsing ethaddr and set to NI registers. */
  850. ca_ni_setup_mac_addr();
  851. #ifdef MIIPHY_REGISTER
  852. /* the phy_read and phy_write
  853. * should meet the proto type of miiphy_register
  854. */
  855. miiphy_register(dev->name, ca_miiphy_read, ca_miiphy_write);
  856. #endif
  857. if (priv->init_rgmii) {
  858. /* hardware settings for RGMII port */
  859. ca_rgmii_init(priv);
  860. }
  861. if (priv->gphy_num > 0) {
  862. /* do internal gphy calibration */
  863. ca_internal_gphy_cal(priv);
  864. }
  865. return 0;
  866. }
  867. static int ca_ni_of_to_plat(struct udevice *dev)
  868. {
  869. int i, ret;
  870. struct cortina_ni_priv *priv = dev_get_priv(dev);
  871. memset(priv, 0, sizeof(struct cortina_ni_priv));
  872. priv->glb_base_addr = dev_remap_addr_index(dev, 0);
  873. if (!priv->glb_base_addr)
  874. return -ENOENT;
  875. printf("CA NI %s: priv->glb_base_addr for index 0 is 0x%p\n",
  876. __func__, priv->glb_base_addr);
  877. priv->per_mdio_base_addr = dev_remap_addr_index(dev, 1);
  878. if (!priv->per_mdio_base_addr)
  879. return -ENOENT;
  880. printf("CA NI %s: priv->per_mdio_base_addr for index 1 is 0x%p\n",
  881. __func__, priv->per_mdio_base_addr);
  882. priv->ni_hv_base_addr = dev_remap_addr_index(dev, 2);
  883. if (!priv->ni_hv_base_addr)
  884. return -ENOENT;
  885. printf("CA NI %s: priv->ni_hv_base_addr for index 2 is 0x%p\n",
  886. __func__, priv->ni_hv_base_addr);
  887. priv->valid_port_map = dev_read_u32_default(dev, "valid-port-map", 1);
  888. priv->valid_port_num = dev_read_u32_default(dev, "valid-port-num", 1);
  889. for (i = 0; i < priv->valid_port_num; i++) {
  890. ret = dev_read_u32_index(dev, "valid-ports", i * 2,
  891. &priv->port_map[i].phy_addr);
  892. ret = dev_read_u32_index(dev, "valid-ports", (i * 2) + 1,
  893. &priv->port_map[i].port);
  894. }
  895. priv->gphy_num = dev_read_u32_default(dev, "inter-gphy-num", 1);
  896. for (i = 0; i < priv->gphy_num; i++) {
  897. ret = dev_read_u32_index(dev, "inter-gphy-val", i * 2,
  898. &priv->gphy_values[i].reg_off);
  899. ret = dev_read_u32_index(dev, "inter-gphy-val", (i * 2) + 1,
  900. &priv->gphy_values[i].value);
  901. }
  902. priv->active_port = dev_read_u32_default(dev, "def-active-port", 1);
  903. priv->init_rgmii = dev_read_u32_default(dev, "init-rgmii", 1);
  904. priv->ni_xram_base = dev_read_u32_default(dev, "ni-xram-base", 1);
  905. return 0;
  906. }
  907. static const struct eth_ops cortina_eth_ops = {
  908. .start = cortina_eth_start,
  909. .send = cortina_eth_send,
  910. .recv = cortina_eth_recv,
  911. .stop = cortina_eth_stop,
  912. };
  913. static const struct udevice_id cortina_eth_ids[] = {
  914. { .compatible = "eth_cortina" },
  915. { }
  916. };
  917. U_BOOT_DRIVER(eth_cortina) = {
  918. .name = "eth_cortina",
  919. .id = UCLASS_ETH,
  920. .of_match = cortina_eth_ids,
  921. .probe = cortina_eth_probe,
  922. .ops = &cortina_eth_ops,
  923. .priv_auto = sizeof(struct cortina_ni_priv),
  924. .plat_auto = sizeof(struct eth_pdata),
  925. .of_to_plat = ca_ni_of_to_plat,
  926. };