calxedaxgmac.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2011 Calxeda, Inc.
  4. */
  5. #include <common.h>
  6. #include <malloc.h>
  7. #include <net.h>
  8. #include <linux/compiler.h>
  9. #include <linux/delay.h>
  10. #include <linux/err.h>
  11. #include <asm/io.h>
  12. #include <dm.h>
  13. #include <dm/device-internal.h> /* for dev_set_priv() */
  14. #define TX_NUM_DESC 1
  15. #define RX_NUM_DESC 32
  16. #define MAC_TIMEOUT (5*CONFIG_SYS_HZ)
  17. #define ETH_BUF_SZ 2048
  18. #define TX_BUF_SZ (ETH_BUF_SZ * TX_NUM_DESC)
  19. #define RX_BUF_SZ (ETH_BUF_SZ * RX_NUM_DESC)
  20. #define RXSTART 0x00000002
  21. #define TXSTART 0x00002000
  22. #define RXENABLE 0x00000004
  23. #define TXENABLE 0x00000008
  24. #define XGMAC_CONTROL_SPD 0x40000000
  25. #define XGMAC_CONTROL_SPD_MASK 0x60000000
  26. #define XGMAC_CONTROL_SARC 0x10000000
  27. #define XGMAC_CONTROL_SARK_MASK 0x18000000
  28. #define XGMAC_CONTROL_CAR 0x04000000
  29. #define XGMAC_CONTROL_CAR_MASK 0x06000000
  30. #define XGMAC_CONTROL_CAR_SHIFT 25
  31. #define XGMAC_CONTROL_DP 0x01000000
  32. #define XGMAC_CONTROL_WD 0x00800000
  33. #define XGMAC_CONTROL_JD 0x00400000
  34. #define XGMAC_CONTROL_JE 0x00100000
  35. #define XGMAC_CONTROL_LM 0x00001000
  36. #define XGMAC_CONTROL_IPC 0x00000400
  37. #define XGMAC_CONTROL_ACS 0x00000080
  38. #define XGMAC_CONTROL_DDIC 0x00000010
  39. #define XGMAC_CONTROL_TE 0x00000008
  40. #define XGMAC_CONTROL_RE 0x00000004
  41. #define XGMAC_DMA_BUSMODE_RESET 0x00000001
  42. #define XGMAC_DMA_BUSMODE_DSL 0x00000004
  43. #define XGMAC_DMA_BUSMODE_DSL_MASK 0x0000007c
  44. #define XGMAC_DMA_BUSMODE_DSL_SHIFT 2
  45. #define XGMAC_DMA_BUSMODE_ATDS 0x00000080
  46. #define XGMAC_DMA_BUSMODE_PBL_MASK 0x00003f00
  47. #define XGMAC_DMA_BUSMODE_PBL_SHIFT 8
  48. #define XGMAC_DMA_BUSMODE_FB 0x00010000
  49. #define XGMAC_DMA_BUSMODE_USP 0x00800000
  50. #define XGMAC_DMA_BUSMODE_8PBL 0x01000000
  51. #define XGMAC_DMA_BUSMODE_AAL 0x02000000
  52. #define XGMAC_DMA_AXIMODE_ENLPI 0x80000000
  53. #define XGMAC_DMA_AXIMODE_MGK 0x40000000
  54. #define XGMAC_DMA_AXIMODE_WROSR 0x00100000
  55. #define XGMAC_DMA_AXIMODE_WROSR_MASK 0x00F00000
  56. #define XGMAC_DMA_AXIMODE_WROSR_SHIFT 20
  57. #define XGMAC_DMA_AXIMODE_RDOSR 0x00010000
  58. #define XGMAC_DMA_AXIMODE_RDOSR_MASK 0x000F0000
  59. #define XGMAC_DMA_AXIMODE_RDOSR_SHIFT 16
  60. #define XGMAC_DMA_AXIMODE_AAL 0x00001000
  61. #define XGMAC_DMA_AXIMODE_BLEN256 0x00000080
  62. #define XGMAC_DMA_AXIMODE_BLEN128 0x00000040
  63. #define XGMAC_DMA_AXIMODE_BLEN64 0x00000020
  64. #define XGMAC_DMA_AXIMODE_BLEN32 0x00000010
  65. #define XGMAC_DMA_AXIMODE_BLEN16 0x00000008
  66. #define XGMAC_DMA_AXIMODE_BLEN8 0x00000004
  67. #define XGMAC_DMA_AXIMODE_BLEN4 0x00000002
  68. #define XGMAC_DMA_AXIMODE_UNDEF 0x00000001
  69. #define XGMAC_CORE_OMR_RTC_SHIFT 3
  70. #define XGMAC_CORE_OMR_RTC_MASK 0x00000018
  71. #define XGMAC_CORE_OMR_RTC 0x00000010
  72. #define XGMAC_CORE_OMR_RSF 0x00000020
  73. #define XGMAC_CORE_OMR_DT 0x00000040
  74. #define XGMAC_CORE_OMR_FEF 0x00000080
  75. #define XGMAC_CORE_OMR_EFC 0x00000100
  76. #define XGMAC_CORE_OMR_RFA_SHIFT 9
  77. #define XGMAC_CORE_OMR_RFA_MASK 0x00000E00
  78. #define XGMAC_CORE_OMR_RFD_SHIFT 12
  79. #define XGMAC_CORE_OMR_RFD_MASK 0x00007000
  80. #define XGMAC_CORE_OMR_TTC_SHIFT 16
  81. #define XGMAC_CORE_OMR_TTC_MASK 0x00030000
  82. #define XGMAC_CORE_OMR_TTC 0x00020000
  83. #define XGMAC_CORE_OMR_FTF 0x00100000
  84. #define XGMAC_CORE_OMR_TSF 0x00200000
  85. #define FIFO_MINUS_1K 0x0
  86. #define FIFO_MINUS_2K 0x1
  87. #define FIFO_MINUS_3K 0x2
  88. #define FIFO_MINUS_4K 0x3
  89. #define FIFO_MINUS_6K 0x4
  90. #define FIFO_MINUS_8K 0x5
  91. #define FIFO_MINUS_12K 0x6
  92. #define FIFO_MINUS_16K 0x7
  93. #define XGMAC_CORE_FLOW_PT_SHIFT 16
  94. #define XGMAC_CORE_FLOW_PT_MASK 0xFFFF0000
  95. #define XGMAC_CORE_FLOW_PT 0x00010000
  96. #define XGMAC_CORE_FLOW_DZQP 0x00000080
  97. #define XGMAC_CORE_FLOW_PLT_SHIFT 4
  98. #define XGMAC_CORE_FLOW_PLT_MASK 0x00000030
  99. #define XGMAC_CORE_FLOW_PLT 0x00000010
  100. #define XGMAC_CORE_FLOW_UP 0x00000008
  101. #define XGMAC_CORE_FLOW_RFE 0x00000004
  102. #define XGMAC_CORE_FLOW_TFE 0x00000002
  103. #define XGMAC_CORE_FLOW_FCB 0x00000001
  104. /* XGMAC Descriptor Defines */
  105. #define MAX_DESC_BUF_SZ (0x2000 - 8)
  106. #define RXDESC_EXT_STATUS 0x00000001
  107. #define RXDESC_CRC_ERR 0x00000002
  108. #define RXDESC_RX_ERR 0x00000008
  109. #define RXDESC_RX_WDOG 0x00000010
  110. #define RXDESC_FRAME_TYPE 0x00000020
  111. #define RXDESC_GIANT_FRAME 0x00000080
  112. #define RXDESC_LAST_SEG 0x00000100
  113. #define RXDESC_FIRST_SEG 0x00000200
  114. #define RXDESC_VLAN_FRAME 0x00000400
  115. #define RXDESC_OVERFLOW_ERR 0x00000800
  116. #define RXDESC_LENGTH_ERR 0x00001000
  117. #define RXDESC_SA_FILTER_FAIL 0x00002000
  118. #define RXDESC_DESCRIPTOR_ERR 0x00004000
  119. #define RXDESC_ERROR_SUMMARY 0x00008000
  120. #define RXDESC_FRAME_LEN_OFFSET 16
  121. #define RXDESC_FRAME_LEN_MASK 0x3fff0000
  122. #define RXDESC_DA_FILTER_FAIL 0x40000000
  123. #define RXDESC1_END_RING 0x00008000
  124. #define RXDESC_IP_PAYLOAD_MASK 0x00000003
  125. #define RXDESC_IP_PAYLOAD_UDP 0x00000001
  126. #define RXDESC_IP_PAYLOAD_TCP 0x00000002
  127. #define RXDESC_IP_PAYLOAD_ICMP 0x00000003
  128. #define RXDESC_IP_HEADER_ERR 0x00000008
  129. #define RXDESC_IP_PAYLOAD_ERR 0x00000010
  130. #define RXDESC_IPV4_PACKET 0x00000040
  131. #define RXDESC_IPV6_PACKET 0x00000080
  132. #define TXDESC_UNDERFLOW_ERR 0x00000001
  133. #define TXDESC_JABBER_TIMEOUT 0x00000002
  134. #define TXDESC_LOCAL_FAULT 0x00000004
  135. #define TXDESC_REMOTE_FAULT 0x00000008
  136. #define TXDESC_VLAN_FRAME 0x00000010
  137. #define TXDESC_FRAME_FLUSHED 0x00000020
  138. #define TXDESC_IP_HEADER_ERR 0x00000040
  139. #define TXDESC_PAYLOAD_CSUM_ERR 0x00000080
  140. #define TXDESC_ERROR_SUMMARY 0x00008000
  141. #define TXDESC_SA_CTRL_INSERT 0x00040000
  142. #define TXDESC_SA_CTRL_REPLACE 0x00080000
  143. #define TXDESC_2ND_ADDR_CHAINED 0x00100000
  144. #define TXDESC_END_RING 0x00200000
  145. #define TXDESC_CSUM_IP 0x00400000
  146. #define TXDESC_CSUM_IP_PAYLD 0x00800000
  147. #define TXDESC_CSUM_ALL 0x00C00000
  148. #define TXDESC_CRC_EN_REPLACE 0x01000000
  149. #define TXDESC_CRC_EN_APPEND 0x02000000
  150. #define TXDESC_DISABLE_PAD 0x04000000
  151. #define TXDESC_FIRST_SEG 0x10000000
  152. #define TXDESC_LAST_SEG 0x20000000
  153. #define TXDESC_INTERRUPT 0x40000000
  154. #define DESC_OWN 0x80000000
  155. #define DESC_BUFFER1_SZ_MASK 0x00001fff
  156. #define DESC_BUFFER2_SZ_MASK 0x1fff0000
  157. #define DESC_BUFFER2_SZ_OFFSET 16
  158. struct xgmac_regs {
  159. u32 config;
  160. u32 framefilter;
  161. u32 resv_1[4];
  162. u32 flow_control;
  163. u32 vlantag;
  164. u32 version;
  165. u32 vlaninclude;
  166. u32 resv_2[2];
  167. u32 pacestretch;
  168. u32 vlanhash;
  169. u32 resv_3;
  170. u32 intreg;
  171. struct {
  172. u32 hi; /* 0x40 */
  173. u32 lo; /* 0x44 */
  174. } macaddr[16];
  175. u32 resv_4[0xd0];
  176. u32 core_opmode; /* 0x400 */
  177. u32 resv_5[0x2bf];
  178. u32 busmode; /* 0xf00 */
  179. u32 txpoll;
  180. u32 rxpoll;
  181. u32 rxdesclist;
  182. u32 txdesclist;
  183. u32 dma_status;
  184. u32 dma_opmode;
  185. u32 intenable;
  186. u32 resv_6[2];
  187. u32 axi_mode; /* 0xf28 */
  188. };
  189. struct xgmac_dma_desc {
  190. __le32 flags;
  191. __le32 buf_size;
  192. __le32 buf1_addr; /* Buffer 1 Address Pointer */
  193. __le32 buf2_addr; /* Buffer 2 Address Pointer */
  194. __le32 ext_status;
  195. __le32 res[3];
  196. };
  197. static struct xgmac_regs *xgmac_get_regs(struct eth_pdata *pdata)
  198. {
  199. /*
  200. * We use PHYS_64BIT on Highbank, so phys_addr_t is bigger than
  201. * a pointer. U-Boot doesn't use LPAE (not even the MMU on highbank),
  202. * so we can't access anything above 4GB.
  203. * We have a check in the probe function below the ensure this,
  204. * so casting to a 32-bit pointer type is fine here.
  205. */
  206. return (struct xgmac_regs *)(uintptr_t)pdata->iobase;
  207. }
  208. /* XGMAC Descriptor Access Helpers */
  209. static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz)
  210. {
  211. if (buf_sz > MAX_DESC_BUF_SZ)
  212. p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ |
  213. (buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET);
  214. else
  215. p->buf_size = cpu_to_le32(buf_sz);
  216. }
  217. static inline int desc_get_buf_len(struct xgmac_dma_desc *p)
  218. {
  219. u32 len = le32_to_cpu(p->buf_size);
  220. return (len & DESC_BUFFER1_SZ_MASK) +
  221. ((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET);
  222. }
  223. static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size,
  224. int buf_sz)
  225. {
  226. struct xgmac_dma_desc *end = p + ring_size - 1;
  227. memset(p, 0, sizeof(*p) * ring_size);
  228. for (; p <= end; p++)
  229. desc_set_buf_len(p, buf_sz);
  230. end->buf_size |= cpu_to_le32(RXDESC1_END_RING);
  231. }
  232. static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size)
  233. {
  234. memset(p, 0, sizeof(*p) * ring_size);
  235. p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING);
  236. }
  237. static inline int desc_get_owner(struct xgmac_dma_desc *p)
  238. {
  239. return le32_to_cpu(p->flags) & DESC_OWN;
  240. }
  241. static inline void desc_set_rx_owner(struct xgmac_dma_desc *p)
  242. {
  243. /* Clear all fields and set the owner */
  244. p->flags = cpu_to_le32(DESC_OWN);
  245. }
  246. static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags)
  247. {
  248. u32 tmpflags = le32_to_cpu(p->flags);
  249. tmpflags &= TXDESC_END_RING;
  250. tmpflags |= flags | DESC_OWN;
  251. p->flags = cpu_to_le32(tmpflags);
  252. }
  253. static inline void *desc_get_buf_addr(struct xgmac_dma_desc *p)
  254. {
  255. return (void *)le32_to_cpu(p->buf1_addr);
  256. }
  257. static inline void desc_set_buf_addr(struct xgmac_dma_desc *p,
  258. void *paddr, int len)
  259. {
  260. p->buf1_addr = cpu_to_le32(paddr);
  261. if (len > MAX_DESC_BUF_SZ)
  262. p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ);
  263. }
  264. static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p,
  265. void *paddr, int len)
  266. {
  267. desc_set_buf_len(p, len);
  268. desc_set_buf_addr(p, paddr, len);
  269. }
  270. static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p)
  271. {
  272. u32 data = le32_to_cpu(p->flags);
  273. u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET;
  274. if (data & RXDESC_FRAME_TYPE)
  275. len -= 4;
  276. return len;
  277. }
  278. struct calxeda_eth_dev {
  279. struct xgmac_dma_desc rx_chain[RX_NUM_DESC];
  280. struct xgmac_dma_desc tx_chain[TX_NUM_DESC];
  281. char rxbuffer[RX_BUF_SZ];
  282. u32 tx_currdesc;
  283. u32 rx_currdesc;
  284. } __aligned(32);
  285. /*
  286. * Initialize a descriptor ring. Calxeda XGMAC is configured to use
  287. * advanced descriptors.
  288. */
  289. static void init_rx_desc(struct eth_pdata *pdata, struct calxeda_eth_dev *priv)
  290. {
  291. struct xgmac_dma_desc *rxdesc = priv->rx_chain;
  292. struct xgmac_regs *regs = xgmac_get_regs(pdata);
  293. void *rxbuffer = priv->rxbuffer;
  294. int i;
  295. desc_init_rx_desc(rxdesc, RX_NUM_DESC, ETH_BUF_SZ);
  296. writel((ulong)rxdesc, &regs->rxdesclist);
  297. for (i = 0; i < RX_NUM_DESC; i++) {
  298. desc_set_buf_addr(rxdesc + i, rxbuffer + (i * ETH_BUF_SZ),
  299. ETH_BUF_SZ);
  300. desc_set_rx_owner(rxdesc + i);
  301. }
  302. }
  303. static void init_tx_desc(struct eth_pdata *pdata, struct calxeda_eth_dev *priv)
  304. {
  305. struct xgmac_regs *regs = xgmac_get_regs(pdata);
  306. desc_init_tx_desc(priv->tx_chain, TX_NUM_DESC);
  307. writel((ulong)priv->tx_chain, &regs->txdesclist);
  308. }
  309. static int xgmac_reset(struct xgmac_regs *regs)
  310. {
  311. int timeout = MAC_TIMEOUT;
  312. u32 value;
  313. value = readl(&regs->config) & XGMAC_CONTROL_SPD_MASK;
  314. writel(XGMAC_DMA_BUSMODE_RESET, &regs->busmode);
  315. while ((timeout-- >= 0) &&
  316. (readl(&regs->busmode) & XGMAC_DMA_BUSMODE_RESET))
  317. udelay(1);
  318. writel(value, &regs->config);
  319. return timeout;
  320. }
  321. static void xgmac_hwmacaddr(struct eth_pdata *pdata)
  322. {
  323. struct xgmac_regs *regs = xgmac_get_regs(pdata);
  324. u32 macaddr[2];
  325. memcpy(macaddr, pdata->enetaddr, ARP_HLEN);
  326. writel(macaddr[1], &regs->macaddr[0].hi);
  327. writel(macaddr[0], &regs->macaddr[0].lo);
  328. }
  329. static int xgmac_eth_start(struct udevice *dev)
  330. {
  331. struct eth_pdata *pdata = dev_get_plat(dev);
  332. struct xgmac_regs *regs = xgmac_get_regs(pdata);
  333. struct calxeda_eth_dev *priv = dev_get_priv(dev);
  334. u32 value;
  335. if (xgmac_reset(regs) < 0)
  336. return -ETIMEDOUT;
  337. /* set the hardware MAC address */
  338. xgmac_hwmacaddr(pdata);
  339. /* set the AXI bus modes */
  340. value = XGMAC_DMA_BUSMODE_ATDS |
  341. (16 << XGMAC_DMA_BUSMODE_PBL_SHIFT) |
  342. XGMAC_DMA_BUSMODE_FB | XGMAC_DMA_BUSMODE_AAL;
  343. writel(value, &regs->busmode);
  344. value = XGMAC_DMA_AXIMODE_AAL | XGMAC_DMA_AXIMODE_BLEN16 |
  345. XGMAC_DMA_AXIMODE_BLEN8 | XGMAC_DMA_AXIMODE_BLEN4;
  346. writel(value, &regs->axi_mode);
  347. /* set flow control parameters and store and forward mode */
  348. value = (FIFO_MINUS_12K << XGMAC_CORE_OMR_RFD_SHIFT) |
  349. (FIFO_MINUS_4K << XGMAC_CORE_OMR_RFA_SHIFT) |
  350. XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF;
  351. writel(value, &regs->core_opmode);
  352. /* enable pause frames */
  353. value = (1024 << XGMAC_CORE_FLOW_PT_SHIFT) |
  354. (1 << XGMAC_CORE_FLOW_PLT_SHIFT) |
  355. XGMAC_CORE_FLOW_UP | XGMAC_CORE_FLOW_RFE | XGMAC_CORE_FLOW_TFE;
  356. writel(value, &regs->flow_control);
  357. /* Initialize the descriptor chains */
  358. init_rx_desc(pdata, priv);
  359. init_tx_desc(pdata, priv);
  360. /* must set to 0, or when started up will cause issues */
  361. priv->tx_currdesc = 0;
  362. priv->rx_currdesc = 0;
  363. /* set default core values */
  364. value = readl(&regs->config);
  365. value &= XGMAC_CONTROL_SPD_MASK;
  366. value |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_ACS |
  367. XGMAC_CONTROL_IPC | XGMAC_CONTROL_CAR;
  368. /* Everything is ready enable both mac and DMA */
  369. value |= RXENABLE | TXENABLE;
  370. writel(value, &regs->config);
  371. value = readl(&regs->dma_opmode);
  372. value |= RXSTART | TXSTART;
  373. writel(value, &regs->dma_opmode);
  374. return 0;
  375. }
  376. static int xgmac_tx(struct udevice *dev, void *packet, int length)
  377. {
  378. struct calxeda_eth_dev *priv = dev_get_priv(dev);
  379. struct eth_pdata *pdata = dev_get_plat(dev);
  380. struct xgmac_regs *regs = xgmac_get_regs(pdata);
  381. u32 currdesc = priv->tx_currdesc;
  382. struct xgmac_dma_desc *txdesc = &priv->tx_chain[currdesc];
  383. int timeout;
  384. desc_set_buf_addr_and_size(txdesc, packet, length);
  385. desc_set_tx_owner(txdesc, TXDESC_FIRST_SEG |
  386. TXDESC_LAST_SEG | TXDESC_CRC_EN_APPEND);
  387. /* write poll demand */
  388. writel(1, &regs->txpoll);
  389. timeout = 1000000;
  390. while (desc_get_owner(txdesc)) {
  391. if (timeout-- < 0) {
  392. printf("xgmac: TX timeout\n");
  393. return -ETIMEDOUT;
  394. }
  395. udelay(1);
  396. }
  397. priv->tx_currdesc = (currdesc + 1) & (TX_NUM_DESC - 1);
  398. return 0;
  399. }
  400. static int xgmac_rx(struct udevice *dev, int flags, uchar **packetp)
  401. {
  402. struct calxeda_eth_dev *priv = dev_get_priv(dev);
  403. u32 currdesc = priv->rx_currdesc;
  404. struct xgmac_dma_desc *rxdesc = &priv->rx_chain[currdesc];
  405. int length = 0;
  406. /* check if the host has the desc */
  407. if (desc_get_owner(rxdesc))
  408. return -EAGAIN; /* the MAC is still chewing on it */
  409. length = desc_get_rx_frame_len(rxdesc);
  410. *packetp = desc_get_buf_addr(rxdesc);
  411. priv->rx_currdesc = (currdesc + 1) & (RX_NUM_DESC - 1);
  412. return length;
  413. }
  414. static int xgmac_free_pkt(struct udevice *dev, uchar *packet, int length)
  415. {
  416. struct eth_pdata *pdata = dev_get_plat(dev);
  417. struct xgmac_regs *regs = xgmac_get_regs(pdata);
  418. struct calxeda_eth_dev *priv = dev_get_priv(dev);
  419. u32 rxdesc = ((char *)packet - priv->rxbuffer) / ETH_BUF_SZ;
  420. struct xgmac_dma_desc *p = &priv->rx_chain[rxdesc];
  421. /* set descriptor back to owned by XGMAC */
  422. desc_set_rx_owner(p);
  423. writel(1, &regs->rxpoll);
  424. return 0;
  425. }
  426. static void xgmac_eth_stop(struct udevice *dev)
  427. {
  428. struct calxeda_eth_dev *priv = dev_get_priv(dev);
  429. struct eth_pdata *pdata = dev_get_plat(dev);
  430. struct xgmac_regs *regs = xgmac_get_regs(pdata);
  431. int value;
  432. /* Disable TX/RX */
  433. value = readl(&regs->config);
  434. value &= ~(RXENABLE | TXENABLE);
  435. writel(value, &regs->config);
  436. /* Disable DMA */
  437. value = readl(&regs->dma_opmode);
  438. value &= ~(RXSTART | TXSTART);
  439. writel(value, &regs->dma_opmode);
  440. /* must set to 0, or when started up will cause issues */
  441. priv->tx_currdesc = 0;
  442. priv->rx_currdesc = 0;
  443. }
  444. /*
  445. * Changing the MAC address is not a good idea, as the fabric would
  446. * need to know about this as well (it does not learn MAC addresses).
  447. */
  448. static int xgmac_eth_write_hwaddr(struct udevice *dev)
  449. {
  450. return -ENOSYS;
  451. }
  452. static int xgmac_eth_read_rom_hwaddr(struct udevice *dev)
  453. {
  454. struct eth_pdata *pdata = dev_get_plat(dev);
  455. struct xgmac_regs *regs = xgmac_get_regs(pdata);
  456. u32 macaddr[2];
  457. /* The MAC address is already configured, so read it from registers. */
  458. macaddr[1] = readl(&regs->macaddr[0].hi);
  459. macaddr[0] = readl(&regs->macaddr[0].lo);
  460. memcpy(pdata->enetaddr, macaddr, ARP_HLEN);
  461. return 0;
  462. }
  463. static int xgmac_ofdata_to_platdata(struct udevice *dev)
  464. {
  465. struct eth_pdata *pdata = dev_get_plat(dev);
  466. struct calxeda_eth_dev *priv;
  467. /* Structure must be aligned, because it contains the descriptors */
  468. priv = memalign(32, sizeof(*priv));
  469. if (!priv)
  470. return -ENOMEM;
  471. dev_set_priv(dev, priv);
  472. pdata->iobase = devfdt_get_addr(dev);
  473. if (pdata->iobase == FDT_ADDR_T_NONE) {
  474. printf("%s: Cannot find XGMAC base address\n", __func__);
  475. return -EINVAL;
  476. }
  477. if (pdata->iobase >= (1ULL << 32)) {
  478. printf("%s: MMIO base address cannot be above 4GB\n", __func__);
  479. return -EINVAL;
  480. }
  481. return 0;
  482. }
  483. static int xgmac_eth_probe(struct udevice *dev)
  484. {
  485. struct eth_pdata *pdata = dev_get_plat(dev);
  486. struct xgmac_regs *regs = xgmac_get_regs(pdata);
  487. /* check hardware version */
  488. if (readl(&regs->version) != 0x1012)
  489. return -ENODEV;
  490. xgmac_eth_read_rom_hwaddr(dev);
  491. return 0;
  492. }
  493. static const struct eth_ops xgmac_eth_ops = {
  494. .start = xgmac_eth_start,
  495. .send = xgmac_tx,
  496. .recv = xgmac_rx,
  497. .free_pkt = xgmac_free_pkt,
  498. .stop = xgmac_eth_stop,
  499. .write_hwaddr = xgmac_eth_write_hwaddr,
  500. .read_rom_hwaddr = xgmac_eth_read_rom_hwaddr,
  501. };
  502. static const struct udevice_id xgmac_eth_ids[] = {
  503. { .compatible = "calxeda,hb-xgmac" },
  504. { }
  505. };
  506. U_BOOT_DRIVER(eth_xgmac) = {
  507. .name = "eth_xgmac",
  508. .id = UCLASS_ETH,
  509. .of_match = xgmac_eth_ids,
  510. .of_to_plat = xgmac_ofdata_to_platdata,
  511. .probe = xgmac_eth_probe,
  512. .ops = &xgmac_eth_ops,
  513. .plat_auto = sizeof(struct eth_pdata),
  514. };