bcm6368-eth.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
  4. *
  5. * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c:
  6. * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <dma.h>
  12. #include <log.h>
  13. #include <malloc.h>
  14. #include <miiphy.h>
  15. #include <net.h>
  16. #include <reset.h>
  17. #include <wait_bit.h>
  18. #include <asm/io.h>
  19. #include <dm/device_compat.h>
  20. #include <linux/delay.h>
  21. #define ETH_PORT_STR "brcm,enetsw-port"
  22. #define ETH_RX_DESC PKTBUFSRX
  23. #define ETH_ZLEN 60
  24. #define ETH_TIMEOUT 100
  25. #define ETH_MAX_PORT 8
  26. #define ETH_RGMII_PORT0 4
  27. /* Port traffic control */
  28. #define ETH_PTCTRL_REG(x) (0x0 + (x))
  29. #define ETH_PTCTRL_RXDIS_SHIFT 0
  30. #define ETH_PTCTRL_RXDIS_MASK (1 << ETH_PTCTRL_RXDIS_SHIFT)
  31. #define ETH_PTCTRL_TXDIS_SHIFT 1
  32. #define ETH_PTCTRL_TXDIS_MASK (1 << ETH_PTCTRL_TXDIS_SHIFT)
  33. /* Switch mode register */
  34. #define ETH_SWMODE_REG 0xb
  35. #define ETH_SWMODE_FWD_EN_SHIFT 1
  36. #define ETH_SWMODE_FWD_EN_MASK (1 << ETH_SWMODE_FWD_EN_SHIFT)
  37. /* IMP override Register */
  38. #define ETH_IMPOV_REG 0xe
  39. #define ETH_IMPOV_LINKUP_SHIFT 0
  40. #define ETH_IMPOV_LINKUP_MASK (1 << ETH_IMPOV_LINKUP_SHIFT)
  41. #define ETH_IMPOV_FDX_SHIFT 1
  42. #define ETH_IMPOV_FDX_MASK (1 << ETH_IMPOV_FDX_SHIFT)
  43. #define ETH_IMPOV_100_SHIFT 2
  44. #define ETH_IMPOV_100_MASK (1 << ETH_IMPOV_100_SHIFT)
  45. #define ETH_IMPOV_1000_SHIFT 3
  46. #define ETH_IMPOV_1000_MASK (1 << ETH_IMPOV_1000_SHIFT)
  47. #define ETH_IMPOV_RXFLOW_SHIFT 4
  48. #define ETH_IMPOV_RXFLOW_MASK (1 << ETH_IMPOV_RXFLOW_SHIFT)
  49. #define ETH_IMPOV_TXFLOW_SHIFT 5
  50. #define ETH_IMPOV_TXFLOW_MASK (1 << ETH_IMPOV_TXFLOW_SHIFT)
  51. #define ETH_IMPOV_FORCE_SHIFT 7
  52. #define ETH_IMPOV_FORCE_MASK (1 << ETH_IMPOV_FORCE_SHIFT)
  53. /* Port override Register */
  54. #define ETH_PORTOV_REG(x) (0x58 + (x))
  55. #define ETH_PORTOV_LINKUP_SHIFT 0
  56. #define ETH_PORTOV_LINKUP_MASK (1 << ETH_PORTOV_LINKUP_SHIFT)
  57. #define ETH_PORTOV_FDX_SHIFT 1
  58. #define ETH_PORTOV_FDX_MASK (1 << ETH_PORTOV_FDX_SHIFT)
  59. #define ETH_PORTOV_100_SHIFT 2
  60. #define ETH_PORTOV_100_MASK (1 << ETH_PORTOV_100_SHIFT)
  61. #define ETH_PORTOV_1000_SHIFT 3
  62. #define ETH_PORTOV_1000_MASK (1 << ETH_PORTOV_1000_SHIFT)
  63. #define ETH_PORTOV_RXFLOW_SHIFT 4
  64. #define ETH_PORTOV_RXFLOW_MASK (1 << ETH_PORTOV_RXFLOW_SHIFT)
  65. #define ETH_PORTOV_TXFLOW_SHIFT 5
  66. #define ETH_PORTOV_TXFLOW_MASK (1 << ETH_PORTOV_TXFLOW_SHIFT)
  67. #define ETH_PORTOV_ENABLE_SHIFT 6
  68. #define ETH_PORTOV_ENABLE_MASK (1 << ETH_PORTOV_ENABLE_SHIFT)
  69. /* Port RGMII control register */
  70. #define ETH_RGMII_CTRL_REG(x) (0x60 + (x))
  71. #define ETH_RGMII_CTRL_GMII_CLK_EN (1 << 7)
  72. #define ETH_RGMII_CTRL_MII_OVERRIDE_EN (1 << 6)
  73. #define ETH_RGMII_CTRL_MII_MODE_MASK (3 << 4)
  74. #define ETH_RGMII_CTRL_RGMII_MODE (0 << 4)
  75. #define ETH_RGMII_CTRL_MII_MODE (1 << 4)
  76. #define ETH_RGMII_CTRL_RVMII_MODE (2 << 4)
  77. #define ETH_RGMII_CTRL_TIMING_SEL_EN (1 << 0)
  78. /* Port RGMII timing register */
  79. #define ENETSW_RGMII_TIMING_REG(x) (0x68 + (x))
  80. /* MDIO control register */
  81. #define MII_SC_REG 0xb0
  82. #define MII_SC_EXT_SHIFT 16
  83. #define MII_SC_EXT_MASK (1 << MII_SC_EXT_SHIFT)
  84. #define MII_SC_REG_SHIFT 20
  85. #define MII_SC_PHYID_SHIFT 25
  86. #define MII_SC_RD_SHIFT 30
  87. #define MII_SC_RD_MASK (1 << MII_SC_RD_SHIFT)
  88. #define MII_SC_WR_SHIFT 31
  89. #define MII_SC_WR_MASK (1 << MII_SC_WR_SHIFT)
  90. /* MDIO data register */
  91. #define MII_DAT_REG 0xb4
  92. /* Global Management Configuration Register */
  93. #define ETH_GMCR_REG 0x200
  94. #define ETH_GMCR_RST_MIB_SHIFT 0
  95. #define ETH_GMCR_RST_MIB_MASK (1 << ETH_GMCR_RST_MIB_SHIFT)
  96. /* Jumbo control register port mask register */
  97. #define ETH_JMBCTL_PORT_REG 0x4004
  98. /* Jumbo control mib good frame register */
  99. #define ETH_JMBCTL_MAXSIZE_REG 0x4008
  100. /* ETH port data */
  101. struct bcm_enetsw_port {
  102. bool used;
  103. const char *name;
  104. /* Config */
  105. bool bypass_link;
  106. int force_speed;
  107. bool force_duplex_full;
  108. /* PHY */
  109. int phy_id;
  110. };
  111. /* ETH data */
  112. struct bcm6368_eth_priv {
  113. void __iomem *base;
  114. /* DMA */
  115. struct dma rx_dma;
  116. struct dma tx_dma;
  117. /* Ports */
  118. uint8_t num_ports;
  119. struct bcm_enetsw_port used_ports[ETH_MAX_PORT];
  120. int sw_port_link[ETH_MAX_PORT];
  121. bool rgmii_override;
  122. bool rgmii_timing;
  123. /* PHY */
  124. int phy_id;
  125. };
  126. static inline bool bcm_enet_port_is_rgmii(int portid)
  127. {
  128. return portid >= ETH_RGMII_PORT0;
  129. }
  130. static int bcm6368_mdio_read(struct bcm6368_eth_priv *priv, uint8_t ext,
  131. int phy_id, int reg)
  132. {
  133. uint32_t val;
  134. writel_be(0, priv->base + MII_SC_REG);
  135. val = MII_SC_RD_MASK |
  136. (phy_id << MII_SC_PHYID_SHIFT) |
  137. (reg << MII_SC_REG_SHIFT);
  138. if (ext)
  139. val |= MII_SC_EXT_MASK;
  140. writel_be(val, priv->base + MII_SC_REG);
  141. udelay(50);
  142. return readw_be(priv->base + MII_DAT_REG);
  143. }
  144. static int bcm6368_mdio_write(struct bcm6368_eth_priv *priv, uint8_t ext,
  145. int phy_id, int reg, u16 data)
  146. {
  147. uint32_t val;
  148. writel_be(0, priv->base + MII_SC_REG);
  149. val = MII_SC_WR_MASK |
  150. (phy_id << MII_SC_PHYID_SHIFT) |
  151. (reg << MII_SC_REG_SHIFT);
  152. if (ext)
  153. val |= MII_SC_EXT_MASK;
  154. val |= data;
  155. writel_be(val, priv->base + MII_SC_REG);
  156. udelay(50);
  157. return 0;
  158. }
  159. static int bcm6368_eth_free_pkt(struct udevice *dev, uchar *packet, int len)
  160. {
  161. struct bcm6368_eth_priv *priv = dev_get_priv(dev);
  162. return dma_prepare_rcv_buf(&priv->rx_dma, packet, len);
  163. }
  164. static int bcm6368_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  165. {
  166. struct bcm6368_eth_priv *priv = dev_get_priv(dev);
  167. return dma_receive(&priv->rx_dma, (void**)packetp, NULL);
  168. }
  169. static int bcm6368_eth_send(struct udevice *dev, void *packet, int length)
  170. {
  171. struct bcm6368_eth_priv *priv = dev_get_priv(dev);
  172. /* pad packets smaller than ETH_ZLEN */
  173. if (length < ETH_ZLEN) {
  174. memset(packet + length, 0, ETH_ZLEN - length);
  175. length = ETH_ZLEN;
  176. }
  177. return dma_send(&priv->tx_dma, packet, length, NULL);
  178. }
  179. static int bcm6368_eth_adjust_link(struct udevice *dev)
  180. {
  181. struct bcm6368_eth_priv *priv = dev_get_priv(dev);
  182. unsigned int i;
  183. for (i = 0; i < priv->num_ports; i++) {
  184. struct bcm_enetsw_port *port;
  185. int val, j, up, adv, lpa, speed, duplex, media;
  186. int external_phy = bcm_enet_port_is_rgmii(i);
  187. u8 override;
  188. port = &priv->used_ports[i];
  189. if (!port->used)
  190. continue;
  191. if (port->bypass_link)
  192. continue;
  193. /* dummy read to clear */
  194. for (j = 0; j < 2; j++)
  195. val = bcm6368_mdio_read(priv, external_phy,
  196. port->phy_id, MII_BMSR);
  197. if (val == 0xffff)
  198. continue;
  199. up = (val & BMSR_LSTATUS) ? 1 : 0;
  200. if (!(up ^ priv->sw_port_link[i]))
  201. continue;
  202. priv->sw_port_link[i] = up;
  203. /* link changed */
  204. if (!up) {
  205. dev_info(dev, "link DOWN on %s\n", port->name);
  206. writeb_be(ETH_PORTOV_ENABLE_MASK,
  207. priv->base + ETH_PORTOV_REG(i));
  208. writeb_be(ETH_PTCTRL_RXDIS_MASK |
  209. ETH_PTCTRL_TXDIS_MASK,
  210. priv->base + ETH_PTCTRL_REG(i));
  211. continue;
  212. }
  213. adv = bcm6368_mdio_read(priv, external_phy,
  214. port->phy_id, MII_ADVERTISE);
  215. lpa = bcm6368_mdio_read(priv, external_phy, port->phy_id,
  216. MII_LPA);
  217. /* figure out media and duplex from advertise and LPA values */
  218. media = mii_nway_result(lpa & adv);
  219. duplex = (media & ADVERTISE_FULL) ? 1 : 0;
  220. if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
  221. speed = 100;
  222. else
  223. speed = 10;
  224. if (val & BMSR_ESTATEN) {
  225. adv = bcm6368_mdio_read(priv, external_phy,
  226. port->phy_id, MII_CTRL1000);
  227. lpa = bcm6368_mdio_read(priv, external_phy,
  228. port->phy_id, MII_STAT1000);
  229. if ((adv & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
  230. (lpa & (LPA_1000FULL | LPA_1000HALF))) {
  231. speed = 1000;
  232. duplex = (lpa & LPA_1000FULL);
  233. }
  234. }
  235. pr_alert("link UP on %s, %dMbps, %s-duplex\n",
  236. port->name, speed, duplex ? "full" : "half");
  237. override = ETH_PORTOV_ENABLE_MASK |
  238. ETH_PORTOV_LINKUP_MASK;
  239. if (speed == 1000)
  240. override |= ETH_PORTOV_1000_MASK;
  241. else if (speed == 100)
  242. override |= ETH_PORTOV_100_MASK;
  243. if (duplex)
  244. override |= ETH_PORTOV_FDX_MASK;
  245. writeb_be(override, priv->base + ETH_PORTOV_REG(i));
  246. writeb_be(0, priv->base + ETH_PTCTRL_REG(i));
  247. }
  248. return 0;
  249. }
  250. static int bcm6368_eth_start(struct udevice *dev)
  251. {
  252. struct bcm6368_eth_priv *priv = dev_get_priv(dev);
  253. uint8_t i;
  254. /* disable all ports */
  255. for (i = 0; i < priv->num_ports; i++) {
  256. setbits_8(priv->base + ETH_PORTOV_REG(i),
  257. ETH_PORTOV_ENABLE_MASK);
  258. setbits_8(priv->base + ETH_PTCTRL_REG(i),
  259. ETH_PTCTRL_RXDIS_MASK | ETH_PTCTRL_TXDIS_MASK);
  260. priv->sw_port_link[i] = 0;
  261. }
  262. /* enable external ports */
  263. for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) {
  264. u8 rgmii_ctrl = ETH_RGMII_CTRL_GMII_CLK_EN;
  265. if (!priv->used_ports[i].used)
  266. continue;
  267. if (priv->rgmii_override)
  268. rgmii_ctrl |= ETH_RGMII_CTRL_MII_OVERRIDE_EN;
  269. if (priv->rgmii_timing)
  270. rgmii_ctrl |= ETH_RGMII_CTRL_TIMING_SEL_EN;
  271. setbits_8(priv->base + ETH_RGMII_CTRL_REG(i), rgmii_ctrl);
  272. }
  273. /* reset mib */
  274. setbits_8(priv->base + ETH_GMCR_REG, ETH_GMCR_RST_MIB_MASK);
  275. mdelay(1);
  276. clrbits_8(priv->base + ETH_GMCR_REG, ETH_GMCR_RST_MIB_MASK);
  277. mdelay(1);
  278. /* force CPU port state */
  279. setbits_8(priv->base + ETH_IMPOV_REG,
  280. ETH_IMPOV_FORCE_MASK | ETH_IMPOV_LINKUP_MASK);
  281. /* enable switch forward engine */
  282. setbits_8(priv->base + ETH_SWMODE_REG, ETH_SWMODE_FWD_EN_MASK);
  283. /* prepare rx dma buffers */
  284. for (i = 0; i < ETH_RX_DESC; i++) {
  285. int ret = dma_prepare_rcv_buf(&priv->rx_dma, net_rx_packets[i],
  286. PKTSIZE_ALIGN);
  287. if (ret < 0)
  288. break;
  289. }
  290. /* enable dma rx channel */
  291. dma_enable(&priv->rx_dma);
  292. /* enable dma tx channel */
  293. dma_enable(&priv->tx_dma);
  294. /* apply override config for bypass_link ports here. */
  295. for (i = 0; i < priv->num_ports; i++) {
  296. struct bcm_enetsw_port *port;
  297. u8 override;
  298. port = &priv->used_ports[i];
  299. if (!port->used)
  300. continue;
  301. if (!port->bypass_link)
  302. continue;
  303. override = ETH_PORTOV_ENABLE_MASK |
  304. ETH_PORTOV_LINKUP_MASK;
  305. switch (port->force_speed) {
  306. case 1000:
  307. override |= ETH_PORTOV_1000_MASK;
  308. break;
  309. case 100:
  310. override |= ETH_PORTOV_100_MASK;
  311. break;
  312. case 10:
  313. break;
  314. default:
  315. pr_warn("%s: invalid forced speed on port %s\n",
  316. __func__, port->name);
  317. break;
  318. }
  319. if (port->force_duplex_full)
  320. override |= ETH_PORTOV_FDX_MASK;
  321. writeb_be(override, priv->base + ETH_PORTOV_REG(i));
  322. writeb_be(0, priv->base + ETH_PTCTRL_REG(i));
  323. }
  324. bcm6368_eth_adjust_link(dev);
  325. return 0;
  326. }
  327. static void bcm6368_eth_stop(struct udevice *dev)
  328. {
  329. struct bcm6368_eth_priv *priv = dev_get_priv(dev);
  330. uint8_t i;
  331. /* disable all ports */
  332. for (i = 0; i < priv->num_ports; i++) {
  333. setbits_8(priv->base + ETH_PORTOV_REG(i),
  334. ETH_PORTOV_ENABLE_MASK);
  335. setbits_8(priv->base + ETH_PTCTRL_REG(i),
  336. ETH_PTCTRL_RXDIS_MASK | ETH_PTCTRL_TXDIS_MASK);
  337. }
  338. /* disable external ports */
  339. for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) {
  340. if (!priv->used_ports[i].used)
  341. continue;
  342. clrbits_8(priv->base + ETH_RGMII_CTRL_REG(i),
  343. ETH_RGMII_CTRL_GMII_CLK_EN);
  344. }
  345. /* disable CPU port */
  346. clrbits_8(priv->base + ETH_IMPOV_REG,
  347. ETH_IMPOV_FORCE_MASK | ETH_IMPOV_LINKUP_MASK);
  348. /* disable switch forward engine */
  349. clrbits_8(priv->base + ETH_SWMODE_REG, ETH_SWMODE_FWD_EN_MASK);
  350. /* disable dma rx channel */
  351. dma_disable(&priv->rx_dma);
  352. /* disable dma tx channel */
  353. dma_disable(&priv->tx_dma);
  354. }
  355. static const struct eth_ops bcm6368_eth_ops = {
  356. .free_pkt = bcm6368_eth_free_pkt,
  357. .recv = bcm6368_eth_recv,
  358. .send = bcm6368_eth_send,
  359. .start = bcm6368_eth_start,
  360. .stop = bcm6368_eth_stop,
  361. };
  362. static const struct udevice_id bcm6368_eth_ids[] = {
  363. { .compatible = "brcm,bcm6368-enet", },
  364. { /* sentinel */ }
  365. };
  366. static bool bcm6368_phy_is_external(struct bcm6368_eth_priv *priv, int phy_id)
  367. {
  368. uint8_t i;
  369. for (i = 0; i < priv->num_ports; ++i) {
  370. if (!priv->used_ports[i].used)
  371. continue;
  372. if (priv->used_ports[i].phy_id == phy_id)
  373. return bcm_enet_port_is_rgmii(i);
  374. }
  375. return true;
  376. }
  377. static int bcm6368_mii_mdio_read(struct mii_dev *bus, int addr, int devaddr,
  378. int reg)
  379. {
  380. struct bcm6368_eth_priv *priv = bus->priv;
  381. bool ext = bcm6368_phy_is_external(priv, addr);
  382. return bcm6368_mdio_read(priv, ext, addr, reg);
  383. }
  384. static int bcm6368_mii_mdio_write(struct mii_dev *bus, int addr, int devaddr,
  385. int reg, u16 data)
  386. {
  387. struct bcm6368_eth_priv *priv = bus->priv;
  388. bool ext = bcm6368_phy_is_external(priv, addr);
  389. return bcm6368_mdio_write(priv, ext, addr, reg, data);
  390. }
  391. static int bcm6368_mdio_init(const char *name, struct bcm6368_eth_priv *priv)
  392. {
  393. struct mii_dev *bus;
  394. bus = mdio_alloc();
  395. if (!bus) {
  396. pr_err("%s: failed to allocate MDIO bus\n", __func__);
  397. return -ENOMEM;
  398. }
  399. bus->read = bcm6368_mii_mdio_read;
  400. bus->write = bcm6368_mii_mdio_write;
  401. bus->priv = priv;
  402. snprintf(bus->name, sizeof(bus->name), "%s", name);
  403. return mdio_register(bus);
  404. }
  405. static int bcm6368_eth_probe(struct udevice *dev)
  406. {
  407. struct eth_pdata *pdata = dev_get_plat(dev);
  408. struct bcm6368_eth_priv *priv = dev_get_priv(dev);
  409. int num_ports, ret, i;
  410. ofnode node;
  411. /* get base address */
  412. priv->base = dev_remap_addr(dev);
  413. if (!priv->base)
  414. return -EINVAL;
  415. pdata->iobase = (phys_addr_t) priv->base;
  416. /* get number of ports */
  417. num_ports = dev_read_u32_default(dev, "brcm,num-ports", ETH_MAX_PORT);
  418. if (!num_ports || num_ports > ETH_MAX_PORT)
  419. return -EINVAL;
  420. /* get dma channels */
  421. ret = dma_get_by_name(dev, "tx", &priv->tx_dma);
  422. if (ret)
  423. return -EINVAL;
  424. ret = dma_get_by_name(dev, "rx", &priv->rx_dma);
  425. if (ret)
  426. return -EINVAL;
  427. /* try to enable clocks */
  428. for (i = 0; ; i++) {
  429. struct clk clk;
  430. int ret;
  431. ret = clk_get_by_index(dev, i, &clk);
  432. if (ret < 0)
  433. break;
  434. ret = clk_enable(&clk);
  435. if (ret < 0) {
  436. pr_err("%s: error enabling clock %d\n", __func__, i);
  437. return ret;
  438. }
  439. ret = clk_free(&clk);
  440. if (ret < 0) {
  441. pr_err("%s: error freeing clock %d\n", __func__, i);
  442. return ret;
  443. }
  444. }
  445. /* try to perform resets */
  446. for (i = 0; ; i++) {
  447. struct reset_ctl reset;
  448. int ret;
  449. ret = reset_get_by_index(dev, i, &reset);
  450. if (ret < 0)
  451. break;
  452. ret = reset_deassert(&reset);
  453. if (ret < 0) {
  454. pr_err("%s: error deasserting reset %d\n", __func__, i);
  455. return ret;
  456. }
  457. ret = reset_free(&reset);
  458. if (ret < 0) {
  459. pr_err("%s: error freeing reset %d\n", __func__, i);
  460. return ret;
  461. }
  462. }
  463. /* set priv data */
  464. priv->num_ports = num_ports;
  465. if (dev_read_bool(dev, "brcm,rgmii-override"))
  466. priv->rgmii_override = true;
  467. if (dev_read_bool(dev, "brcm,rgmii-timing"))
  468. priv->rgmii_timing = true;
  469. /* get ports */
  470. dev_for_each_subnode(node, dev) {
  471. const char *comp;
  472. const char *label;
  473. unsigned int p;
  474. int phy_id;
  475. int speed;
  476. comp = ofnode_read_string(node, "compatible");
  477. if (!comp || memcmp(comp, ETH_PORT_STR, sizeof(ETH_PORT_STR)))
  478. continue;
  479. p = ofnode_read_u32_default(node, "reg", ETH_MAX_PORT);
  480. if (p >= num_ports)
  481. return -EINVAL;
  482. label = ofnode_read_string(node, "label");
  483. if (!label) {
  484. debug("%s: node %s has no label\n", __func__,
  485. ofnode_get_name(node));
  486. return -EINVAL;
  487. }
  488. phy_id = ofnode_read_u32_default(node, "brcm,phy-id", -1);
  489. priv->used_ports[p].used = true;
  490. priv->used_ports[p].name = label;
  491. priv->used_ports[p].phy_id = phy_id;
  492. if (ofnode_read_bool(node, "full-duplex"))
  493. priv->used_ports[p].force_duplex_full = true;
  494. if (ofnode_read_bool(node, "bypass-link"))
  495. priv->used_ports[p].bypass_link = true;
  496. speed = ofnode_read_u32_default(node, "speed", 0);
  497. if (speed)
  498. priv->used_ports[p].force_speed = speed;
  499. }
  500. /* init mii bus */
  501. ret = bcm6368_mdio_init(dev->name, priv);
  502. if (ret)
  503. return ret;
  504. /* enable jumbo on all ports */
  505. writel_be(0x1ff, priv->base + ETH_JMBCTL_PORT_REG);
  506. writew_be(9728, priv->base + ETH_JMBCTL_MAXSIZE_REG);
  507. return 0;
  508. }
  509. U_BOOT_DRIVER(bcm6368_eth) = {
  510. .name = "bcm6368_eth",
  511. .id = UCLASS_ETH,
  512. .of_match = bcm6368_eth_ids,
  513. .ops = &bcm6368_eth_ops,
  514. .plat_auto = sizeof(struct eth_pdata),
  515. .priv_auto = sizeof(struct bcm6368_eth_priv),
  516. .probe = bcm6368_eth_probe,
  517. };