bcm6348-eth.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
  4. *
  5. * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c:
  6. * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <dma.h>
  12. #include <log.h>
  13. #include <malloc.h>
  14. #include <miiphy.h>
  15. #include <net.h>
  16. #include <phy.h>
  17. #include <reset.h>
  18. #include <wait_bit.h>
  19. #include <asm/io.h>
  20. #define ETH_RX_DESC PKTBUFSRX
  21. #define ETH_MAX_MTU_SIZE 1518
  22. #define ETH_TIMEOUT 100
  23. #define ETH_TX_WATERMARK 32
  24. /* ETH Receiver Configuration register */
  25. #define ETH_RXCFG_REG 0x00
  26. #define ETH_RXCFG_ENFLOW_SHIFT 5
  27. #define ETH_RXCFG_ENFLOW_MASK (1 << ETH_RXCFG_ENFLOW_SHIFT)
  28. /* ETH Receive Maximum Length register */
  29. #define ETH_RXMAXLEN_REG 0x04
  30. #define ETH_RXMAXLEN_SHIFT 0
  31. #define ETH_RXMAXLEN_MASK (0x7ff << ETH_RXMAXLEN_SHIFT)
  32. /* ETH Transmit Maximum Length register */
  33. #define ETH_TXMAXLEN_REG 0x08
  34. #define ETH_TXMAXLEN_SHIFT 0
  35. #define ETH_TXMAXLEN_MASK (0x7ff << ETH_TXMAXLEN_SHIFT)
  36. /* MII Status/Control register */
  37. #define MII_SC_REG 0x10
  38. #define MII_SC_MDCFREQDIV_SHIFT 0
  39. #define MII_SC_MDCFREQDIV_MASK (0x7f << MII_SC_MDCFREQDIV_SHIFT)
  40. #define MII_SC_PREAMBLE_EN_SHIFT 7
  41. #define MII_SC_PREAMBLE_EN_MASK (1 << MII_SC_PREAMBLE_EN_SHIFT)
  42. /* MII Data register */
  43. #define MII_DAT_REG 0x14
  44. #define MII_DAT_DATA_SHIFT 0
  45. #define MII_DAT_DATA_MASK (0xffff << MII_DAT_DATA_SHIFT)
  46. #define MII_DAT_TA_SHIFT 16
  47. #define MII_DAT_TA_MASK (0x3 << MII_DAT_TA_SHIFT)
  48. #define MII_DAT_REG_SHIFT 18
  49. #define MII_DAT_REG_MASK (0x1f << MII_DAT_REG_SHIFT)
  50. #define MII_DAT_PHY_SHIFT 23
  51. #define MII_DAT_PHY_MASK (0x1f << MII_DAT_PHY_SHIFT)
  52. #define MII_DAT_OP_SHIFT 28
  53. #define MII_DAT_OP_WRITE (0x5 << MII_DAT_OP_SHIFT)
  54. #define MII_DAT_OP_READ (0x6 << MII_DAT_OP_SHIFT)
  55. /* ETH Interrupts Mask register */
  56. #define ETH_IRMASK_REG 0x18
  57. /* ETH Interrupts register */
  58. #define ETH_IR_REG 0x1c
  59. #define ETH_IR_MII_SHIFT 0
  60. #define ETH_IR_MII_MASK (1 << ETH_IR_MII_SHIFT)
  61. /* ETH Control register */
  62. #define ETH_CTL_REG 0x2c
  63. #define ETH_CTL_ENABLE_SHIFT 0
  64. #define ETH_CTL_ENABLE_MASK (1 << ETH_CTL_ENABLE_SHIFT)
  65. #define ETH_CTL_DISABLE_SHIFT 1
  66. #define ETH_CTL_DISABLE_MASK (1 << ETH_CTL_DISABLE_SHIFT)
  67. #define ETH_CTL_RESET_SHIFT 2
  68. #define ETH_CTL_RESET_MASK (1 << ETH_CTL_RESET_SHIFT)
  69. #define ETH_CTL_EPHY_SHIFT 3
  70. #define ETH_CTL_EPHY_MASK (1 << ETH_CTL_EPHY_SHIFT)
  71. /* ETH Transmit Control register */
  72. #define ETH_TXCTL_REG 0x30
  73. #define ETH_TXCTL_FD_SHIFT 0
  74. #define ETH_TXCTL_FD_MASK (1 << ETH_TXCTL_FD_SHIFT)
  75. /* ETH Transmit Watermask register */
  76. #define ETH_TXWMARK_REG 0x34
  77. #define ETH_TXWMARK_WM_SHIFT 0
  78. #define ETH_TXWMARK_WM_MASK (0x3f << ETH_TXWMARK_WM_SHIFT)
  79. /* MIB Control register */
  80. #define MIB_CTL_REG 0x38
  81. #define MIB_CTL_RDCLEAR_SHIFT 0
  82. #define MIB_CTL_RDCLEAR_MASK (1 << MIB_CTL_RDCLEAR_SHIFT)
  83. /* ETH Perfect Match registers */
  84. #define ETH_PM_CNT 4
  85. #define ETH_PML_REG(x) (0x58 + (x) * 0x8)
  86. #define ETH_PMH_REG(x) (0x5c + (x) * 0x8)
  87. #define ETH_PMH_VALID_SHIFT 16
  88. #define ETH_PMH_VALID_MASK (1 << ETH_PMH_VALID_SHIFT)
  89. /* MIB Counters registers */
  90. #define MIB_REG_CNT 55
  91. #define MIB_REG(x) (0x200 + (x) * 4)
  92. /* ETH data */
  93. struct bcm6348_eth_priv {
  94. void __iomem *base;
  95. /* DMA */
  96. struct dma rx_dma;
  97. struct dma tx_dma;
  98. /* PHY */
  99. int phy_id;
  100. struct phy_device *phy_dev;
  101. };
  102. static void bcm6348_eth_mac_disable(struct bcm6348_eth_priv *priv)
  103. {
  104. /* disable emac */
  105. clrsetbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_ENABLE_MASK,
  106. ETH_CTL_DISABLE_MASK);
  107. /* wait until emac is disabled */
  108. if (wait_for_bit_be32(priv->base + ETH_CTL_REG,
  109. ETH_CTL_DISABLE_MASK, false,
  110. ETH_TIMEOUT, false))
  111. pr_err("%s: error disabling emac\n", __func__);
  112. }
  113. static void bcm6348_eth_mac_enable(struct bcm6348_eth_priv *priv)
  114. {
  115. setbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_ENABLE_MASK);
  116. }
  117. static void bcm6348_eth_mac_reset(struct bcm6348_eth_priv *priv)
  118. {
  119. /* reset emac */
  120. writel_be(ETH_CTL_RESET_MASK, priv->base + ETH_CTL_REG);
  121. wmb();
  122. /* wait until emac is reset */
  123. if (wait_for_bit_be32(priv->base + ETH_CTL_REG,
  124. ETH_CTL_RESET_MASK, false,
  125. ETH_TIMEOUT, false))
  126. pr_err("%s: error resetting emac\n", __func__);
  127. }
  128. static int bcm6348_eth_free_pkt(struct udevice *dev, uchar *packet, int len)
  129. {
  130. struct bcm6348_eth_priv *priv = dev_get_priv(dev);
  131. return dma_prepare_rcv_buf(&priv->rx_dma, packet, len);
  132. }
  133. static int bcm6348_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  134. {
  135. struct bcm6348_eth_priv *priv = dev_get_priv(dev);
  136. return dma_receive(&priv->rx_dma, (void**)packetp, NULL);
  137. }
  138. static int bcm6348_eth_send(struct udevice *dev, void *packet, int length)
  139. {
  140. struct bcm6348_eth_priv *priv = dev_get_priv(dev);
  141. return dma_send(&priv->tx_dma, packet, length, NULL);
  142. }
  143. static int bcm6348_eth_adjust_link(struct udevice *dev,
  144. struct phy_device *phydev)
  145. {
  146. struct bcm6348_eth_priv *priv = dev_get_priv(dev);
  147. /* mac duplex parameters */
  148. if (phydev->duplex)
  149. setbits_be32(priv->base + ETH_TXCTL_REG, ETH_TXCTL_FD_MASK);
  150. else
  151. clrbits_be32(priv->base + ETH_TXCTL_REG, ETH_TXCTL_FD_MASK);
  152. /* rx flow control (pause frame handling) */
  153. if (phydev->pause)
  154. setbits_be32(priv->base + ETH_RXCFG_REG,
  155. ETH_RXCFG_ENFLOW_MASK);
  156. else
  157. clrbits_be32(priv->base + ETH_RXCFG_REG,
  158. ETH_RXCFG_ENFLOW_MASK);
  159. return 0;
  160. }
  161. static int bcm6348_eth_start(struct udevice *dev)
  162. {
  163. struct bcm6348_eth_priv *priv = dev_get_priv(dev);
  164. int ret, i;
  165. /* prepare rx dma buffers */
  166. for (i = 0; i < ETH_RX_DESC; i++) {
  167. ret = dma_prepare_rcv_buf(&priv->rx_dma, net_rx_packets[i],
  168. PKTSIZE_ALIGN);
  169. if (ret < 0)
  170. break;
  171. }
  172. /* enable dma rx channel */
  173. dma_enable(&priv->rx_dma);
  174. /* enable dma tx channel */
  175. dma_enable(&priv->tx_dma);
  176. ret = phy_startup(priv->phy_dev);
  177. if (ret) {
  178. pr_err("%s: could not initialize phy\n", __func__);
  179. return ret;
  180. }
  181. if (!priv->phy_dev->link) {
  182. pr_err("%s: no phy link\n", __func__);
  183. return -EIO;
  184. }
  185. bcm6348_eth_adjust_link(dev, priv->phy_dev);
  186. /* zero mib counters */
  187. for (i = 0; i < MIB_REG_CNT; i++)
  188. writel_be(0, MIB_REG(i));
  189. /* enable rx flow control */
  190. setbits_be32(priv->base + ETH_RXCFG_REG, ETH_RXCFG_ENFLOW_MASK);
  191. /* set max rx/tx length */
  192. writel_be((ETH_MAX_MTU_SIZE << ETH_RXMAXLEN_SHIFT) &
  193. ETH_RXMAXLEN_MASK, priv->base + ETH_RXMAXLEN_REG);
  194. writel_be((ETH_MAX_MTU_SIZE << ETH_TXMAXLEN_SHIFT) &
  195. ETH_TXMAXLEN_MASK, priv->base + ETH_TXMAXLEN_REG);
  196. /* set correct transmit fifo watermark */
  197. writel_be((ETH_TX_WATERMARK << ETH_TXWMARK_WM_SHIFT) &
  198. ETH_TXWMARK_WM_MASK, priv->base + ETH_TXWMARK_REG);
  199. /* enable emac */
  200. bcm6348_eth_mac_enable(priv);
  201. /* clear interrupts */
  202. writel_be(0, priv->base + ETH_IRMASK_REG);
  203. return 0;
  204. }
  205. static void bcm6348_eth_stop(struct udevice *dev)
  206. {
  207. struct bcm6348_eth_priv *priv = dev_get_priv(dev);
  208. /* disable dma rx channel */
  209. dma_disable(&priv->rx_dma);
  210. /* disable dma tx channel */
  211. dma_disable(&priv->tx_dma);
  212. /* disable emac */
  213. bcm6348_eth_mac_disable(priv);
  214. }
  215. static int bcm6348_eth_write_hwaddr(struct udevice *dev)
  216. {
  217. struct eth_pdata *pdata = dev_get_plat(dev);
  218. struct bcm6348_eth_priv *priv = dev_get_priv(dev);
  219. bool running = false;
  220. /* check if emac is running */
  221. if (readl_be(priv->base + ETH_CTL_REG) & ETH_CTL_ENABLE_MASK)
  222. running = true;
  223. /* disable emac */
  224. if (running)
  225. bcm6348_eth_mac_disable(priv);
  226. /* set mac address */
  227. writel_be((pdata->enetaddr[2] << 24) | (pdata->enetaddr[3]) << 16 |
  228. (pdata->enetaddr[4]) << 8 | (pdata->enetaddr[5]),
  229. priv->base + ETH_PML_REG(0));
  230. writel_be((pdata->enetaddr[1]) | (pdata->enetaddr[0] << 8) |
  231. ETH_PMH_VALID_MASK, priv->base + ETH_PMH_REG(0));
  232. /* enable emac */
  233. if (running)
  234. bcm6348_eth_mac_enable(priv);
  235. return 0;
  236. }
  237. static const struct eth_ops bcm6348_eth_ops = {
  238. .free_pkt = bcm6348_eth_free_pkt,
  239. .recv = bcm6348_eth_recv,
  240. .send = bcm6348_eth_send,
  241. .start = bcm6348_eth_start,
  242. .stop = bcm6348_eth_stop,
  243. .write_hwaddr = bcm6348_eth_write_hwaddr,
  244. };
  245. static const struct udevice_id bcm6348_eth_ids[] = {
  246. { .compatible = "brcm,bcm6348-enet", },
  247. { /* sentinel */ }
  248. };
  249. static int bcm6348_mdio_op(void __iomem *base, uint32_t data)
  250. {
  251. /* make sure mii interrupt status is cleared */
  252. writel_be(ETH_IR_MII_MASK, base + ETH_IR_REG);
  253. /* issue mii op */
  254. writel_be(data, base + MII_DAT_REG);
  255. /* wait until emac is disabled */
  256. return wait_for_bit_be32(base + ETH_IR_REG,
  257. ETH_IR_MII_MASK, true,
  258. ETH_TIMEOUT, false);
  259. }
  260. static int bcm6348_mdio_read(struct mii_dev *bus, int addr, int devaddr,
  261. int reg)
  262. {
  263. void __iomem *base = bus->priv;
  264. uint32_t val;
  265. val = MII_DAT_OP_READ;
  266. val |= (reg << MII_DAT_REG_SHIFT) & MII_DAT_REG_MASK;
  267. val |= (0x2 << MII_DAT_TA_SHIFT) & MII_DAT_TA_MASK;
  268. val |= (addr << MII_DAT_PHY_SHIFT) & MII_DAT_PHY_MASK;
  269. if (bcm6348_mdio_op(base, val)) {
  270. pr_err("%s: timeout\n", __func__);
  271. return -EINVAL;
  272. }
  273. val = readl_be(base + MII_DAT_REG) & MII_DAT_DATA_MASK;
  274. val >>= MII_DAT_DATA_SHIFT;
  275. return val;
  276. }
  277. static int bcm6348_mdio_write(struct mii_dev *bus, int addr, int dev_addr,
  278. int reg, u16 value)
  279. {
  280. void __iomem *base = bus->priv;
  281. uint32_t val;
  282. val = MII_DAT_OP_WRITE;
  283. val |= (reg << MII_DAT_REG_SHIFT) & MII_DAT_REG_MASK;
  284. val |= (0x2 << MII_DAT_TA_SHIFT) & MII_DAT_TA_MASK;
  285. val |= (addr << MII_DAT_PHY_SHIFT) & MII_DAT_PHY_MASK;
  286. val |= (value << MII_DAT_DATA_SHIFT) & MII_DAT_DATA_MASK;
  287. if (bcm6348_mdio_op(base, val)) {
  288. pr_err("%s: timeout\n", __func__);
  289. return -EINVAL;
  290. }
  291. return 0;
  292. }
  293. static int bcm6348_mdio_init(const char *name, void __iomem *base)
  294. {
  295. struct mii_dev *bus;
  296. bus = mdio_alloc();
  297. if (!bus) {
  298. pr_err("%s: failed to allocate MDIO bus\n", __func__);
  299. return -ENOMEM;
  300. }
  301. bus->read = bcm6348_mdio_read;
  302. bus->write = bcm6348_mdio_write;
  303. bus->priv = base;
  304. snprintf(bus->name, sizeof(bus->name), "%s", name);
  305. return mdio_register(bus);
  306. }
  307. static int bcm6348_phy_init(struct udevice *dev)
  308. {
  309. struct eth_pdata *pdata = dev_get_plat(dev);
  310. struct bcm6348_eth_priv *priv = dev_get_priv(dev);
  311. struct mii_dev *bus;
  312. /* get mii bus */
  313. bus = miiphy_get_dev_by_name(dev->name);
  314. /* phy connect */
  315. priv->phy_dev = phy_connect(bus, priv->phy_id, dev,
  316. pdata->phy_interface);
  317. if (!priv->phy_dev) {
  318. pr_err("%s: no phy device\n", __func__);
  319. return -ENODEV;
  320. }
  321. priv->phy_dev->supported = (SUPPORTED_10baseT_Half |
  322. SUPPORTED_10baseT_Full |
  323. SUPPORTED_100baseT_Half |
  324. SUPPORTED_100baseT_Full |
  325. SUPPORTED_Autoneg |
  326. SUPPORTED_Pause |
  327. SUPPORTED_MII);
  328. priv->phy_dev->advertising = priv->phy_dev->supported;
  329. /* phy config */
  330. phy_config(priv->phy_dev);
  331. return 0;
  332. }
  333. static int bcm6348_eth_probe(struct udevice *dev)
  334. {
  335. struct eth_pdata *pdata = dev_get_plat(dev);
  336. struct bcm6348_eth_priv *priv = dev_get_priv(dev);
  337. struct ofnode_phandle_args phy;
  338. const char *phy_mode;
  339. int ret, i;
  340. /* get base address */
  341. priv->base = dev_remap_addr(dev);
  342. if (!priv->base)
  343. return -EINVAL;
  344. pdata->iobase = (phys_addr_t) priv->base;
  345. /* get phy mode */
  346. pdata->phy_interface = PHY_INTERFACE_MODE_NONE;
  347. phy_mode = dev_read_string(dev, "phy-mode");
  348. if (phy_mode)
  349. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  350. if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
  351. return -ENODEV;
  352. /* get phy */
  353. if (dev_read_phandle_with_args(dev, "phy", NULL, 0, 0, &phy))
  354. return -ENOENT;
  355. priv->phy_id = ofnode_read_u32_default(phy.node, "reg", -1);
  356. /* get dma channels */
  357. ret = dma_get_by_name(dev, "tx", &priv->tx_dma);
  358. if (ret)
  359. return -EINVAL;
  360. ret = dma_get_by_name(dev, "rx", &priv->rx_dma);
  361. if (ret)
  362. return -EINVAL;
  363. /* try to enable clocks */
  364. for (i = 0; ; i++) {
  365. struct clk clk;
  366. int ret;
  367. ret = clk_get_by_index(dev, i, &clk);
  368. if (ret < 0)
  369. break;
  370. ret = clk_enable(&clk);
  371. if (ret < 0) {
  372. pr_err("%s: error enabling clock %d\n", __func__, i);
  373. return ret;
  374. }
  375. ret = clk_free(&clk);
  376. if (ret < 0) {
  377. pr_err("%s: error freeing clock %d\n", __func__, i);
  378. return ret;
  379. }
  380. }
  381. /* try to perform resets */
  382. for (i = 0; ; i++) {
  383. struct reset_ctl reset;
  384. int ret;
  385. ret = reset_get_by_index(dev, i, &reset);
  386. if (ret < 0)
  387. break;
  388. ret = reset_deassert(&reset);
  389. if (ret < 0) {
  390. pr_err("%s: error deasserting reset %d\n", __func__, i);
  391. return ret;
  392. }
  393. ret = reset_free(&reset);
  394. if (ret < 0) {
  395. pr_err("%s: error freeing reset %d\n", __func__, i);
  396. return ret;
  397. }
  398. }
  399. /* disable emac */
  400. bcm6348_eth_mac_disable(priv);
  401. /* reset emac */
  402. bcm6348_eth_mac_reset(priv);
  403. /* select correct mii interface */
  404. if (pdata->phy_interface == PHY_INTERFACE_MODE_INTERNAL)
  405. clrbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_EPHY_MASK);
  406. else
  407. setbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_EPHY_MASK);
  408. /* turn on mdc clock */
  409. writel_be((0x1f << MII_SC_MDCFREQDIV_SHIFT) |
  410. MII_SC_PREAMBLE_EN_MASK, priv->base + MII_SC_REG);
  411. /* set mib counters to not clear when read */
  412. clrbits_be32(priv->base + MIB_CTL_REG, MIB_CTL_RDCLEAR_MASK);
  413. /* initialize perfect match registers */
  414. for (i = 0; i < ETH_PM_CNT; i++) {
  415. writel_be(0, priv->base + ETH_PML_REG(i));
  416. writel_be(0, priv->base + ETH_PMH_REG(i));
  417. }
  418. /* init mii bus */
  419. ret = bcm6348_mdio_init(dev->name, priv->base);
  420. if (ret)
  421. return ret;
  422. /* init phy */
  423. ret = bcm6348_phy_init(dev);
  424. if (ret)
  425. return ret;
  426. return 0;
  427. }
  428. U_BOOT_DRIVER(bcm6348_eth) = {
  429. .name = "bcm6348_eth",
  430. .id = UCLASS_ETH,
  431. .of_match = bcm6348_eth_ids,
  432. .ops = &bcm6348_eth_ops,
  433. .plat_auto = sizeof(struct eth_pdata),
  434. .priv_auto = sizeof(struct bcm6348_eth_priv),
  435. .probe = bcm6348_eth_probe,
  436. };