ax88180.h 12 KB

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  1. /* ax88180.h: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */
  2. /*
  3. *
  4. * This program is free software; you can distribute it and/or modify it
  5. * under the terms of the GNU General Public License (Version 2) as
  6. * published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  11. * for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License along
  14. * with this program; if not, write to the Free Software Foundation, Inc.,
  15. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  16. *
  17. */
  18. #ifndef _AX88180_H_
  19. #define _AX88180_H_
  20. #include <asm/io.h>
  21. #include <asm/types.h>
  22. #include <config.h>
  23. typedef enum _ax88180_link_state {
  24. INS_LINK_DOWN,
  25. INS_LINK_UP,
  26. INS_LINK_UNKNOWN
  27. } ax88180_link_state;
  28. struct ax88180_private {
  29. unsigned char BusWidth;
  30. unsigned char PadSize;
  31. unsigned short PhyAddr;
  32. unsigned short PhyID0;
  33. unsigned short PhyID1;
  34. unsigned short FirstTxDesc;
  35. unsigned short NextTxDesc;
  36. ax88180_link_state LinkState;
  37. };
  38. #define BUS_WIDTH_16 1
  39. #define BUS_WIDTH_32 2
  40. #define ENABLE_JUMBO 1
  41. #define DISABLE_JUMBO 0
  42. #define ENABLE_BURST 1
  43. #define DISABLE_BURST 0
  44. #define NORMAL_RX_MODE 0
  45. #define RX_LOOPBACK_MODE 1
  46. #define RX_INIFINIT_LOOP_MODE 2
  47. #define TX_INIFINIT_LOOP_MODE 3
  48. #define DEFAULT_ETH_MTU 1500
  49. /* Jumbo packet size 4086 bytes included 4 bytes CRC*/
  50. #define MAX_JUMBO_MTU 4072
  51. /* Max Tx Jumbo size 4086 bytes included 4 bytes CRC */
  52. #define MAX_TX_JUMBO_SIZE 4086
  53. /* Max Rx Jumbo size is 15K Bytes */
  54. #define MAX_RX_SIZE 0x3C00
  55. #define MARVELL_ALASKA_PHYSID0 0x141
  56. #define MARVELL_88E1118_PHYSID1 0xE40
  57. #define CICADA_CIS8201_PHYSID0 0x000F
  58. #define MEDIA_AUTO 0
  59. #define MEDIA_1000FULL 1
  60. #define MEDIA_1000HALF 2
  61. #define MEDIA_100FULL 3
  62. #define MEDIA_100HALF 4
  63. #define MEDIA_10FULL 5
  64. #define MEDIA_10HALF 6
  65. #define MEDIA_UNKNOWN 7
  66. #define AUTO_MEDIA 0
  67. #define FORCE_MEDIA 1
  68. #define TXDP_MASK 3
  69. #define TXDP0 0
  70. #define TXDP1 1
  71. #define TXDP2 2
  72. #define TXDP3 3
  73. #define CMD_MAP_SIZE 0x100
  74. #if defined (CONFIG_DRIVER_AX88180_16BIT)
  75. #define AX88180_MEMORY_SIZE 0x00004000
  76. #define START_BASE 0x1000
  77. #define RX_BUF_SIZE 0x1000
  78. #define TX_BUF_SIZE 0x0F00
  79. #define TX_BASE START_BASE
  80. #define CMD_BASE (TX_BASE + TX_BUF_SIZE)
  81. #define RX_BASE (CMD_BASE + CMD_MAP_SIZE)
  82. #else
  83. #define AX88180_MEMORY_SIZE 0x00010000
  84. #define RX_BUF_SIZE 0x8000
  85. #define TX_BUF_SIZE 0x7C00
  86. #define RX_BASE 0x0000
  87. #define TX_BASE (RX_BASE + RX_BUF_SIZE)
  88. #define CMD_BASE (TX_BASE + TX_BUF_SIZE)
  89. #endif
  90. /* AX88180 Memory Mapping Definition */
  91. #define RXBUFFER_START RX_BASE
  92. #define RX_PACKET_LEN_OFFSET 0
  93. #define RX_PAGE_NUM_MASK 0x7FF /* RX pages 0~7FFh */
  94. #define TXBUFFER_START TX_BASE
  95. /* AX88180 MAC Register Definition */
  96. #define DECODE (0)
  97. #define DECODE_EN 0x00000001
  98. #define BASE (6)
  99. #define CMD (CMD_BASE + 0x0000)
  100. #define WAKEMOD 0x00000001
  101. #define TXEN 0x00000100
  102. #define RXEN 0x00000200
  103. #define DEFAULT_CMD WAKEMOD
  104. #define IMR (CMD_BASE + 0x0004)
  105. #define IMR_RXBUFFOVR 0x00000001
  106. #define IMR_WATCHDOG 0x00000002
  107. #define IMR_TX 0x00000008
  108. #define IMR_RX 0x00000010
  109. #define IMR_PHY 0x00000020
  110. #define CLEAR_IMR 0x00000000
  111. #define DEFAULT_IMR (IMR_PHY | IMR_RX | IMR_TX |\
  112. IMR_RXBUFFOVR | IMR_WATCHDOG)
  113. #define ISR (CMD_BASE + 0x0008)
  114. #define ISR_RXBUFFOVR 0x00000001
  115. #define ISR_WATCHDOG 0x00000002
  116. #define ISR_TX 0x00000008
  117. #define ISR_RX 0x00000010
  118. #define ISR_PHY 0x00000020
  119. #define TXCFG (CMD_BASE + 0x0010)
  120. #define AUTOPAD_CRC 0x00000050
  121. #define DEFAULT_TXCFG AUTOPAD_CRC
  122. #define TXCMD (CMD_BASE + 0x0014)
  123. #define TXCMD_TXDP_MASK 0x00006000
  124. #define TXCMD_TXDP0 0x00000000
  125. #define TXCMD_TXDP1 0x00002000
  126. #define TXCMD_TXDP2 0x00004000
  127. #define TXCMD_TXDP3 0x00006000
  128. #define TX_START_WRITE 0x00008000
  129. #define TX_STOP_WRITE 0x00000000
  130. #define DEFAULT_TXCMD 0x00000000
  131. #define TXBS (CMD_BASE + 0x0018)
  132. #define TXDP0_USED 0x00000001
  133. #define TXDP1_USED 0x00000002
  134. #define TXDP2_USED 0x00000004
  135. #define TXDP3_USED 0x00000008
  136. #define DEFAULT_TXBS 0x00000000
  137. #define TXDES0 (CMD_BASE + 0x0020)
  138. #define TXDPx_ENABLE 0x00008000
  139. #define TXDPx_LEN_MASK 0x00001FFF
  140. #define DEFAULT_TXDES0 0x00000000
  141. #define TXDES1 (CMD_BASE + 0x0024)
  142. #define TXDPx_ENABLE 0x00008000
  143. #define TXDPx_LEN_MASK 0x00001FFF
  144. #define DEFAULT_TXDES1 0x00000000
  145. #define TXDES2 (CMD_BASE + 0x0028)
  146. #define TXDPx_ENABLE 0x00008000
  147. #define TXDPx_LEN_MASK 0x00001FFF
  148. #define DEFAULT_TXDES2 0x00000000
  149. #define TXDES3 (CMD_BASE + 0x002C)
  150. #define TXDPx_ENABLE 0x00008000
  151. #define TXDPx_LEN_MASK 0x00001FFF
  152. #define DEFAULT_TXDES3 0x00000000
  153. #define RXCFG (CMD_BASE + 0x0030)
  154. #define RXBUFF_PROTECT 0x00000001
  155. #define RXTCPCRC_CHECK 0x00000010
  156. #define RXFLOW_ENABLE 0x00000100
  157. #define DEFAULT_RXCFG RXBUFF_PROTECT
  158. #define RXCURT (CMD_BASE + 0x0034)
  159. #define DEFAULT_RXCURT 0x00000000
  160. #define RXBOUND (CMD_BASE + 0x0038)
  161. #define DEFAULT_RXBOUND 0x7FF /* RX pages 0~7FFh */
  162. #define MACCFG0 (CMD_BASE + 0x0040)
  163. #define MACCFG0_BIT3_0 0x00000007
  164. #define IPGT_VAL 0x00000150
  165. #define TXFLOW_ENABLE 0x00001000
  166. #define SPEED100 0x00008000
  167. #define DEFAULT_MACCFG0 (IPGT_VAL | MACCFG0_BIT3_0)
  168. #define MACCFG1 (CMD_BASE + 0x0044)
  169. #define RGMII_EN 0x00000002
  170. #define RXFLOW_EN 0x00000020
  171. #define FULLDUPLEX 0x00000040
  172. #define MAX_JUMBO_LEN 0x00000780
  173. #define RXJUMBO_EN 0x00000800
  174. #define GIGA_MODE_EN 0x00001000
  175. #define RXCRC_CHECK 0x00002000
  176. #define RXPAUSE_DA_CHECK 0x00004000
  177. #define JUMBO_LEN_4K 0x00000200
  178. #define JUMBO_LEN_15K 0x00000780
  179. #define DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK | \
  180. RGMII_EN)
  181. #define CICADA_DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK)
  182. #define MACCFG2 (CMD_BASE + 0x0048)
  183. #define MACCFG2_BIT15_8 0x00000100
  184. #define JAM_LIMIT_MASK 0x000000FC
  185. #define DEFAULT_JAM_LIMIT 0x00000064
  186. #define DEFAULT_MACCFG2 MACCFG2_BIT15_8
  187. #define MACCFG3 (CMD_BASE + 0x004C)
  188. #define IPGR2_VAL 0x0000000E
  189. #define IPGR1_VAL 0x00000600
  190. #define NOABORT 0x00008000
  191. #define DEFAULT_MACCFG3 (IPGR1_VAL | IPGR2_VAL)
  192. #define TXPAUT (CMD_BASE + 0x0054)
  193. #define DEFAULT_TXPAUT 0x001FE000
  194. #define RXBTHD0 (CMD_BASE + 0x0058)
  195. #define DEFAULT_RXBTHD0 0x00000300
  196. #define RXBTHD1 (CMD_BASE + 0x005C)
  197. #define DEFAULT_RXBTHD1 0x00000600
  198. #define RXFULTHD (CMD_BASE + 0x0060)
  199. #define DEFAULT_RXFULTHD 0x00000100
  200. #define MISC (CMD_BASE + 0x0068)
  201. /* Normal operation mode */
  202. #define MISC_NORMAL 0x00000003
  203. /* Clear bit 0 to reset MAC */
  204. #define MISC_RESET_MAC 0x00000002
  205. /* Clear bit 1 to reset PHY */
  206. #define MISC_RESET_PHY 0x00000001
  207. /* Clear bit 0 and 1 to reset MAC and PHY */
  208. #define MISC_RESET_MAC_PHY 0x00000000
  209. #define DEFAULT_MISC MISC_NORMAL
  210. #define MACID0 (CMD_BASE + 0x0070)
  211. #define MACID1 (CMD_BASE + 0x0074)
  212. #define MACID2 (CMD_BASE + 0x0078)
  213. #define TXLEN (CMD_BASE + 0x007C)
  214. #define DEFAULT_TXLEN 0x000005FC
  215. #define RXFILTER (CMD_BASE + 0x0080)
  216. #define RX_RXANY 0x00000001
  217. #define RX_MULTICAST 0x00000002
  218. #define RX_UNICAST 0x00000004
  219. #define RX_BROADCAST 0x00000008
  220. #define RX_MULTI_HASH 0x00000010
  221. #define DISABLE_RXFILTER 0x00000000
  222. #define DEFAULT_RXFILTER (RX_BROADCAST + RX_UNICAST)
  223. #define MDIOCTRL (CMD_BASE + 0x0084)
  224. #define PHY_ADDR_MASK 0x0000001F
  225. #define REG_ADDR_MASK 0x00001F00
  226. #define READ_PHY 0x00004000
  227. #define WRITE_PHY 0x00008000
  228. #define MDIODP (CMD_BASE + 0x0088)
  229. #define GPIOCTRL (CMD_BASE + 0x008C)
  230. #define RXINDICATOR (CMD_BASE + 0x0090)
  231. #define RX_START_READ 0x00000001
  232. #define RX_STOP_READ 0x00000000
  233. #define DEFAULT_RXINDICATOR RX_STOP_READ
  234. #define TXST (CMD_BASE + 0x0094)
  235. #define MDCCLKPAT (CMD_BASE + 0x00A0)
  236. #define RXIPCRCCNT (CMD_BASE + 0x00A4)
  237. #define RXCRCCNT (CMD_BASE + 0x00A8)
  238. #define TXFAILCNT (CMD_BASE + 0x00AC)
  239. #define PROMDP (CMD_BASE + 0x00B0)
  240. #define PROMCTRL (CMD_BASE + 0x00B4)
  241. #define RELOAD_EEPROM 0x00000200
  242. #define MAXRXLEN (CMD_BASE + 0x00B8)
  243. #define HASHTAB0 (CMD_BASE + 0x00C0)
  244. #define HASHTAB1 (CMD_BASE + 0x00C4)
  245. #define HASHTAB2 (CMD_BASE + 0x00C8)
  246. #define HASHTAB3 (CMD_BASE + 0x00CC)
  247. #define DOGTHD0 (CMD_BASE + 0x00E0)
  248. #define DEFAULT_DOGTHD0 0x0000FFFF
  249. #define DOGTHD1 (CMD_BASE + 0x00E4)
  250. #define START_WATCHDOG_TIMER 0x00008000
  251. #define DEFAULT_DOGTHD1 0x00000FFF
  252. #define SOFTRST (CMD_BASE + 0x00EC)
  253. #define SOFTRST_NORMAL 0x00000003
  254. #define SOFTRST_RESET_MAC 0x00000002
  255. /* Marvell 88E1111 Gigabit PHY Register Definition */
  256. #define M88_SSR 0x0011
  257. #define SSR_SPEED_MASK 0xC000
  258. #define SSR_SPEED_1000 0x8000
  259. #define SSR_SPEED_100 0x4000
  260. #define SSR_SPEED_10 0x0000
  261. #define SSR_DUPLEX 0x2000
  262. #define SSR_MEDIA_RESOLVED_OK 0x0800
  263. #define SSR_MEDIA_MASK (SSR_SPEED_MASK | SSR_DUPLEX)
  264. #define SSR_1000FULL (SSR_SPEED_1000 | SSR_DUPLEX)
  265. #define SSR_1000HALF SSR_SPEED_1000
  266. #define SSR_100FULL (SSR_SPEED_100 | SSR_DUPLEX)
  267. #define SSR_100HALF SSR_SPEED_100
  268. #define SSR_10FULL (SSR_SPEED_10 | SSR_DUPLEX)
  269. #define SSR_10HALF SSR_SPEED_10
  270. #define M88_IER 0x0012
  271. #define LINK_CHANGE_INT 0x0400
  272. #define M88_ISR 0x0013
  273. #define LINK_CHANGE_STATUS 0x0400
  274. #define M88E1111_EXT_SCR 0x0014
  275. #define RGMII_RXCLK_DELAY 0x0080
  276. #define RGMII_TXCLK_DELAY 0x0002
  277. #define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY)
  278. #define M88E1111_EXT_SSR 0x001B
  279. #define HWCFG_MODE_MASK 0x000F
  280. #define RGMII_COPPER_MODE 0x000B
  281. /* Marvell 88E1118 Gigabit PHY Register Definition */
  282. #define M88E1118_CR 0x14
  283. #define M88E1118_CR_RGMII_RXCLK_DELAY 0x0020
  284. #define M88E1118_CR_RGMII_TXCLK_DELAY 0x0010
  285. #define M88E1118_CR_DEFAULT (M88E1118_CR_RGMII_TXCLK_DELAY | \
  286. M88E1118_CR_RGMII_RXCLK_DELAY)
  287. #define M88E1118_LEDCTL 0x10 /* Reg 16 on page 3 */
  288. #define M88E1118_LEDCTL_LED2INT 0x200
  289. #define M88E1118_LEDCTL_LED2BLNK 0x400
  290. #define M88E1118_LEDCTL_LED0DUALMODE1 0xc
  291. #define M88E1118_LEDCTL_LED0DUALMODE2 0xd
  292. #define M88E1118_LEDCTL_LED0DUALMODE3 0xe
  293. #define M88E1118_LEDCTL_LED0DUALMODE4 0xf
  294. #define M88E1118_LEDCTL_DEFAULT (M88E1118_LEDCTL_LED2BLNK | \
  295. M88E1118_LEDCTL_LED0DUALMODE4)
  296. #define M88E1118_LEDMIX 0x11 /* Reg 17 on page 3 */
  297. #define M88E1118_LEDMIX_LED050 0x4
  298. #define M88E1118_LEDMIX_LED150 0x8
  299. #define M88E1118_PAGE_SEL 0x16 /* Reg page select */
  300. /* CICADA CIS8201 Gigabit PHY Register Definition */
  301. #define CIS_IMR 0x0019
  302. #define CIS_INT_ENABLE 0x8000
  303. #define CIS_LINK_CHANGE_INT 0x2000
  304. #define CIS_ISR 0x001A
  305. #define CIS_INT_PENDING 0x8000
  306. #define CIS_LINK_CHANGE_STATUS 0x2000
  307. #define CIS_AUX_CTRL_STATUS 0x001C
  308. #define CIS_AUTONEG_COMPLETE 0x8000
  309. #define CIS_SPEED_MASK 0x0018
  310. #define CIS_SPEED_1000 0x0010
  311. #define CIS_SPEED_100 0x0008
  312. #define CIS_SPEED_10 0x0000
  313. #define CIS_DUPLEX 0x0020
  314. #define CIS_MEDIA_MASK (CIS_SPEED_MASK | CIS_DUPLEX)
  315. #define CIS_1000FULL (CIS_SPEED_1000 | CIS_DUPLEX)
  316. #define CIS_1000HALF CIS_SPEED_1000
  317. #define CIS_100FULL (CIS_SPEED_100 | CIS_DUPLEX)
  318. #define CIS_100HALF CIS_SPEED_100
  319. #define CIS_10FULL (CIS_SPEED_10 | CIS_DUPLEX)
  320. #define CIS_10HALF CIS_SPEED_10
  321. #define CIS_SMI_PRIORITY 0x0004
  322. static inline unsigned short INW (struct eth_device *dev, unsigned long addr)
  323. {
  324. return le16_to_cpu(readw(addr + (void *)dev->iobase));
  325. }
  326. /*
  327. Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer
  328. */
  329. #if defined (CONFIG_DRIVER_AX88180_16BIT)
  330. static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
  331. {
  332. writew(cpu_to_le16(command), addr + (void *)dev->iobase);
  333. }
  334. static inline unsigned short READ_RXBUF (struct eth_device *dev)
  335. {
  336. return le16_to_cpu(readw(RXBUFFER_START + (void *)dev->iobase));
  337. }
  338. static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data)
  339. {
  340. writew(cpu_to_le16(data), TXBUFFER_START + (void *)dev->iobase);
  341. }
  342. #else
  343. static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
  344. {
  345. writel(cpu_to_le32(command), addr + (void *)dev->iobase);
  346. }
  347. static inline unsigned long READ_RXBUF (struct eth_device *dev)
  348. {
  349. return le32_to_cpu(readl(RXBUFFER_START + (void *)dev->iobase));
  350. }
  351. static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data)
  352. {
  353. writel(cpu_to_le32(data), TXBUFFER_START + (void *)dev->iobase);
  354. }
  355. #endif
  356. #endif /* _AX88180_H_ */