at91_emac.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2009 BuS Elektronik GmbH & Co. KG
  4. * Jens Scharsig (esw@bus-elektronik.de)
  5. *
  6. * (C) Copyright 2003
  7. * Author : Hamid Ikdoumi (Atmel)
  8. */
  9. #include <common.h>
  10. #include <log.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/hardware.h>
  13. #include <asm/arch/at91_emac.h>
  14. #include <asm/arch/clk.h>
  15. #include <asm/arch/at91_pio.h>
  16. #include <net.h>
  17. #include <netdev.h>
  18. #include <malloc.h>
  19. #include <miiphy.h>
  20. #include <linux/delay.h>
  21. #include <linux/mii.h>
  22. #undef MII_DEBUG
  23. #undef ET_DEBUG
  24. #if (CONFIG_SYS_RX_ETH_BUFFER > 1024)
  25. #error AT91 EMAC supports max 1024 RX buffers. \
  26. Please decrease the CONFIG_SYS_RX_ETH_BUFFER value
  27. #endif
  28. #ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR
  29. #define CONFIG_DRIVER_AT91EMAC_PHYADDR 0
  30. #endif
  31. /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
  32. #if (AT91C_MASTER_CLOCK > 80000000)
  33. #define HCLK_DIV AT91_EMAC_CFG_MCLK_64
  34. #elif (AT91C_MASTER_CLOCK > 40000000)
  35. #define HCLK_DIV AT91_EMAC_CFG_MCLK_32
  36. #elif (AT91C_MASTER_CLOCK > 20000000)
  37. #define HCLK_DIV AT91_EMAC_CFG_MCLK_16
  38. #else
  39. #define HCLK_DIV AT91_EMAC_CFG_MCLK_8
  40. #endif
  41. #ifdef ET_DEBUG
  42. #define DEBUG_AT91EMAC 1
  43. #else
  44. #define DEBUG_AT91EMAC 0
  45. #endif
  46. #ifdef MII_DEBUG
  47. #define DEBUG_AT91PHY 1
  48. #else
  49. #define DEBUG_AT91PHY 0
  50. #endif
  51. #ifndef CONFIG_DRIVER_AT91EMAC_QUIET
  52. #define VERBOSEP 1
  53. #else
  54. #define VERBOSEP 0
  55. #endif
  56. #define RBF_ADDR 0xfffffffc
  57. #define RBF_OWNER (1<<0)
  58. #define RBF_WRAP (1<<1)
  59. #define RBF_BROADCAST (1<<31)
  60. #define RBF_MULTICAST (1<<30)
  61. #define RBF_UNICAST (1<<29)
  62. #define RBF_EXTERNAL (1<<28)
  63. #define RBF_UNKNOWN (1<<27)
  64. #define RBF_SIZE 0x07ff
  65. #define RBF_LOCAL4 (1<<26)
  66. #define RBF_LOCAL3 (1<<25)
  67. #define RBF_LOCAL2 (1<<24)
  68. #define RBF_LOCAL1 (1<<23)
  69. #define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER
  70. #define RBF_FRAMELEN 0x600
  71. typedef struct {
  72. unsigned long addr, size;
  73. } rbf_t;
  74. typedef struct {
  75. rbf_t rbfdt[RBF_FRAMEMAX];
  76. unsigned long rbindex;
  77. } emac_device;
  78. void at91emac_EnableMDIO(at91_emac_t *at91mac)
  79. {
  80. /* Mac CTRL reg set for MDIO enable */
  81. writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl);
  82. }
  83. void at91emac_DisableMDIO(at91_emac_t *at91mac)
  84. {
  85. /* Mac CTRL reg set for MDIO disable */
  86. writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl);
  87. }
  88. int at91emac_read(at91_emac_t *at91mac, unsigned char addr,
  89. unsigned char reg, unsigned short *value)
  90. {
  91. unsigned long netstat;
  92. at91emac_EnableMDIO(at91mac);
  93. writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R |
  94. AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
  95. AT91_EMAC_MAN_PHYA(addr),
  96. &at91mac->man);
  97. do {
  98. netstat = readl(&at91mac->sr);
  99. debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
  100. } while (!(netstat & AT91_EMAC_SR_IDLE));
  101. *value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK;
  102. at91emac_DisableMDIO(at91mac);
  103. debug_cond(DEBUG_AT91PHY,
  104. "AT91PHY read %p REG(%d)=%x\n", at91mac, reg, *value);
  105. return 0;
  106. }
  107. int at91emac_write(at91_emac_t *at91mac, unsigned char addr,
  108. unsigned char reg, unsigned short value)
  109. {
  110. unsigned long netstat;
  111. debug_cond(DEBUG_AT91PHY,
  112. "AT91PHY write %p REG(%d)=%p\n", at91mac, reg, &value);
  113. at91emac_EnableMDIO(at91mac);
  114. writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W |
  115. AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
  116. AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK),
  117. &at91mac->man);
  118. do {
  119. netstat = readl(&at91mac->sr);
  120. debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
  121. } while (!(netstat & AT91_EMAC_SR_IDLE));
  122. at91emac_DisableMDIO(at91mac);
  123. return 0;
  124. }
  125. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  126. at91_emac_t *get_emacbase_by_name(const char *devname)
  127. {
  128. struct eth_device *netdev;
  129. netdev = eth_get_dev_by_name(devname);
  130. return (at91_emac_t *) netdev->iobase;
  131. }
  132. int at91emac_mii_read(struct mii_dev *bus, int addr, int devad, int reg)
  133. {
  134. unsigned short value = 0;
  135. at91_emac_t *emac;
  136. emac = get_emacbase_by_name(bus->name);
  137. at91emac_read(emac , addr, reg, &value);
  138. return value;
  139. }
  140. int at91emac_mii_write(struct mii_dev *bus, int addr, int devad, int reg,
  141. u16 value)
  142. {
  143. at91_emac_t *emac;
  144. emac = get_emacbase_by_name(bus->name);
  145. at91emac_write(emac, addr, reg, value);
  146. return 0;
  147. }
  148. #endif
  149. static int at91emac_phy_reset(struct eth_device *netdev)
  150. {
  151. int i;
  152. u16 status, adv;
  153. at91_emac_t *emac;
  154. emac = (at91_emac_t *) netdev->iobase;
  155. adv = ADVERTISE_CSMA | ADVERTISE_ALL;
  156. at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
  157. MII_ADVERTISE, adv);
  158. debug_cond(VERBOSEP, "%s: Starting autonegotiation...\n", netdev->name);
  159. at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
  160. (BMCR_ANENABLE | BMCR_ANRESTART));
  161. for (i = 0; i < 30000; i++) {
  162. at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
  163. MII_BMSR, &status);
  164. if (status & BMSR_ANEGCOMPLETE)
  165. break;
  166. udelay(100);
  167. }
  168. if (status & BMSR_ANEGCOMPLETE) {
  169. debug_cond(VERBOSEP,
  170. "%s: Autonegotiation complete\n", netdev->name);
  171. } else {
  172. printf("%s: Autonegotiation timed out (status=0x%04x)\n",
  173. netdev->name, status);
  174. return -1;
  175. }
  176. return 0;
  177. }
  178. static int at91emac_phy_init(struct eth_device *netdev)
  179. {
  180. u16 phy_id, status, adv, lpa;
  181. int media, speed, duplex;
  182. int i;
  183. at91_emac_t *emac;
  184. emac = (at91_emac_t *) netdev->iobase;
  185. /* Check if the PHY is up to snuff... */
  186. at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
  187. MII_PHYSID1, &phy_id);
  188. if (phy_id == 0xffff) {
  189. printf("%s: No PHY present\n", netdev->name);
  190. return -1;
  191. }
  192. at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
  193. MII_BMSR, &status);
  194. if (!(status & BMSR_LSTATUS)) {
  195. /* Try to re-negotiate if we don't have link already. */
  196. if (at91emac_phy_reset(netdev))
  197. return -2;
  198. for (i = 0; i < 100000 / 100; i++) {
  199. at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
  200. MII_BMSR, &status);
  201. if (status & BMSR_LSTATUS)
  202. break;
  203. udelay(100);
  204. }
  205. }
  206. if (!(status & BMSR_LSTATUS)) {
  207. debug_cond(VERBOSEP, "%s: link down\n", netdev->name);
  208. return -3;
  209. } else {
  210. at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
  211. MII_ADVERTISE, &adv);
  212. at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
  213. MII_LPA, &lpa);
  214. media = mii_nway_result(lpa & adv);
  215. speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
  216. ? 1 : 0);
  217. duplex = (media & ADVERTISE_FULL) ? 1 : 0;
  218. debug_cond(VERBOSEP, "%s: link up, %sMbps %s-duplex\n",
  219. netdev->name,
  220. speed ? "100" : "10",
  221. duplex ? "full" : "half");
  222. }
  223. return 0;
  224. }
  225. int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
  226. {
  227. unsigned short stat1;
  228. at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
  229. if (!(stat1 & BMSR_LSTATUS)) /* link status up? */
  230. return -1;
  231. if (stat1 & BMSR_100FULL) {
  232. /*set Emac for 100BaseTX and Full Duplex */
  233. writel(readl(&emac->cfg) |
  234. AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD,
  235. &emac->cfg);
  236. return 0;
  237. }
  238. if (stat1 & BMSR_10FULL) {
  239. /*set MII for 10BaseT and Full Duplex */
  240. writel((readl(&emac->cfg) &
  241. ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
  242. ) | AT91_EMAC_CFG_FD,
  243. &emac->cfg);
  244. return 0;
  245. }
  246. if (stat1 & BMSR_100HALF) {
  247. /*set MII for 100BaseTX and Half Duplex */
  248. writel((readl(&emac->cfg) &
  249. ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
  250. ) | AT91_EMAC_CFG_SPD,
  251. &emac->cfg);
  252. return 0;
  253. }
  254. if (stat1 & BMSR_10HALF) {
  255. /*set MII for 10BaseT and Half Duplex */
  256. writel((readl(&emac->cfg) &
  257. ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)),
  258. &emac->cfg);
  259. return 0;
  260. }
  261. return 0;
  262. }
  263. static int at91emac_init(struct eth_device *netdev, struct bd_info *bd)
  264. {
  265. int i;
  266. u32 value;
  267. emac_device *dev;
  268. at91_emac_t *emac;
  269. at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
  270. emac = (at91_emac_t *) netdev->iobase;
  271. dev = (emac_device *) netdev->priv;
  272. /* PIO Disable Register */
  273. value = ATMEL_PMX_AA_EMDIO | ATMEL_PMX_AA_EMDC |
  274. ATMEL_PMX_AA_ERXER | ATMEL_PMX_AA_ERX1 |
  275. ATMEL_PMX_AA_ERX0 | ATMEL_PMX_AA_ECRS |
  276. ATMEL_PMX_AA_ETX1 | ATMEL_PMX_AA_ETX0 |
  277. ATMEL_PMX_AA_ETXEN | ATMEL_PMX_AA_EREFCK;
  278. writel(value, &pio->pioa.pdr);
  279. writel(value, &pio->pioa.mux.pio2.asr);
  280. #ifdef CONFIG_RMII
  281. value = ATMEL_PMX_BA_ERXCK;
  282. #else
  283. value = ATMEL_PMX_BA_ERXCK | ATMEL_PMX_BA_ECOL |
  284. ATMEL_PMX_BA_ERXDV | ATMEL_PMX_BA_ERX3 |
  285. ATMEL_PMX_BA_ERX2 | ATMEL_PMX_BA_ETXER |
  286. ATMEL_PMX_BA_ETX3 | ATMEL_PMX_BA_ETX2;
  287. #endif
  288. writel(value, &pio->piob.pdr);
  289. writel(value, &pio->piob.mux.pio2.bsr);
  290. at91_periph_clk_enable(ATMEL_ID_EMAC);
  291. writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl);
  292. /* Init Ethernet buffers */
  293. for (i = 0; i < RBF_FRAMEMAX; i++) {
  294. dev->rbfdt[i].addr = (unsigned long) net_rx_packets[i];
  295. dev->rbfdt[i].size = 0;
  296. }
  297. dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
  298. dev->rbindex = 0;
  299. writel((u32) &(dev->rbfdt[0]), &emac->rbqp);
  300. writel(readl(&emac->rsr) &
  301. ~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA),
  302. &emac->rsr);
  303. value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC |
  304. HCLK_DIV;
  305. #ifdef CONFIG_RMII
  306. value |= AT91_EMAC_CFG_RMII;
  307. #endif
  308. writel(value, &emac->cfg);
  309. writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE,
  310. &emac->ctl);
  311. if (!at91emac_phy_init(netdev)) {
  312. at91emac_UpdateLinkSpeed(emac);
  313. return 0;
  314. }
  315. return -1;
  316. }
  317. static void at91emac_halt(struct eth_device *netdev)
  318. {
  319. at91_emac_t *emac;
  320. emac = (at91_emac_t *) netdev->iobase;
  321. writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE),
  322. &emac->ctl);
  323. debug_cond(DEBUG_AT91EMAC, "halt MAC\n");
  324. }
  325. static int at91emac_send(struct eth_device *netdev, void *packet, int length)
  326. {
  327. at91_emac_t *emac;
  328. emac = (at91_emac_t *) netdev->iobase;
  329. while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ))
  330. ;
  331. writel((u32) packet, &emac->tar);
  332. writel(AT91_EMAC_TCR_LEN(length), &emac->tcr);
  333. while (AT91_EMAC_TCR_LEN(readl(&emac->tcr)))
  334. ;
  335. debug_cond(DEBUG_AT91EMAC, "Send %d\n", length);
  336. writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr);
  337. return 0;
  338. }
  339. static int at91emac_recv(struct eth_device *netdev)
  340. {
  341. emac_device *dev;
  342. at91_emac_t *emac;
  343. rbf_t *rbfp;
  344. int size;
  345. emac = (at91_emac_t *) netdev->iobase;
  346. dev = (emac_device *) netdev->priv;
  347. rbfp = &dev->rbfdt[dev->rbindex];
  348. while (rbfp->addr & RBF_OWNER) {
  349. size = rbfp->size & RBF_SIZE;
  350. net_process_received_packet(net_rx_packets[dev->rbindex], size);
  351. debug_cond(DEBUG_AT91EMAC, "Recv[%ld]: %d bytes @ %lx\n",
  352. dev->rbindex, size, rbfp->addr);
  353. rbfp->addr &= ~RBF_OWNER;
  354. rbfp->size = 0;
  355. if (dev->rbindex < (RBF_FRAMEMAX-1))
  356. dev->rbindex++;
  357. else
  358. dev->rbindex = 0;
  359. rbfp = &(dev->rbfdt[dev->rbindex]);
  360. if (!(rbfp->addr & RBF_OWNER))
  361. writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC,
  362. &emac->rsr);
  363. }
  364. if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) {
  365. /* EMAC silicon bug 41.3.1 workaround 1 */
  366. writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl);
  367. writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl);
  368. dev->rbindex = 0;
  369. printf("%s: reset receiver (EMAC dead lock bug)\n",
  370. netdev->name);
  371. }
  372. return 0;
  373. }
  374. static int at91emac_write_hwaddr(struct eth_device *netdev)
  375. {
  376. at91_emac_t *emac;
  377. emac = (at91_emac_t *) netdev->iobase;
  378. at91_periph_clk_enable(ATMEL_ID_EMAC);
  379. debug_cond(DEBUG_AT91EMAC,
  380. "init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n",
  381. netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3],
  382. netdev->enetaddr[2], netdev->enetaddr[1], netdev->enetaddr[0]);
  383. writel( (netdev->enetaddr[0] | netdev->enetaddr[1] << 8 |
  384. netdev->enetaddr[2] << 16 | netdev->enetaddr[3] << 24),
  385. &emac->sa2l);
  386. writel((netdev->enetaddr[4] | netdev->enetaddr[5] << 8), &emac->sa2h);
  387. debug_cond(DEBUG_AT91EMAC, "init MAC-ADDR %x%x\n",
  388. readl(&emac->sa2h), readl(&emac->sa2l));
  389. return 0;
  390. }
  391. int at91emac_register(struct bd_info *bis, unsigned long iobase)
  392. {
  393. emac_device *emac;
  394. emac_device *emacfix;
  395. struct eth_device *dev;
  396. if (iobase == 0)
  397. iobase = ATMEL_BASE_EMAC;
  398. emac = malloc(sizeof(*emac)+512);
  399. if (emac == NULL)
  400. return -1;
  401. dev = malloc(sizeof(*dev));
  402. if (dev == NULL) {
  403. free(emac);
  404. return -1;
  405. }
  406. /* alignment as per Errata (64 bytes) is insufficient! */
  407. emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00);
  408. memset(emacfix, 0, sizeof(emac_device));
  409. memset(dev, 0, sizeof(*dev));
  410. strcpy(dev->name, "emac");
  411. dev->iobase = iobase;
  412. dev->priv = emacfix;
  413. dev->init = at91emac_init;
  414. dev->halt = at91emac_halt;
  415. dev->send = at91emac_send;
  416. dev->recv = at91emac_recv;
  417. dev->write_hwaddr = at91emac_write_hwaddr;
  418. eth_register(dev);
  419. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  420. int retval;
  421. struct mii_dev *mdiodev = mdio_alloc();
  422. if (!mdiodev)
  423. return -ENOMEM;
  424. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  425. mdiodev->read = at91emac_mii_read;
  426. mdiodev->write = at91emac_mii_write;
  427. retval = mdio_register(mdiodev);
  428. if (retval < 0)
  429. return retval;
  430. #endif
  431. return 1;
  432. }