armada100_fec.h 6.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2011
  4. * eInfochips Ltd. <www.einfochips.com>
  5. * Written-by: Ajay Bhargav <contact@8051projects.net>
  6. *
  7. * (C) Copyright 2010
  8. * Marvell Semiconductor <www.marvell.com>
  9. * Contributor: Mahavir Jain <mjain@marvell.com>
  10. */
  11. #ifndef __ARMADA100_FEC_H__
  12. #define __ARMADA100_FEC_H__
  13. #define PORT_NUM 0x0
  14. /* RX & TX descriptor command */
  15. #define BUF_OWNED_BY_DMA (1<<31)
  16. /* RX descriptor status */
  17. #define RX_EN_INT (1<<23)
  18. #define RX_FIRST_DESC (1<<17)
  19. #define RX_LAST_DESC (1<<16)
  20. #define RX_ERROR (1<<15)
  21. /* TX descriptor command */
  22. #define TX_EN_INT (1<<23)
  23. #define TX_GEN_CRC (1<<22)
  24. #define TX_ZERO_PADDING (1<<18)
  25. #define TX_FIRST_DESC (1<<17)
  26. #define TX_LAST_DESC (1<<16)
  27. #define TX_ERROR (1<<15)
  28. /* smi register */
  29. #define SMI_BUSY (1<<28) /* 0 - Write, 1 - Read */
  30. #define SMI_R_VALID (1<<27) /* 0 - Write, 1 - Read */
  31. #define SMI_OP_W (0<<26) /* Write operation */
  32. #define SMI_OP_R (1<<26) /* Read operation */
  33. #define HASH_ADD 0
  34. #define HASH_DELETE 1
  35. #define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */
  36. #define HOP_NUMBER 12
  37. #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
  38. #define PHY_WAIT_MICRO_SECONDS 10
  39. #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
  40. #define ETH_EXTRA_HEADER (6+6+2+4)
  41. /* dest+src addr+protocol id+crc */
  42. #define MAX_PKT_SIZE 1536
  43. /* Bit definitions of the SDMA Config Reg */
  44. #define SDCR_BSZ_OFF 12
  45. #define SDCR_BSZ8 (3<<SDCR_BSZ_OFF)
  46. #define SDCR_BSZ4 (2<<SDCR_BSZ_OFF)
  47. #define SDCR_BSZ2 (1<<SDCR_BSZ_OFF)
  48. #define SDCR_BSZ1 (0<<SDCR_BSZ_OFF)
  49. #define SDCR_BLMR (1<<6)
  50. #define SDCR_BLMT (1<<7)
  51. #define SDCR_RIFB (1<<9)
  52. #define SDCR_RC_OFF 2
  53. #define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF)
  54. /* SDMA_CMD */
  55. #define SDMA_CMD_AT (1<<31)
  56. #define SDMA_CMD_TXDL (1<<24)
  57. #define SDMA_CMD_TXDH (1<<23)
  58. #define SDMA_CMD_AR (1<<15)
  59. #define SDMA_CMD_ERD (1<<7)
  60. /* Bit definitions of the Port Config Reg */
  61. #define PCR_HS (1<<12)
  62. #define PCR_EN (1<<7)
  63. #define PCR_PM (1<<0)
  64. /* Bit definitions of the Port Config Extend Reg */
  65. #define PCXR_2BSM (1<<28)
  66. #define PCXR_DSCP_EN (1<<21)
  67. #define PCXR_MFL_1518 (0<<14)
  68. #define PCXR_MFL_1536 (1<<14)
  69. #define PCXR_MFL_2048 (2<<14)
  70. #define PCXR_MFL_64K (3<<14)
  71. #define PCXR_FLP (1<<11)
  72. #define PCXR_PRIO_TX_OFF 3
  73. #define PCXR_TX_HIGH_PRI (7<<PCXR_PRIO_TX_OFF)
  74. /*
  75. * * Bit definitions of the Interrupt Cause Reg
  76. * * and Interrupt MASK Reg is the same
  77. * */
  78. #define ICR_RXBUF (1<<0)
  79. #define ICR_TXBUF_H (1<<2)
  80. #define ICR_TXBUF_L (1<<3)
  81. #define ICR_TXEND_H (1<<6)
  82. #define ICR_TXEND_L (1<<7)
  83. #define ICR_RXERR (1<<8)
  84. #define ICR_TXERR_H (1<<10)
  85. #define ICR_TXERR_L (1<<11)
  86. #define ICR_TX_UDR (1<<13)
  87. #define ICR_MII_CH (1<<28)
  88. #define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\
  89. ICR_TXERR_H | ICR_TXERR_L |\
  90. ICR_TXEND_H | ICR_TXEND_L |\
  91. ICR_RXBUF | ICR_RXERR | ICR_MII_CH)
  92. #define PHY_MASK 0x0000001f
  93. #define to_darmdfec(_kd) container_of(_kd, struct armdfec_device, dev)
  94. /* Size of a Tx/Rx descriptor used in chain list data structure */
  95. #define ARMDFEC_RXQ_DESC_ALIGNED_SIZE \
  96. (((sizeof(struct rx_desc) / PKTALIGN) + 1) * PKTALIGN)
  97. #define RX_BUF_OFFSET 0x2
  98. #define RXQ 0x0 /* RX Queue 0 */
  99. #define TXQ 0x1 /* TX Queue 1 */
  100. struct addr_table_entry_t {
  101. u32 lo;
  102. u32 hi;
  103. };
  104. /* Bit fields of a Hash Table Entry */
  105. enum hash_table_entry {
  106. HTEVALID = 1,
  107. HTESKIP = 2,
  108. HTERD = 4,
  109. HTERDBIT = 2
  110. };
  111. struct tx_desc {
  112. u32 cmd_sts; /* Command/status field */
  113. u16 reserved;
  114. u16 byte_cnt; /* buffer byte count */
  115. u8 *buf_ptr; /* pointer to buffer for this descriptor */
  116. struct tx_desc *nextdesc_p; /* Pointer to next descriptor */
  117. };
  118. struct rx_desc {
  119. u32 cmd_sts; /* Descriptor command status */
  120. u16 byte_cnt; /* Descriptor buffer byte count */
  121. u16 buf_size; /* Buffer size */
  122. u8 *buf_ptr; /* Descriptor buffer pointer */
  123. struct rx_desc *nxtdesc_p; /* Next descriptor pointer */
  124. };
  125. /*
  126. * Armada100 Fast Ethernet controller Registers
  127. * Refer Datasheet Appendix A.22
  128. */
  129. struct armdfec_reg {
  130. u32 phyadr; /* PHY Address */
  131. u32 pad1[3];
  132. u32 smi; /* SMI */
  133. u32 pad2[0xFB];
  134. u32 pconf; /* Port configuration */
  135. u32 pad3;
  136. u32 pconf_ext; /* Port configuration extend */
  137. u32 pad4;
  138. u32 pcmd; /* Port Command */
  139. u32 pad5;
  140. u32 pstatus; /* Port Status */
  141. u32 pad6;
  142. u32 spar; /* Serial Parameters */
  143. u32 pad7;
  144. u32 htpr; /* Hash table pointer */
  145. u32 pad8;
  146. u32 fcsal; /* Flow control source address low */
  147. u32 pad9;
  148. u32 fcsah; /* Flow control source address high */
  149. u32 pad10;
  150. u32 sdma_conf; /* SDMA configuration */
  151. u32 pad11;
  152. u32 sdma_cmd; /* SDMA command */
  153. u32 pad12;
  154. u32 ic; /* Interrupt cause */
  155. u32 iwc; /* Interrupt write to clear */
  156. u32 im; /* Interrupt mask */
  157. u32 pad13;
  158. u32 *eth_idscpp[4]; /* Eth0 IP Differentiated Services Code
  159. Point to Priority 0 Low */
  160. u32 eth_vlan_p; /* Eth0 VLAN Priority Tag to Priority */
  161. u32 pad14[3];
  162. struct rx_desc *rxfdp[4]; /* Ethernet First Rx Descriptor
  163. Pointer */
  164. u32 pad15[4];
  165. struct rx_desc *rxcdp[4]; /* Ethernet Current Rx Descriptor
  166. Pointer */
  167. u32 pad16[0x0C];
  168. struct tx_desc *txcdp[2]; /* Ethernet Current Tx Descriptor
  169. Pointer */
  170. };
  171. struct armdfec_device {
  172. struct eth_device dev;
  173. struct armdfec_reg *regs;
  174. struct tx_desc *p_txdesc;
  175. struct rx_desc *p_rxdesc;
  176. struct rx_desc *p_rxdesc_curr;
  177. u8 *p_rxbuf;
  178. u8 *p_aligned_txbuf;
  179. u8 *htpr; /* hash pointer */
  180. };
  181. #endif /* __ARMADA100_FEC_H__ */