armada100_fec.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2011
  4. * eInfochips Ltd. <www.einfochips.com>
  5. * Written-by: Ajay Bhargav <contact@8051projects.net>
  6. *
  7. * (C) Copyright 2010
  8. * Marvell Semiconductor <www.marvell.com>
  9. * Contributor: Mahavir Jain <mjain@marvell.com>
  10. */
  11. #include <common.h>
  12. #include <log.h>
  13. #include <net.h>
  14. #include <malloc.h>
  15. #include <miiphy.h>
  16. #include <netdev.h>
  17. #include <asm/types.h>
  18. #include <asm/byteorder.h>
  19. #include <linux/delay.h>
  20. #include <linux/err.h>
  21. #include <linux/mii.h>
  22. #include <asm/io.h>
  23. #include <asm/arch/armada100.h>
  24. #include "armada100_fec.h"
  25. #define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */
  26. #ifdef DEBUG
  27. static int eth_dump_regs(struct eth_device *dev)
  28. {
  29. struct armdfec_device *darmdfec = to_darmdfec(dev);
  30. struct armdfec_reg *regs = darmdfec->regs;
  31. unsigned int i = 0;
  32. printf("\noffset: phy_adr, value: 0x%x\n", readl(&regs->phyadr));
  33. printf("offset: smi, value: 0x%x\n", readl(&regs->smi));
  34. for (i = 0x400; i <= 0x4e4; i += 4)
  35. printf("offset: 0x%x, value: 0x%x\n",
  36. i, readl(ARMD1_FEC_BASE + i));
  37. return 0;
  38. }
  39. #endif
  40. static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond)
  41. {
  42. u32 timeout = PHY_WAIT_ITERATIONS;
  43. u32 reg_val;
  44. while (--timeout) {
  45. reg_val = readl(reg);
  46. if (cond && (reg_val & flag))
  47. break;
  48. else if (!cond && !(reg_val & flag))
  49. break;
  50. udelay(PHY_WAIT_MICRO_SECONDS);
  51. }
  52. return !timeout;
  53. }
  54. static int smi_reg_read(struct mii_dev *bus, int phy_addr, int devad,
  55. int phy_reg)
  56. {
  57. u16 value = 0;
  58. struct eth_device *dev = eth_get_dev_by_name(bus->name);
  59. struct armdfec_device *darmdfec = to_darmdfec(dev);
  60. struct armdfec_reg *regs = darmdfec->regs;
  61. u32 val;
  62. if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
  63. val = readl(&regs->phyadr);
  64. value = val & 0x1f;
  65. return value;
  66. }
  67. /* check parameters */
  68. if (phy_addr > PHY_MASK) {
  69. printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n",
  70. __func__, phy_addr);
  71. return -EINVAL;
  72. }
  73. if (phy_reg > PHY_MASK) {
  74. printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n",
  75. __func__, phy_reg);
  76. return -EINVAL;
  77. }
  78. /* wait for the SMI register to become available */
  79. if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, false)) {
  80. printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
  81. return -1;
  82. }
  83. writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, &regs->smi);
  84. /* now wait for the data to be valid */
  85. if (armdfec_phy_timeout(&regs->smi, SMI_R_VALID, true)) {
  86. val = readl(&regs->smi);
  87. printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n",
  88. __func__, val);
  89. return -1;
  90. }
  91. val = readl(&regs->smi);
  92. value = val & 0xffff;
  93. return value;
  94. }
  95. static int smi_reg_write(struct mii_dev *bus, int phy_addr, int devad,
  96. int phy_reg, u16 value)
  97. {
  98. struct eth_device *dev = eth_get_dev_by_name(bus->name);
  99. struct armdfec_device *darmdfec = to_darmdfec(dev);
  100. struct armdfec_reg *regs = darmdfec->regs;
  101. if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
  102. clrsetbits_le32(&regs->phyadr, 0x1f, value & 0x1f);
  103. return 0;
  104. }
  105. /* check parameters */
  106. if (phy_addr > PHY_MASK) {
  107. printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__);
  108. return -EINVAL;
  109. }
  110. if (phy_reg > PHY_MASK) {
  111. printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__);
  112. return -EINVAL;
  113. }
  114. /* wait for the SMI register to become available */
  115. if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, false)) {
  116. printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
  117. return -1;
  118. }
  119. writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_W | (value & 0xffff),
  120. &regs->smi);
  121. return 0;
  122. }
  123. /*
  124. * Abort any transmit and receive operations and put DMA
  125. * in idle state. AT and AR bits are cleared upon entering
  126. * in IDLE state. So poll those bits to verify operation.
  127. */
  128. static void abortdma(struct eth_device *dev)
  129. {
  130. struct armdfec_device *darmdfec = to_darmdfec(dev);
  131. struct armdfec_reg *regs = darmdfec->regs;
  132. int delay;
  133. int maxretries = 40;
  134. u32 tmp;
  135. while (--maxretries) {
  136. writel(SDMA_CMD_AR | SDMA_CMD_AT, &regs->sdma_cmd);
  137. udelay(100);
  138. delay = 10;
  139. while (--delay) {
  140. tmp = readl(&regs->sdma_cmd);
  141. if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT)))
  142. break;
  143. udelay(10);
  144. }
  145. if (delay)
  146. break;
  147. }
  148. if (!maxretries)
  149. printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__);
  150. }
  151. static inline u32 nibble_swapping_32_bit(u32 x)
  152. {
  153. return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4);
  154. }
  155. static inline u32 nibble_swapping_16_bit(u32 x)
  156. {
  157. return ((x & 0x0000f0f0) >> 4) | ((x & 0x00000f0f) << 4);
  158. }
  159. static inline u32 flip_4_bits(u32 x)
  160. {
  161. return ((x & 0x01) << 3) | ((x & 0x002) << 1)
  162. | ((x & 0x04) >> 1) | ((x & 0x008) >> 3);
  163. }
  164. /*
  165. * This function will calculate the hash function of the address.
  166. * depends on the hash mode and hash size.
  167. * Inputs
  168. * mach - the 2 most significant bytes of the MAC address.
  169. * macl - the 4 least significant bytes of the MAC address.
  170. * Outputs
  171. * return the calculated entry.
  172. */
  173. static u32 hash_function(u32 mach, u32 macl)
  174. {
  175. u32 hashresult;
  176. u32 addrh;
  177. u32 addrl;
  178. u32 addr0;
  179. u32 addr1;
  180. u32 addr2;
  181. u32 addr3;
  182. u32 addrhswapped;
  183. u32 addrlswapped;
  184. addrh = nibble_swapping_16_bit(mach);
  185. addrl = nibble_swapping_32_bit(macl);
  186. addrhswapped = flip_4_bits(addrh & 0xf)
  187. + ((flip_4_bits((addrh >> 4) & 0xf)) << 4)
  188. + ((flip_4_bits((addrh >> 8) & 0xf)) << 8)
  189. + ((flip_4_bits((addrh >> 12) & 0xf)) << 12);
  190. addrlswapped = flip_4_bits(addrl & 0xf)
  191. + ((flip_4_bits((addrl >> 4) & 0xf)) << 4)
  192. + ((flip_4_bits((addrl >> 8) & 0xf)) << 8)
  193. + ((flip_4_bits((addrl >> 12) & 0xf)) << 12)
  194. + ((flip_4_bits((addrl >> 16) & 0xf)) << 16)
  195. + ((flip_4_bits((addrl >> 20) & 0xf)) << 20)
  196. + ((flip_4_bits((addrl >> 24) & 0xf)) << 24)
  197. + ((flip_4_bits((addrl >> 28) & 0xf)) << 28);
  198. addrh = addrhswapped;
  199. addrl = addrlswapped;
  200. addr0 = (addrl >> 2) & 0x03f;
  201. addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2);
  202. addr2 = (addrl >> 15) & 0x1ff;
  203. addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8);
  204. hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
  205. hashresult = hashresult & 0x07ff;
  206. return hashresult;
  207. }
  208. /*
  209. * This function will add an entry to the address table.
  210. * depends on the hash mode and hash size that was initialized.
  211. * Inputs
  212. * mach - the 2 most significant bytes of the MAC address.
  213. * macl - the 4 least significant bytes of the MAC address.
  214. * skip - if 1, skip this address.
  215. * rd - the RD field in the address table.
  216. * Outputs
  217. * address table entry is added.
  218. * 0 if success.
  219. * -ENOSPC if table full
  220. */
  221. static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach,
  222. u32 macl, u32 rd, u32 skip, int del)
  223. {
  224. struct addr_table_entry_t *entry, *start;
  225. u32 newhi;
  226. u32 newlo;
  227. u32 i;
  228. newlo = (((mach >> 4) & 0xf) << 15)
  229. | (((mach >> 0) & 0xf) << 11)
  230. | (((mach >> 12) & 0xf) << 7)
  231. | (((mach >> 8) & 0xf) << 3)
  232. | (((macl >> 20) & 0x1) << 31)
  233. | (((macl >> 16) & 0xf) << 27)
  234. | (((macl >> 28) & 0xf) << 23)
  235. | (((macl >> 24) & 0xf) << 19)
  236. | (skip << HTESKIP) | (rd << HTERDBIT)
  237. | HTEVALID;
  238. newhi = (((macl >> 4) & 0xf) << 15)
  239. | (((macl >> 0) & 0xf) << 11)
  240. | (((macl >> 12) & 0xf) << 7)
  241. | (((macl >> 8) & 0xf) << 3)
  242. | (((macl >> 21) & 0x7) << 0);
  243. /*
  244. * Pick the appropriate table, start scanning for free/reusable
  245. * entries at the index obtained by hashing the specified MAC address
  246. */
  247. start = (struct addr_table_entry_t *)(darmdfec->htpr);
  248. entry = start + hash_function(mach, macl);
  249. for (i = 0; i < HOP_NUMBER; i++) {
  250. if (!(entry->lo & HTEVALID)) {
  251. break;
  252. } else {
  253. /* if same address put in same position */
  254. if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8))
  255. && (entry->hi == newhi))
  256. break;
  257. }
  258. if (entry == start + 0x7ff)
  259. entry = start;
  260. else
  261. entry++;
  262. }
  263. if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) &&
  264. (entry->hi != newhi) && del)
  265. return 0;
  266. if (i == HOP_NUMBER) {
  267. if (!del) {
  268. printf("ARMD100 FEC: (%s) table section is full\n",
  269. __func__);
  270. return -ENOSPC;
  271. } else {
  272. return 0;
  273. }
  274. }
  275. /*
  276. * Update the selected entry
  277. */
  278. if (del) {
  279. entry->hi = 0;
  280. entry->lo = 0;
  281. } else {
  282. entry->hi = newhi;
  283. entry->lo = newlo;
  284. }
  285. return 0;
  286. }
  287. /*
  288. * Create an addressTable entry from MAC address info
  289. * found in the specifed net_device struct
  290. *
  291. * Input : pointer to ethernet interface network device structure
  292. * Output : N/A
  293. */
  294. static void update_hash_table_mac_address(struct armdfec_device *darmdfec,
  295. u8 *oaddr, u8 *addr)
  296. {
  297. u32 mach;
  298. u32 macl;
  299. /* Delete old entry */
  300. if (oaddr) {
  301. mach = (oaddr[0] << 8) | oaddr[1];
  302. macl = (oaddr[2] << 24) | (oaddr[3] << 16) |
  303. (oaddr[4] << 8) | oaddr[5];
  304. add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE);
  305. }
  306. /* Add new entry */
  307. mach = (addr[0] << 8) | addr[1];
  308. macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
  309. add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD);
  310. }
  311. /* Address Table Initialization */
  312. static void init_hashtable(struct eth_device *dev)
  313. {
  314. struct armdfec_device *darmdfec = to_darmdfec(dev);
  315. struct armdfec_reg *regs = darmdfec->regs;
  316. memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE);
  317. writel((u32)darmdfec->htpr, &regs->htpr);
  318. }
  319. /*
  320. * This detects PHY chip from address 0-31 by reading PHY status
  321. * registers. PHY chip can be connected at any of this address.
  322. */
  323. static int ethernet_phy_detect(struct eth_device *dev)
  324. {
  325. u32 val;
  326. u16 tmp, mii_status;
  327. u8 addr;
  328. for (addr = 0; addr < 32; addr++) {
  329. if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0)
  330. /* try next phy */
  331. continue;
  332. /* invalid MII status. More validation required here... */
  333. if (mii_status == 0 || mii_status == 0xffff)
  334. /* try next phy */
  335. continue;
  336. if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0)
  337. /* try next phy */
  338. continue;
  339. val = tmp << 16;
  340. if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0)
  341. /* try next phy */
  342. continue;
  343. val |= tmp;
  344. if ((val & 0xfffffff0) != 0)
  345. return addr;
  346. }
  347. return -1;
  348. }
  349. static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec)
  350. {
  351. struct rx_desc *p_rx_desc;
  352. int i;
  353. /* initialize the Rx descriptors ring */
  354. p_rx_desc = darmdfec->p_rxdesc;
  355. for (i = 0; i < RINGSZ; i++) {
  356. p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
  357. p_rx_desc->buf_size = PKTSIZE_ALIGN;
  358. p_rx_desc->byte_cnt = 0;
  359. p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN;
  360. if (i == (RINGSZ - 1)) {
  361. p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc;
  362. } else {
  363. p_rx_desc->nxtdesc_p = (struct rx_desc *)
  364. ((u32)p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE);
  365. p_rx_desc = p_rx_desc->nxtdesc_p;
  366. }
  367. }
  368. darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc;
  369. }
  370. static int armdfec_init(struct eth_device *dev, struct bd_info *bd)
  371. {
  372. struct armdfec_device *darmdfec = to_darmdfec(dev);
  373. struct armdfec_reg *regs = darmdfec->regs;
  374. int phy_adr;
  375. u32 temp;
  376. armdfec_init_rx_desc_ring(darmdfec);
  377. /* Disable interrupts */
  378. writel(0, &regs->im);
  379. writel(0, &regs->ic);
  380. /* Write to ICR to clear interrupts. */
  381. writel(0, &regs->iwc);
  382. /*
  383. * Abort any transmit and receive operations and put DMA
  384. * in idle state.
  385. */
  386. abortdma(dev);
  387. /* Initialize address hash table */
  388. init_hashtable(dev);
  389. /* SDMA configuration */
  390. writel(SDCR_BSZ8 | /* Burst size = 32 bytes */
  391. SDCR_RIFB | /* Rx interrupt on frame */
  392. SDCR_BLMT | /* Little endian transmit */
  393. SDCR_BLMR | /* Little endian receive */
  394. SDCR_RC_MAX_RETRANS, /* Max retransmit count */
  395. &regs->sdma_conf);
  396. /* Port Configuration */
  397. writel(PCR_HS, &regs->pconf); /* Hash size is 1/2kb */
  398. /* Set extended port configuration */
  399. writel(PCXR_2BSM | /* Two byte suffix aligns IP hdr */
  400. PCXR_DSCP_EN | /* Enable DSCP in IP */
  401. PCXR_MFL_1536 | /* Set MTU = 1536 */
  402. PCXR_FLP | /* do not force link pass */
  403. PCXR_TX_HIGH_PRI, /* Transmit - high priority queue */
  404. &regs->pconf_ext);
  405. update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr);
  406. /* Update TX and RX queue descriptor register */
  407. temp = (u32)&regs->txcdp[TXQ];
  408. writel((u32)darmdfec->p_txdesc, temp);
  409. temp = (u32)&regs->rxfdp[RXQ];
  410. writel((u32)darmdfec->p_rxdesc, temp);
  411. temp = (u32)&regs->rxcdp[RXQ];
  412. writel((u32)darmdfec->p_rxdesc_curr, temp);
  413. /* Enable Interrupts */
  414. writel(ALL_INTS, &regs->im);
  415. /* Enable Ethernet Port */
  416. setbits_le32(&regs->pconf, PCR_EN);
  417. /* Enable RX DMA engine */
  418. setbits_le32(&regs->sdma_cmd, SDMA_CMD_ERD);
  419. #ifdef DEBUG
  420. eth_dump_regs(dev);
  421. #endif
  422. #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
  423. #if defined(CONFIG_PHY_BASE_ADR)
  424. miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR);
  425. #else
  426. /* Search phy address from range 0-31 */
  427. phy_adr = ethernet_phy_detect(dev);
  428. if (phy_adr < 0) {
  429. printf("ARMD100 FEC: PHY not detected at address range 0-31\n");
  430. return -1;
  431. } else {
  432. debug("ARMD100 FEC: PHY detected at addr %d\n", phy_adr);
  433. miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr);
  434. }
  435. #endif
  436. #if defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
  437. /* Wait up to 5s for the link status */
  438. for (i = 0; i < 5; i++) {
  439. u16 phy_adr;
  440. miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr);
  441. /* Return if we get link up */
  442. if (miiphy_link(dev->name, phy_adr))
  443. return 0;
  444. udelay(1000000);
  445. }
  446. printf("ARMD100 FEC: No link on %s\n", dev->name);
  447. return -1;
  448. #endif
  449. #endif
  450. return 0;
  451. }
  452. static void armdfec_halt(struct eth_device *dev)
  453. {
  454. struct armdfec_device *darmdfec = to_darmdfec(dev);
  455. struct armdfec_reg *regs = darmdfec->regs;
  456. /* Stop RX DMA */
  457. clrbits_le32(&regs->sdma_cmd, SDMA_CMD_ERD);
  458. /*
  459. * Abort any transmit and receive operations and put DMA
  460. * in idle state.
  461. */
  462. abortdma(dev);
  463. /* Disable interrupts */
  464. writel(0, &regs->im);
  465. writel(0, &regs->ic);
  466. writel(0, &regs->iwc);
  467. /* Disable Port */
  468. clrbits_le32(&regs->pconf, PCR_EN);
  469. }
  470. static int armdfec_send(struct eth_device *dev, void *dataptr, int datasize)
  471. {
  472. struct armdfec_device *darmdfec = to_darmdfec(dev);
  473. struct armdfec_reg *regs = darmdfec->regs;
  474. struct tx_desc *p_txdesc = darmdfec->p_txdesc;
  475. void *p = (void *)dataptr;
  476. int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS;
  477. u32 cmd_sts, temp;
  478. /* Copy buffer if it's misaligned */
  479. if ((u32)dataptr & 0x07) {
  480. if (datasize > PKTSIZE_ALIGN) {
  481. printf("ARMD100 FEC: Non-aligned data too large (%d)\n",
  482. datasize);
  483. return -1;
  484. }
  485. memcpy(darmdfec->p_aligned_txbuf, p, datasize);
  486. p = darmdfec->p_aligned_txbuf;
  487. }
  488. p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC;
  489. p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC;
  490. p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA;
  491. p_txdesc->cmd_sts |= TX_EN_INT;
  492. p_txdesc->buf_ptr = p;
  493. p_txdesc->byte_cnt = datasize;
  494. /* Apply send command using high priority TX queue */
  495. temp = (u32)&regs->txcdp[TXQ];
  496. writel((u32)p_txdesc, temp);
  497. writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, &regs->sdma_cmd);
  498. /*
  499. * wait for packet xmit completion
  500. */
  501. cmd_sts = readl(&p_txdesc->cmd_sts);
  502. while (cmd_sts & BUF_OWNED_BY_DMA) {
  503. /* return fail if error is detected */
  504. if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) ==
  505. (TX_ERROR | TX_LAST_DESC)) {
  506. printf("ARMD100 FEC: (%s) in xmit packet\n", __func__);
  507. return -1;
  508. }
  509. cmd_sts = readl(&p_txdesc->cmd_sts);
  510. if (!(retry--)) {
  511. printf("ARMD100 FEC: (%s) xmit packet timeout!\n",
  512. __func__);
  513. return -1;
  514. }
  515. }
  516. return 0;
  517. }
  518. static int armdfec_recv(struct eth_device *dev)
  519. {
  520. struct armdfec_device *darmdfec = to_darmdfec(dev);
  521. struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr;
  522. u32 cmd_sts;
  523. u32 timeout = 0;
  524. u32 temp;
  525. /* wait untill rx packet available or timeout */
  526. do {
  527. if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) {
  528. timeout++;
  529. } else {
  530. debug("ARMD100 FEC: %s time out...\n", __func__);
  531. return -1;
  532. }
  533. } while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA);
  534. if (p_rxdesc_curr->byte_cnt != 0) {
  535. debug("ARMD100 FEC: %s: Received %d byte Packet @ 0x%x"
  536. "(cmd_sts= %08x)\n", __func__,
  537. (u32)p_rxdesc_curr->byte_cnt,
  538. (u32)p_rxdesc_curr->buf_ptr,
  539. (u32)p_rxdesc_curr->cmd_sts);
  540. }
  541. /*
  542. * In case received a packet without first/last bits on
  543. * OR the error summary bit is on,
  544. * the packets needs to be dropeed.
  545. */
  546. cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
  547. if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
  548. (RX_FIRST_DESC | RX_LAST_DESC)) {
  549. printf("ARMD100 FEC: (%s) Dropping packet spread on"
  550. " multiple descriptors\n", __func__);
  551. } else if (cmd_sts & RX_ERROR) {
  552. printf("ARMD100 FEC: (%s) Dropping packet with errors\n",
  553. __func__);
  554. } else {
  555. /* !!! call higher layer processing */
  556. debug("ARMD100 FEC: (%s) Sending Received packet to"
  557. " upper layer (net_process_received_packet)\n", __func__);
  558. /*
  559. * let the upper layer handle the packet, subtract offset
  560. * as two dummy bytes are added in received buffer see
  561. * PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit.
  562. */
  563. net_process_received_packet(
  564. p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET,
  565. (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
  566. }
  567. /*
  568. * free these descriptors and point next in the ring
  569. */
  570. p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
  571. p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
  572. p_rxdesc_curr->byte_cnt = 0;
  573. temp = (u32)&darmdfec->p_rxdesc_curr;
  574. writel((u32)p_rxdesc_curr->nxtdesc_p, temp);
  575. return 0;
  576. }
  577. int armada100_fec_register(unsigned long base_addr)
  578. {
  579. struct armdfec_device *darmdfec;
  580. struct eth_device *dev;
  581. darmdfec = malloc(sizeof(struct armdfec_device));
  582. if (!darmdfec)
  583. goto error;
  584. memset(darmdfec, 0, sizeof(struct armdfec_device));
  585. darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE);
  586. if (!darmdfec->htpr)
  587. goto error1;
  588. darmdfec->p_rxdesc = memalign(PKTALIGN,
  589. ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
  590. if (!darmdfec->p_rxdesc)
  591. goto error1;
  592. darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1);
  593. if (!darmdfec->p_rxbuf)
  594. goto error1;
  595. darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
  596. if (!darmdfec->p_aligned_txbuf)
  597. goto error1;
  598. darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1);
  599. if (!darmdfec->p_txdesc)
  600. goto error1;
  601. dev = &darmdfec->dev;
  602. /* Assign ARMADA100 Fast Ethernet Controller Base Address */
  603. darmdfec->regs = (void *)base_addr;
  604. /* must be less than sizeof(dev->name) */
  605. strcpy(dev->name, "armd-fec0");
  606. dev->init = armdfec_init;
  607. dev->halt = armdfec_halt;
  608. dev->send = armdfec_send;
  609. dev->recv = armdfec_recv;
  610. eth_register(dev);
  611. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  612. int retval;
  613. struct mii_dev *mdiodev = mdio_alloc();
  614. if (!mdiodev)
  615. return -ENOMEM;
  616. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  617. mdiodev->read = smi_reg_read;
  618. mdiodev->write = smi_reg_write;
  619. retval = mdio_register(mdiodev);
  620. if (retval < 0)
  621. return retval;
  622. #endif
  623. return 0;
  624. error1:
  625. free(darmdfec->p_aligned_txbuf);
  626. free(darmdfec->p_rxbuf);
  627. free(darmdfec->p_rxdesc);
  628. free(darmdfec->htpr);
  629. error:
  630. free(darmdfec);
  631. printf("AMD100 FEC: (%s) Failed to allocate memory\n", __func__);
  632. return -1;
  633. }