altera_tse.c 18 KB

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  1. /*
  2. * Altera 10/100/1000 triple speed ethernet mac driver
  3. *
  4. * Copyright (C) 2008 Altera Corporation.
  5. * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <dm.h>
  14. #include <errno.h>
  15. #include <fdt_support.h>
  16. #include <log.h>
  17. #include <memalign.h>
  18. #include <miiphy.h>
  19. #include <net.h>
  20. #include <asm/cache.h>
  21. #include <asm/global_data.h>
  22. #include <linux/dma-mapping.h>
  23. #include <asm/io.h>
  24. #include "altera_tse.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. static inline void alt_sgdma_construct_descriptor(
  27. struct alt_sgdma_descriptor *desc,
  28. struct alt_sgdma_descriptor *next,
  29. void *read_addr,
  30. void *write_addr,
  31. u16 length_or_eop,
  32. int generate_eop,
  33. int read_fixed,
  34. int write_fixed_or_sop)
  35. {
  36. u8 val;
  37. /*
  38. * Mark the "next" descriptor as "not" owned by hardware. This prevents
  39. * The SGDMA controller from continuing to process the chain.
  40. */
  41. next->descriptor_control = next->descriptor_control &
  42. ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
  43. memset(desc, 0, sizeof(struct alt_sgdma_descriptor));
  44. desc->source = virt_to_phys(read_addr);
  45. desc->destination = virt_to_phys(write_addr);
  46. desc->next = virt_to_phys(next);
  47. desc->bytes_to_transfer = length_or_eop;
  48. /*
  49. * Set the descriptor control block as follows:
  50. * - Set "owned by hardware" bit
  51. * - Optionally set "generate EOP" bit
  52. * - Optionally set the "read from fixed address" bit
  53. * - Optionally set the "write to fixed address bit (which serves
  54. * serves as a "generate SOP" control bit in memory-to-stream mode).
  55. * - Set the 4-bit atlantic channel, if specified
  56. *
  57. * Note this step is performed after all other descriptor information
  58. * has been filled out so that, if the controller already happens to be
  59. * pointing at this descriptor, it will not run (via the "owned by
  60. * hardware" bit) until all other descriptor has been set up.
  61. */
  62. val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
  63. if (generate_eop)
  64. val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK;
  65. if (read_fixed)
  66. val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK;
  67. if (write_fixed_or_sop)
  68. val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK;
  69. desc->descriptor_control = val;
  70. }
  71. static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs)
  72. {
  73. int status;
  74. ulong ctime;
  75. /* Wait for the descriptor (chain) to complete */
  76. ctime = get_timer(0);
  77. while (1) {
  78. status = readl(&regs->status);
  79. if (!(status & ALT_SGDMA_STATUS_BUSY_MSK))
  80. break;
  81. if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
  82. status = -ETIMEDOUT;
  83. debug("sgdma timeout\n");
  84. break;
  85. }
  86. }
  87. /* Clear Run */
  88. writel(0, &regs->control);
  89. /* Clear status */
  90. writel(0xff, &regs->status);
  91. return status;
  92. }
  93. static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs,
  94. struct alt_sgdma_descriptor *desc)
  95. {
  96. u32 val;
  97. /* Point the controller at the descriptor */
  98. writel(virt_to_phys(desc), &regs->next_descriptor_pointer);
  99. /*
  100. * Set up SGDMA controller to:
  101. * - Disable interrupt generation
  102. * - Run once a valid descriptor is written to controller
  103. * - Stop on an error with any particular descriptor
  104. */
  105. val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK;
  106. writel(val, &regs->control);
  107. return 0;
  108. }
  109. static void tse_adjust_link(struct altera_tse_priv *priv,
  110. struct phy_device *phydev)
  111. {
  112. struct alt_tse_mac *mac_dev = priv->mac_dev;
  113. u32 refvar;
  114. if (!phydev->link) {
  115. debug("%s: No link.\n", phydev->dev->name);
  116. return;
  117. }
  118. refvar = readl(&mac_dev->command_config);
  119. if (phydev->duplex)
  120. refvar |= ALTERA_TSE_CMD_HD_ENA_MSK;
  121. else
  122. refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK;
  123. switch (phydev->speed) {
  124. case 1000:
  125. refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK;
  126. refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
  127. break;
  128. case 100:
  129. refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
  130. refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
  131. break;
  132. case 10:
  133. refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
  134. refvar |= ALTERA_TSE_CMD_ENA_10_MSK;
  135. break;
  136. }
  137. writel(refvar, &mac_dev->command_config);
  138. }
  139. static int altera_tse_send_sgdma(struct udevice *dev, void *packet, int length)
  140. {
  141. struct altera_tse_priv *priv = dev_get_priv(dev);
  142. struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
  143. alt_sgdma_construct_descriptor(
  144. tx_desc,
  145. tx_desc + 1,
  146. packet, /* read addr */
  147. NULL, /* write addr */
  148. length, /* length or EOP ,will change for each tx */
  149. 1, /* gen eop */
  150. 0, /* read fixed */
  151. 1 /* write fixed or sop */
  152. );
  153. /* send the packet */
  154. alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc);
  155. alt_sgdma_wait_transfer(priv->sgdma_tx);
  156. debug("sent %d bytes\n", tx_desc->actual_bytes_transferred);
  157. return tx_desc->actual_bytes_transferred;
  158. }
  159. static int altera_tse_recv_sgdma(struct udevice *dev, int flags,
  160. uchar **packetp)
  161. {
  162. struct altera_tse_priv *priv = dev_get_priv(dev);
  163. struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
  164. int packet_length;
  165. if (rx_desc->descriptor_status &
  166. ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
  167. alt_sgdma_wait_transfer(priv->sgdma_rx);
  168. packet_length = rx_desc->actual_bytes_transferred;
  169. debug("recv %d bytes\n", packet_length);
  170. *packetp = priv->rx_buf;
  171. return packet_length;
  172. }
  173. return -EAGAIN;
  174. }
  175. static int altera_tse_free_pkt_sgdma(struct udevice *dev, uchar *packet,
  176. int length)
  177. {
  178. struct altera_tse_priv *priv = dev_get_priv(dev);
  179. struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
  180. alt_sgdma_construct_descriptor(
  181. rx_desc,
  182. rx_desc + 1,
  183. NULL, /* read addr */
  184. priv->rx_buf, /* write addr */
  185. 0, /* length or EOP */
  186. 0, /* gen eop */
  187. 0, /* read fixed */
  188. 0 /* write fixed or sop */
  189. );
  190. /* setup the sgdma */
  191. alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc);
  192. debug("recv setup\n");
  193. return 0;
  194. }
  195. static void altera_tse_stop_mac(struct altera_tse_priv *priv)
  196. {
  197. struct alt_tse_mac *mac_dev = priv->mac_dev;
  198. u32 status;
  199. ulong ctime;
  200. /* reset the mac */
  201. writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config);
  202. ctime = get_timer(0);
  203. while (1) {
  204. status = readl(&mac_dev->command_config);
  205. if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK))
  206. break;
  207. if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
  208. debug("Reset mac timeout\n");
  209. break;
  210. }
  211. }
  212. }
  213. static void altera_tse_stop_sgdma(struct udevice *dev)
  214. {
  215. struct altera_tse_priv *priv = dev_get_priv(dev);
  216. struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
  217. struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
  218. struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
  219. int ret;
  220. /* clear rx desc & wait for sgdma to complete */
  221. rx_desc->descriptor_control = 0;
  222. writel(0, &rx_sgdma->control);
  223. ret = alt_sgdma_wait_transfer(rx_sgdma);
  224. if (ret == -ETIMEDOUT)
  225. writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
  226. &rx_sgdma->control);
  227. writel(0, &tx_sgdma->control);
  228. ret = alt_sgdma_wait_transfer(tx_sgdma);
  229. if (ret == -ETIMEDOUT)
  230. writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
  231. &tx_sgdma->control);
  232. }
  233. static void msgdma_reset(struct msgdma_csr *csr)
  234. {
  235. u32 status;
  236. ulong ctime;
  237. /* Reset mSGDMA */
  238. writel(MSGDMA_CSR_STAT_MASK, &csr->status);
  239. writel(MSGDMA_CSR_CTL_RESET, &csr->control);
  240. ctime = get_timer(0);
  241. while (1) {
  242. status = readl(&csr->status);
  243. if (!(status & MSGDMA_CSR_STAT_RESETTING))
  244. break;
  245. if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
  246. debug("Reset msgdma timeout\n");
  247. break;
  248. }
  249. }
  250. /* Clear status */
  251. writel(MSGDMA_CSR_STAT_MASK, &csr->status);
  252. }
  253. static u32 msgdma_wait(struct msgdma_csr *csr)
  254. {
  255. u32 status;
  256. ulong ctime;
  257. /* Wait for the descriptor to complete */
  258. ctime = get_timer(0);
  259. while (1) {
  260. status = readl(&csr->status);
  261. if (!(status & MSGDMA_CSR_STAT_BUSY))
  262. break;
  263. if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
  264. debug("sgdma timeout\n");
  265. break;
  266. }
  267. }
  268. /* Clear status */
  269. writel(MSGDMA_CSR_STAT_MASK, &csr->status);
  270. return status;
  271. }
  272. static int altera_tse_send_msgdma(struct udevice *dev, void *packet,
  273. int length)
  274. {
  275. struct altera_tse_priv *priv = dev_get_priv(dev);
  276. struct msgdma_extended_desc *desc = priv->tx_desc;
  277. u32 tx_buf = virt_to_phys(packet);
  278. u32 status;
  279. writel(tx_buf, &desc->read_addr_lo);
  280. writel(0, &desc->read_addr_hi);
  281. writel(0, &desc->write_addr_lo);
  282. writel(0, &desc->write_addr_hi);
  283. writel(length, &desc->len);
  284. writel(0, &desc->burst_seq_num);
  285. writel(MSGDMA_DESC_TX_STRIDE, &desc->stride);
  286. writel(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control);
  287. status = msgdma_wait(priv->sgdma_tx);
  288. debug("sent %d bytes, status %08x\n", length, status);
  289. return 0;
  290. }
  291. static int altera_tse_recv_msgdma(struct udevice *dev, int flags,
  292. uchar **packetp)
  293. {
  294. struct altera_tse_priv *priv = dev_get_priv(dev);
  295. struct msgdma_csr *csr = priv->sgdma_rx;
  296. struct msgdma_response *resp = priv->rx_resp;
  297. u32 level, length, status;
  298. level = readl(&csr->resp_fill_level);
  299. if (level & 0xffff) {
  300. length = readl(&resp->bytes_transferred);
  301. status = readl(&resp->status);
  302. debug("recv %d bytes, status %08x\n", length, status);
  303. *packetp = priv->rx_buf;
  304. return length;
  305. }
  306. return -EAGAIN;
  307. }
  308. static int altera_tse_free_pkt_msgdma(struct udevice *dev, uchar *packet,
  309. int length)
  310. {
  311. struct altera_tse_priv *priv = dev_get_priv(dev);
  312. struct msgdma_extended_desc *desc = priv->rx_desc;
  313. u32 rx_buf = virt_to_phys(priv->rx_buf);
  314. writel(0, &desc->read_addr_lo);
  315. writel(0, &desc->read_addr_hi);
  316. writel(rx_buf, &desc->write_addr_lo);
  317. writel(0, &desc->write_addr_hi);
  318. writel(PKTSIZE_ALIGN, &desc->len);
  319. writel(0, &desc->burst_seq_num);
  320. writel(MSGDMA_DESC_RX_STRIDE, &desc->stride);
  321. writel(MSGDMA_DESC_CTL_RX_SINGLE, &desc->control);
  322. debug("recv setup\n");
  323. return 0;
  324. }
  325. static void altera_tse_stop_msgdma(struct udevice *dev)
  326. {
  327. struct altera_tse_priv *priv = dev_get_priv(dev);
  328. msgdma_reset(priv->sgdma_rx);
  329. msgdma_reset(priv->sgdma_tx);
  330. }
  331. static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  332. {
  333. struct altera_tse_priv *priv = bus->priv;
  334. struct alt_tse_mac *mac_dev = priv->mac_dev;
  335. u32 value;
  336. /* set mdio address */
  337. writel(addr, &mac_dev->mdio_phy1_addr);
  338. /* get the data */
  339. value = readl(&mac_dev->mdio_phy1[reg]);
  340. return value & 0xffff;
  341. }
  342. static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  343. u16 val)
  344. {
  345. struct altera_tse_priv *priv = bus->priv;
  346. struct alt_tse_mac *mac_dev = priv->mac_dev;
  347. /* set mdio address */
  348. writel(addr, &mac_dev->mdio_phy1_addr);
  349. /* set the data */
  350. writel(val, &mac_dev->mdio_phy1[reg]);
  351. return 0;
  352. }
  353. static int tse_mdio_init(const char *name, struct altera_tse_priv *priv)
  354. {
  355. struct mii_dev *bus = mdio_alloc();
  356. if (!bus) {
  357. printf("Failed to allocate MDIO bus\n");
  358. return -ENOMEM;
  359. }
  360. bus->read = tse_mdio_read;
  361. bus->write = tse_mdio_write;
  362. snprintf(bus->name, sizeof(bus->name), "%s", name);
  363. bus->priv = (void *)priv;
  364. return mdio_register(bus);
  365. }
  366. static int tse_phy_init(struct altera_tse_priv *priv, void *dev)
  367. {
  368. struct phy_device *phydev;
  369. unsigned int mask = 0xffffffff;
  370. if (priv->phyaddr)
  371. mask = 1 << priv->phyaddr;
  372. phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
  373. if (!phydev)
  374. return -ENODEV;
  375. phy_connect_dev(phydev, dev);
  376. phydev->supported &= PHY_GBIT_FEATURES;
  377. phydev->advertising = phydev->supported;
  378. priv->phydev = phydev;
  379. phy_config(phydev);
  380. return 0;
  381. }
  382. static int altera_tse_write_hwaddr(struct udevice *dev)
  383. {
  384. struct altera_tse_priv *priv = dev_get_priv(dev);
  385. struct alt_tse_mac *mac_dev = priv->mac_dev;
  386. struct eth_pdata *pdata = dev_get_plat(dev);
  387. u8 *hwaddr = pdata->enetaddr;
  388. u32 mac_lo, mac_hi;
  389. mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) |
  390. (hwaddr[1] << 8) | hwaddr[0];
  391. mac_hi = (hwaddr[5] << 8) | hwaddr[4];
  392. debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo);
  393. writel(mac_lo, &mac_dev->mac_addr_0);
  394. writel(mac_hi, &mac_dev->mac_addr_1);
  395. writel(mac_lo, &mac_dev->supp_mac_addr_0_0);
  396. writel(mac_hi, &mac_dev->supp_mac_addr_0_1);
  397. writel(mac_lo, &mac_dev->supp_mac_addr_1_0);
  398. writel(mac_hi, &mac_dev->supp_mac_addr_1_1);
  399. writel(mac_lo, &mac_dev->supp_mac_addr_2_0);
  400. writel(mac_hi, &mac_dev->supp_mac_addr_2_1);
  401. writel(mac_lo, &mac_dev->supp_mac_addr_3_0);
  402. writel(mac_hi, &mac_dev->supp_mac_addr_3_1);
  403. return 0;
  404. }
  405. static int altera_tse_send(struct udevice *dev, void *packet, int length)
  406. {
  407. struct altera_tse_priv *priv = dev_get_priv(dev);
  408. unsigned long tx_buf = (unsigned long)packet;
  409. flush_dcache_range(tx_buf, tx_buf + length);
  410. return priv->ops->send(dev, packet, length);
  411. }
  412. static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp)
  413. {
  414. struct altera_tse_priv *priv = dev_get_priv(dev);
  415. return priv->ops->recv(dev, flags, packetp);
  416. }
  417. static int altera_tse_free_pkt(struct udevice *dev, uchar *packet,
  418. int length)
  419. {
  420. struct altera_tse_priv *priv = dev_get_priv(dev);
  421. unsigned long rx_buf = (unsigned long)priv->rx_buf;
  422. invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN);
  423. return priv->ops->free_pkt(dev, packet, length);
  424. }
  425. static void altera_tse_stop(struct udevice *dev)
  426. {
  427. struct altera_tse_priv *priv = dev_get_priv(dev);
  428. priv->ops->stop(dev);
  429. altera_tse_stop_mac(priv);
  430. }
  431. static int altera_tse_start(struct udevice *dev)
  432. {
  433. struct altera_tse_priv *priv = dev_get_priv(dev);
  434. struct alt_tse_mac *mac_dev = priv->mac_dev;
  435. u32 val;
  436. int ret;
  437. /* need to create sgdma */
  438. debug("Configuring rx desc\n");
  439. altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN);
  440. /* start TSE */
  441. debug("Configuring TSE Mac\n");
  442. /* Initialize MAC registers */
  443. writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length);
  444. writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold);
  445. writel(0, &mac_dev->rx_sel_full_threshold);
  446. writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold);
  447. writel(0, &mac_dev->tx_sel_full_threshold);
  448. writel(8, &mac_dev->rx_almost_empty_threshold);
  449. writel(8, &mac_dev->rx_almost_full_threshold);
  450. writel(8, &mac_dev->tx_almost_empty_threshold);
  451. writel(3, &mac_dev->tx_almost_full_threshold);
  452. /* NO Shift */
  453. writel(0, &mac_dev->rx_cmd_stat);
  454. writel(0, &mac_dev->tx_cmd_stat);
  455. /* enable MAC */
  456. val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK;
  457. writel(val, &mac_dev->command_config);
  458. /* Start up the PHY */
  459. ret = phy_startup(priv->phydev);
  460. if (ret) {
  461. debug("Could not initialize PHY %s\n",
  462. priv->phydev->dev->name);
  463. return ret;
  464. }
  465. tse_adjust_link(priv, priv->phydev);
  466. if (!priv->phydev->link)
  467. return -EIO;
  468. return 0;
  469. }
  470. static const struct tse_ops tse_sgdma_ops = {
  471. .send = altera_tse_send_sgdma,
  472. .recv = altera_tse_recv_sgdma,
  473. .free_pkt = altera_tse_free_pkt_sgdma,
  474. .stop = altera_tse_stop_sgdma,
  475. };
  476. static const struct tse_ops tse_msgdma_ops = {
  477. .send = altera_tse_send_msgdma,
  478. .recv = altera_tse_recv_msgdma,
  479. .free_pkt = altera_tse_free_pkt_msgdma,
  480. .stop = altera_tse_stop_msgdma,
  481. };
  482. static int altera_tse_probe(struct udevice *dev)
  483. {
  484. struct eth_pdata *pdata = dev_get_plat(dev);
  485. struct altera_tse_priv *priv = dev_get_priv(dev);
  486. void *blob = (void *)gd->fdt_blob;
  487. int node = dev_of_offset(dev);
  488. const char *list, *end;
  489. const fdt32_t *cell;
  490. void *base, *desc_mem = NULL;
  491. unsigned long addr, size;
  492. int parent, addrc, sizec;
  493. int len, idx;
  494. int ret;
  495. priv->dma_type = dev_get_driver_data(dev);
  496. if (priv->dma_type == ALT_SGDMA)
  497. priv->ops = &tse_sgdma_ops;
  498. else
  499. priv->ops = &tse_msgdma_ops;
  500. /*
  501. * decode regs. there are multiple reg tuples, and they need to
  502. * match with reg-names.
  503. */
  504. parent = fdt_parent_offset(blob, node);
  505. fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
  506. list = fdt_getprop(blob, node, "reg-names", &len);
  507. if (!list)
  508. return -ENOENT;
  509. end = list + len;
  510. cell = fdt_getprop(blob, node, "reg", &len);
  511. if (!cell)
  512. return -ENOENT;
  513. idx = 0;
  514. while (list < end) {
  515. addr = fdt_translate_address((void *)blob,
  516. node, cell + idx);
  517. size = fdt_addr_to_cpu(cell[idx + addrc]);
  518. base = map_physmem(addr, size, MAP_NOCACHE);
  519. len = strlen(list);
  520. if (strcmp(list, "control_port") == 0)
  521. priv->mac_dev = base;
  522. else if (strcmp(list, "rx_csr") == 0)
  523. priv->sgdma_rx = base;
  524. else if (strcmp(list, "rx_desc") == 0)
  525. priv->rx_desc = base;
  526. else if (strcmp(list, "rx_resp") == 0)
  527. priv->rx_resp = base;
  528. else if (strcmp(list, "tx_csr") == 0)
  529. priv->sgdma_tx = base;
  530. else if (strcmp(list, "tx_desc") == 0)
  531. priv->tx_desc = base;
  532. else if (strcmp(list, "s1") == 0)
  533. desc_mem = base;
  534. idx += addrc + sizec;
  535. list += (len + 1);
  536. }
  537. /* decode fifo depth */
  538. priv->rx_fifo_depth = fdtdec_get_int(blob, node,
  539. "rx-fifo-depth", 0);
  540. priv->tx_fifo_depth = fdtdec_get_int(blob, node,
  541. "tx-fifo-depth", 0);
  542. /* decode phy */
  543. addr = fdtdec_get_int(blob, node,
  544. "phy-handle", 0);
  545. addr = fdt_node_offset_by_phandle(blob, addr);
  546. priv->phyaddr = fdtdec_get_int(blob, addr,
  547. "reg", 0);
  548. /* init desc */
  549. if (priv->dma_type == ALT_SGDMA) {
  550. len = sizeof(struct alt_sgdma_descriptor) * 4;
  551. if (!desc_mem) {
  552. desc_mem = dma_alloc_coherent(len, &addr);
  553. if (!desc_mem)
  554. return -ENOMEM;
  555. }
  556. memset(desc_mem, 0, len);
  557. priv->tx_desc = desc_mem;
  558. priv->rx_desc = priv->tx_desc +
  559. 2 * sizeof(struct alt_sgdma_descriptor);
  560. }
  561. /* allocate recv packet buffer */
  562. priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN);
  563. if (!priv->rx_buf)
  564. return -ENOMEM;
  565. /* stop controller */
  566. debug("Reset TSE & SGDMAs\n");
  567. altera_tse_stop(dev);
  568. /* start the phy */
  569. priv->interface = pdata->phy_interface;
  570. tse_mdio_init(dev->name, priv);
  571. priv->bus = miiphy_get_dev_by_name(dev->name);
  572. ret = tse_phy_init(priv, dev);
  573. return ret;
  574. }
  575. static int altera_tse_of_to_plat(struct udevice *dev)
  576. {
  577. struct eth_pdata *pdata = dev_get_plat(dev);
  578. const char *phy_mode;
  579. pdata->phy_interface = -1;
  580. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  581. NULL);
  582. if (phy_mode)
  583. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  584. if (pdata->phy_interface == -1) {
  585. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  586. return -EINVAL;
  587. }
  588. return 0;
  589. }
  590. static const struct eth_ops altera_tse_ops = {
  591. .start = altera_tse_start,
  592. .send = altera_tse_send,
  593. .recv = altera_tse_recv,
  594. .free_pkt = altera_tse_free_pkt,
  595. .stop = altera_tse_stop,
  596. .write_hwaddr = altera_tse_write_hwaddr,
  597. };
  598. static const struct udevice_id altera_tse_ids[] = {
  599. { .compatible = "altr,tse-msgdma-1.0", .data = ALT_MSGDMA },
  600. { .compatible = "altr,tse-1.0", .data = ALT_SGDMA },
  601. {}
  602. };
  603. U_BOOT_DRIVER(altera_tse) = {
  604. .name = "altera_tse",
  605. .id = UCLASS_ETH,
  606. .of_match = altera_tse_ids,
  607. .ops = &altera_tse_ops,
  608. .of_to_plat = altera_tse_of_to_plat,
  609. .plat_auto = sizeof(struct eth_pdata),
  610. .priv_auto = sizeof(struct altera_tse_priv),
  611. .probe = altera_tse_probe,
  612. };