ag7xxx.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Atheros AR71xx / AR9xxx GMAC driver
  4. *
  5. * Copyright (C) 2016 Marek Vasut <marex@denx.de>
  6. * Copyright (C) 2019 Rosy Song <rosysong@rosinson.com>
  7. */
  8. #include <common.h>
  9. #include <clock_legacy.h>
  10. #include <cpu_func.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <log.h>
  14. #include <miiphy.h>
  15. #include <malloc.h>
  16. #include <net.h>
  17. #include <asm/cache.h>
  18. #include <asm/global_data.h>
  19. #include <linux/bitops.h>
  20. #include <linux/compiler.h>
  21. #include <linux/delay.h>
  22. #include <linux/err.h>
  23. #include <linux/mii.h>
  24. #include <wait_bit.h>
  25. #include <asm/io.h>
  26. #include <mach/ath79.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. enum ag7xxx_model {
  29. AG7XXX_MODEL_AG933X,
  30. AG7XXX_MODEL_AG934X,
  31. AG7XXX_MODEL_AG953X,
  32. AG7XXX_MODEL_AG956X
  33. };
  34. /* MAC Configuration 1 */
  35. #define AG7XXX_ETH_CFG1 0x00
  36. #define AG7XXX_ETH_CFG1_SOFT_RST BIT(31)
  37. #define AG7XXX_ETH_CFG1_RX_RST BIT(19)
  38. #define AG7XXX_ETH_CFG1_TX_RST BIT(18)
  39. #define AG7XXX_ETH_CFG1_LOOPBACK BIT(8)
  40. #define AG7XXX_ETH_CFG1_RX_EN BIT(2)
  41. #define AG7XXX_ETH_CFG1_TX_EN BIT(0)
  42. /* MAC Configuration 2 */
  43. #define AG7XXX_ETH_CFG2 0x04
  44. #define AG7XXX_ETH_CFG2_IF_1000 BIT(9)
  45. #define AG7XXX_ETH_CFG2_IF_10_100 BIT(8)
  46. #define AG7XXX_ETH_CFG2_IF_SPEED_MASK (3 << 8)
  47. #define AG7XXX_ETH_CFG2_HUGE_FRAME_EN BIT(5)
  48. #define AG7XXX_ETH_CFG2_LEN_CHECK BIT(4)
  49. #define AG7XXX_ETH_CFG2_PAD_CRC_EN BIT(2)
  50. #define AG7XXX_ETH_CFG2_FDX BIT(0)
  51. /* MII Configuration */
  52. #define AG7XXX_ETH_MII_MGMT_CFG 0x20
  53. #define AG7XXX_ETH_MII_MGMT_CFG_RESET BIT(31)
  54. /* MII Command */
  55. #define AG7XXX_ETH_MII_MGMT_CMD 0x24
  56. #define AG7XXX_ETH_MII_MGMT_CMD_READ 0x1
  57. /* MII Address */
  58. #define AG7XXX_ETH_MII_MGMT_ADDRESS 0x28
  59. #define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT 8
  60. /* MII Control */
  61. #define AG7XXX_ETH_MII_MGMT_CTRL 0x2c
  62. /* MII Status */
  63. #define AG7XXX_ETH_MII_MGMT_STATUS 0x30
  64. /* MII Indicators */
  65. #define AG7XXX_ETH_MII_MGMT_IND 0x34
  66. #define AG7XXX_ETH_MII_MGMT_IND_INVALID BIT(2)
  67. #define AG7XXX_ETH_MII_MGMT_IND_BUSY BIT(0)
  68. /* STA Address 1 & 2 */
  69. #define AG7XXX_ETH_ADDR1 0x40
  70. #define AG7XXX_ETH_ADDR2 0x44
  71. /* ETH Configuration 0 - 5 */
  72. #define AG7XXX_ETH_FIFO_CFG_0 0x48
  73. #define AG7XXX_ETH_FIFO_CFG_1 0x4c
  74. #define AG7XXX_ETH_FIFO_CFG_2 0x50
  75. #define AG7XXX_ETH_FIFO_CFG_3 0x54
  76. #define AG7XXX_ETH_FIFO_CFG_4 0x58
  77. #define AG7XXX_ETH_FIFO_CFG_5 0x5c
  78. /* DMA Transfer Control for Queue 0 */
  79. #define AG7XXX_ETH_DMA_TX_CTRL 0x180
  80. #define AG7XXX_ETH_DMA_TX_CTRL_TXE BIT(0)
  81. /* Descriptor Address for Queue 0 Tx */
  82. #define AG7XXX_ETH_DMA_TX_DESC 0x184
  83. /* DMA Tx Status */
  84. #define AG7XXX_ETH_DMA_TX_STATUS 0x188
  85. /* Rx Control */
  86. #define AG7XXX_ETH_DMA_RX_CTRL 0x18c
  87. #define AG7XXX_ETH_DMA_RX_CTRL_RXE BIT(0)
  88. /* Pointer to Rx Descriptor */
  89. #define AG7XXX_ETH_DMA_RX_DESC 0x190
  90. /* Rx Status */
  91. #define AG7XXX_ETH_DMA_RX_STATUS 0x194
  92. /* Custom register at 0x1805002C */
  93. #define AG7XXX_ETH_XMII 0x2C
  94. #define AG7XXX_ETH_XMII_TX_INVERT BIT(31)
  95. #define AG7XXX_ETH_XMII_RX_DELAY_LSB 28
  96. #define AG7XXX_ETH_XMII_RX_DELAY_MASK 0x30000000
  97. #define AG7XXX_ETH_XMII_RX_DELAY_SET(x) \
  98. (((x) << AG7XXX_ETH_XMII_RX_DELAY_LSB) & AG7XXX_ETH_XMII_RX_DELAY_MASK)
  99. #define AG7XXX_ETH_XMII_TX_DELAY_LSB 26
  100. #define AG7XXX_ETH_XMII_TX_DELAY_MASK 0x0c000000
  101. #define AG7XXX_ETH_XMII_TX_DELAY_SET(x) \
  102. (((x) << AG7XXX_ETH_XMII_TX_DELAY_LSB) & AG7XXX_ETH_XMII_TX_DELAY_MASK)
  103. #define AG7XXX_ETH_XMII_GIGE BIT(25)
  104. /* Custom register at 0x18070000 */
  105. #define AG7XXX_GMAC_ETH_CFG 0x00
  106. #define AG7XXX_ETH_CFG_RXDV_DELAY_LSB 16
  107. #define AG7XXX_ETH_CFG_RXDV_DELAY_MASK 0x00030000
  108. #define AG7XXX_ETH_CFG_RXDV_DELAY_SET(x) \
  109. (((x) << AG7XXX_ETH_CFG_RXDV_DELAY_LSB) & AG7XXX_ETH_CFG_RXDV_DELAY_MASK)
  110. #define AG7XXX_ETH_CFG_RXD_DELAY_LSB 14
  111. #define AG7XXX_ETH_CFG_RXD_DELAY_MASK 0x0000c000
  112. #define AG7XXX_ETH_CFG_RXD_DELAY_SET(x) \
  113. (((x) << AG7XXX_ETH_CFG_RXD_DELAY_LSB) & AG7XXX_ETH_CFG_RXD_DELAY_MASK)
  114. #define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
  115. #define AG7XXX_ETH_CFG_SW_PHY_SWAP BIT(7)
  116. #define AG7XXX_ETH_CFG_SW_ONLY_MODE BIT(6)
  117. #define AG7XXX_ETH_CFG_GE0_ERR_EN BIT(5)
  118. #define AG7XXX_ETH_CFG_MII_GE0_SLAVE BIT(4)
  119. #define AG7XXX_ETH_CFG_MII_GE0_MASTER BIT(3)
  120. #define AG7XXX_ETH_CFG_GMII_GE0 BIT(2)
  121. #define AG7XXX_ETH_CFG_MII_GE0 BIT(1)
  122. #define AG7XXX_ETH_CFG_RGMII_GE0 BIT(0)
  123. #define CONFIG_TX_DESCR_NUM 8
  124. #define CONFIG_RX_DESCR_NUM 8
  125. #define CONFIG_ETH_BUFSIZE 2048
  126. #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
  127. #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
  128. /* DMA descriptor. */
  129. struct ag7xxx_dma_desc {
  130. u32 data_addr;
  131. #define AG7XXX_DMADESC_IS_EMPTY BIT(31)
  132. #define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET 16
  133. #define AG7XXX_DMADESC_PKT_SIZE_OFFSET 0
  134. #define AG7XXX_DMADESC_PKT_SIZE_MASK 0xfff
  135. u32 config;
  136. u32 next_desc;
  137. u32 _pad[5];
  138. };
  139. struct ar7xxx_eth_priv {
  140. struct ag7xxx_dma_desc tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
  141. struct ag7xxx_dma_desc rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
  142. char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  143. char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  144. void __iomem *regs;
  145. void __iomem *phyregs;
  146. struct eth_device *dev;
  147. struct phy_device *phydev;
  148. struct mii_dev *bus;
  149. u32 interface;
  150. u32 tx_currdescnum;
  151. u32 rx_currdescnum;
  152. enum ag7xxx_model model;
  153. };
  154. /*
  155. * Switch and MDIO access
  156. */
  157. static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val)
  158. {
  159. struct ar7xxx_eth_priv *priv = bus->priv;
  160. void __iomem *regs = priv->phyregs;
  161. int ret;
  162. writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
  163. writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
  164. regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
  165. writel(AG7XXX_ETH_MII_MGMT_CMD_READ,
  166. regs + AG7XXX_ETH_MII_MGMT_CMD);
  167. ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
  168. AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
  169. if (ret)
  170. return ret;
  171. *val = readl(regs + AG7XXX_ETH_MII_MGMT_STATUS) & 0xffff;
  172. writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
  173. return 0;
  174. }
  175. static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val)
  176. {
  177. struct ar7xxx_eth_priv *priv = bus->priv;
  178. void __iomem *regs = priv->phyregs;
  179. int ret;
  180. writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
  181. regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
  182. writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL);
  183. ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
  184. AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
  185. return ret;
  186. }
  187. static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val)
  188. {
  189. struct ar7xxx_eth_priv *priv = bus->priv;
  190. u32 phy_addr;
  191. u32 reg_addr;
  192. u32 phy_temp;
  193. u32 reg_temp;
  194. u32 reg_temp_w = (reg & 0xfffffffc) >> 1;
  195. u16 rv = 0;
  196. int ret;
  197. if (priv->model == AG7XXX_MODEL_AG933X ||
  198. priv->model == AG7XXX_MODEL_AG953X) {
  199. phy_addr = 0x1f;
  200. reg_addr = 0x10;
  201. } else if (priv->model == AG7XXX_MODEL_AG934X ||
  202. priv->model == AG7XXX_MODEL_AG956X) {
  203. phy_addr = 0x18;
  204. reg_addr = 0x00;
  205. } else
  206. return -EINVAL;
  207. if (priv->model == AG7XXX_MODEL_AG956X)
  208. ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) & 0x1ff);
  209. else
  210. ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
  211. if (ret)
  212. return ret;
  213. phy_temp = ((reg >> 6) & 0x7) | 0x10;
  214. if (priv->model == AG7XXX_MODEL_AG956X)
  215. reg_temp = reg_temp_w & 0x1f;
  216. else
  217. reg_temp = (reg >> 1) & 0x1e;
  218. *val = 0;
  219. ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv);
  220. if (ret < 0)
  221. return ret;
  222. *val |= rv;
  223. if (priv->model == AG7XXX_MODEL_AG956X) {
  224. phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
  225. reg_temp = (reg_temp_w + 1) & 0x1f;
  226. ret = ag7xxx_switch_read(bus, phy_temp, reg_temp, &rv);
  227. } else {
  228. ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv);
  229. }
  230. if (ret < 0)
  231. return ret;
  232. *val |= (rv << 16);
  233. return 0;
  234. }
  235. static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val)
  236. {
  237. struct ar7xxx_eth_priv *priv = bus->priv;
  238. u32 phy_addr;
  239. u32 reg_addr;
  240. u32 phy_temp;
  241. u32 reg_temp;
  242. u32 reg_temp_w = (reg & 0xfffffffc) >> 1;
  243. int ret;
  244. if (priv->model == AG7XXX_MODEL_AG933X ||
  245. priv->model == AG7XXX_MODEL_AG953X) {
  246. phy_addr = 0x1f;
  247. reg_addr = 0x10;
  248. } else if (priv->model == AG7XXX_MODEL_AG934X ||
  249. priv->model == AG7XXX_MODEL_AG956X) {
  250. phy_addr = 0x18;
  251. reg_addr = 0x00;
  252. } else
  253. return -EINVAL;
  254. if (priv->model == AG7XXX_MODEL_AG956X)
  255. ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) & 0x1ff);
  256. else
  257. ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
  258. if (ret)
  259. return ret;
  260. if (priv->model == AG7XXX_MODEL_AG956X) {
  261. reg_temp = (reg_temp_w + 1) & 0x1f;
  262. phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
  263. } else {
  264. phy_temp = ((reg >> 6) & 0x7) | 0x10;
  265. reg_temp = (reg >> 1) & 0x1e;
  266. }
  267. /*
  268. * The switch on AR933x has some special register behavior, which
  269. * expects particular write order of their nibbles:
  270. * 0x40 ..... MSB first, LSB second
  271. * 0x50 ..... MSB first, LSB second
  272. * 0x98 ..... LSB first, MSB second
  273. * others ... don't care
  274. */
  275. if ((priv->model == AG7XXX_MODEL_AG933X) && (reg == 0x98)) {
  276. ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
  277. if (ret < 0)
  278. return ret;
  279. ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
  280. if (ret < 0)
  281. return ret;
  282. } else {
  283. if (priv->model == AG7XXX_MODEL_AG956X)
  284. ret = ag7xxx_switch_write(bus, phy_temp, reg_temp, val >> 16);
  285. else
  286. ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
  287. if (ret < 0)
  288. return ret;
  289. if (priv->model == AG7XXX_MODEL_AG956X) {
  290. phy_temp = ((reg_temp_w >> 5) & 0x7) | 0x10;
  291. reg_temp = reg_temp_w & 0x1f;
  292. }
  293. ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
  294. if (ret < 0)
  295. return ret;
  296. }
  297. return 0;
  298. }
  299. static int ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
  300. {
  301. u32 data;
  302. unsigned long start;
  303. int ret;
  304. /* No idea if this is long enough or too long */
  305. int timeout_ms = 1000;
  306. /* Dummy read followed by PHY read/write command. */
  307. ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
  308. if (ret < 0)
  309. return ret;
  310. data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31);
  311. ret = ag7xxx_switch_reg_write(bus, 0x98, data);
  312. if (ret < 0)
  313. return ret;
  314. start = get_timer(0);
  315. /* Wait for operation to finish */
  316. do {
  317. ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
  318. if (ret < 0)
  319. return ret;
  320. if (get_timer(start) > timeout_ms)
  321. return -ETIMEDOUT;
  322. } while (data & BIT(31));
  323. return data & 0xffff;
  324. }
  325. static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  326. {
  327. return ag7xxx_mdio_rw(bus, addr, reg, BIT(27));
  328. }
  329. static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  330. u16 val)
  331. {
  332. int ret;
  333. ret = ag7xxx_mdio_rw(bus, addr, reg, val);
  334. if (ret < 0)
  335. return ret;
  336. return 0;
  337. }
  338. /*
  339. * DMA ring handlers
  340. */
  341. static void ag7xxx_dma_clean_tx(struct udevice *dev)
  342. {
  343. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  344. struct ag7xxx_dma_desc *curr, *next;
  345. u32 start, end;
  346. int i;
  347. for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
  348. curr = &priv->tx_mac_descrtable[i];
  349. next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM];
  350. curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]);
  351. curr->config = AG7XXX_DMADESC_IS_EMPTY;
  352. curr->next_desc = virt_to_phys(next);
  353. }
  354. priv->tx_currdescnum = 0;
  355. /* Cache: Flush descriptors, don't care about buffers. */
  356. start = (u32)(&priv->tx_mac_descrtable[0]);
  357. end = start + sizeof(priv->tx_mac_descrtable);
  358. flush_dcache_range(start, end);
  359. }
  360. static void ag7xxx_dma_clean_rx(struct udevice *dev)
  361. {
  362. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  363. struct ag7xxx_dma_desc *curr, *next;
  364. u32 start, end;
  365. int i;
  366. for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
  367. curr = &priv->rx_mac_descrtable[i];
  368. next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM];
  369. curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]);
  370. curr->config = AG7XXX_DMADESC_IS_EMPTY;
  371. curr->next_desc = virt_to_phys(next);
  372. }
  373. priv->rx_currdescnum = 0;
  374. /* Cache: Flush+Invalidate descriptors, Invalidate buffers. */
  375. start = (u32)(&priv->rx_mac_descrtable[0]);
  376. end = start + sizeof(priv->rx_mac_descrtable);
  377. flush_dcache_range(start, end);
  378. invalidate_dcache_range(start, end);
  379. start = (u32)&priv->rxbuffs;
  380. end = start + sizeof(priv->rxbuffs);
  381. invalidate_dcache_range(start, end);
  382. }
  383. /*
  384. * Ethernet I/O
  385. */
  386. static int ag7xxx_eth_send(struct udevice *dev, void *packet, int length)
  387. {
  388. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  389. struct ag7xxx_dma_desc *curr;
  390. u32 start, end;
  391. curr = &priv->tx_mac_descrtable[priv->tx_currdescnum];
  392. /* Cache: Invalidate descriptor. */
  393. start = (u32)curr;
  394. end = start + sizeof(*curr);
  395. invalidate_dcache_range(start, end);
  396. if (!(curr->config & AG7XXX_DMADESC_IS_EMPTY)) {
  397. printf("ag7xxx: Out of TX DMA descriptors!\n");
  398. return -EPERM;
  399. }
  400. /* Copy the packet into the data buffer. */
  401. memcpy(phys_to_virt(curr->data_addr), packet, length);
  402. curr->config = length & AG7XXX_DMADESC_PKT_SIZE_MASK;
  403. /* Cache: Flush descriptor, Flush buffer. */
  404. start = (u32)curr;
  405. end = start + sizeof(*curr);
  406. flush_dcache_range(start, end);
  407. start = (u32)phys_to_virt(curr->data_addr);
  408. end = start + length;
  409. flush_dcache_range(start, end);
  410. /* Load the DMA descriptor and start TX DMA. */
  411. writel(AG7XXX_ETH_DMA_TX_CTRL_TXE,
  412. priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
  413. /* Switch to next TX descriptor. */
  414. priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CONFIG_TX_DESCR_NUM;
  415. return 0;
  416. }
  417. static int ag7xxx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  418. {
  419. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  420. struct ag7xxx_dma_desc *curr;
  421. u32 start, end, length;
  422. curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
  423. /* Cache: Invalidate descriptor. */
  424. start = (u32)curr;
  425. end = start + sizeof(*curr);
  426. invalidate_dcache_range(start, end);
  427. /* No packets received. */
  428. if (curr->config & AG7XXX_DMADESC_IS_EMPTY)
  429. return -EAGAIN;
  430. length = curr->config & AG7XXX_DMADESC_PKT_SIZE_MASK;
  431. /* Cache: Invalidate buffer. */
  432. start = (u32)phys_to_virt(curr->data_addr);
  433. end = start + length;
  434. invalidate_dcache_range(start, end);
  435. /* Receive one packet and return length. */
  436. *packetp = phys_to_virt(curr->data_addr);
  437. return length;
  438. }
  439. static int ag7xxx_eth_free_pkt(struct udevice *dev, uchar *packet,
  440. int length)
  441. {
  442. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  443. struct ag7xxx_dma_desc *curr;
  444. u32 start, end;
  445. curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
  446. curr->config = AG7XXX_DMADESC_IS_EMPTY;
  447. /* Cache: Flush descriptor. */
  448. start = (u32)curr;
  449. end = start + sizeof(*curr);
  450. flush_dcache_range(start, end);
  451. /* Switch to next RX descriptor. */
  452. priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CONFIG_RX_DESCR_NUM;
  453. return 0;
  454. }
  455. static int ag7xxx_eth_start(struct udevice *dev)
  456. {
  457. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  458. /* FIXME: Check if link up */
  459. /* Clear the DMA rings. */
  460. ag7xxx_dma_clean_tx(dev);
  461. ag7xxx_dma_clean_rx(dev);
  462. /* Load DMA descriptors and start the RX DMA. */
  463. writel(virt_to_phys(&priv->tx_mac_descrtable[priv->tx_currdescnum]),
  464. priv->regs + AG7XXX_ETH_DMA_TX_DESC);
  465. writel(virt_to_phys(&priv->rx_mac_descrtable[priv->rx_currdescnum]),
  466. priv->regs + AG7XXX_ETH_DMA_RX_DESC);
  467. writel(AG7XXX_ETH_DMA_RX_CTRL_RXE,
  468. priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
  469. return 0;
  470. }
  471. static void ag7xxx_eth_stop(struct udevice *dev)
  472. {
  473. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  474. /* Stop the TX DMA. */
  475. writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
  476. wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
  477. 1000, 0);
  478. /* Stop the RX DMA. */
  479. writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
  480. wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
  481. 1000, 0);
  482. }
  483. /*
  484. * Hardware setup
  485. */
  486. static int ag7xxx_eth_write_hwaddr(struct udevice *dev)
  487. {
  488. struct eth_pdata *pdata = dev_get_plat(dev);
  489. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  490. unsigned char *mac = pdata->enetaddr;
  491. u32 macid_lo, macid_hi;
  492. macid_hi = mac[3] | (mac[2] << 8) | (mac[1] << 16) | (mac[0] << 24);
  493. macid_lo = (mac[5] << 16) | (mac[4] << 24);
  494. writel(macid_lo, priv->regs + AG7XXX_ETH_ADDR1);
  495. writel(macid_hi, priv->regs + AG7XXX_ETH_ADDR2);
  496. return 0;
  497. }
  498. static void ag7xxx_hw_setup(struct udevice *dev)
  499. {
  500. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  501. u32 speed;
  502. setbits_be32(priv->regs + AG7XXX_ETH_CFG1,
  503. AG7XXX_ETH_CFG1_RX_RST | AG7XXX_ETH_CFG1_TX_RST |
  504. AG7XXX_ETH_CFG1_SOFT_RST);
  505. mdelay(10);
  506. writel(AG7XXX_ETH_CFG1_RX_EN | AG7XXX_ETH_CFG1_TX_EN,
  507. priv->regs + AG7XXX_ETH_CFG1);
  508. if (priv->interface == PHY_INTERFACE_MODE_RMII)
  509. speed = AG7XXX_ETH_CFG2_IF_10_100;
  510. else
  511. speed = AG7XXX_ETH_CFG2_IF_1000;
  512. clrsetbits_be32(priv->regs + AG7XXX_ETH_CFG2,
  513. AG7XXX_ETH_CFG2_IF_SPEED_MASK,
  514. speed | AG7XXX_ETH_CFG2_PAD_CRC_EN |
  515. AG7XXX_ETH_CFG2_LEN_CHECK);
  516. writel(0xfff0000, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
  517. writel(0x1fff, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
  518. writel(0x1f00, priv->regs + AG7XXX_ETH_FIFO_CFG_0);
  519. setbits_be32(priv->regs + AG7XXX_ETH_FIFO_CFG_4, 0x3ffff);
  520. writel(0x10ffff, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
  521. writel(0xaaa0555, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
  522. writel(0x7eccf, priv->regs + AG7XXX_ETH_FIFO_CFG_5);
  523. writel(0x1f00140, priv->regs + AG7XXX_ETH_FIFO_CFG_3);
  524. }
  525. static int ag7xxx_mii_get_div(void)
  526. {
  527. ulong freq = get_bus_freq(0);
  528. switch (freq / 1000000) {
  529. case 150: return 0x7;
  530. case 175: return 0x5;
  531. case 200: return 0x4;
  532. case 210: return 0x9;
  533. case 220: return 0x9;
  534. default: return 0x7;
  535. }
  536. }
  537. static int ag7xxx_mii_setup(struct udevice *dev)
  538. {
  539. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  540. int i, ret, div = ag7xxx_mii_get_div();
  541. u32 reg;
  542. if (priv->model == AG7XXX_MODEL_AG933X) {
  543. /* Unit 0 is PHY-less on AR9331, see datasheet Figure 2-3 */
  544. if (priv->interface == PHY_INTERFACE_MODE_RMII)
  545. return 0;
  546. }
  547. if (priv->model == AG7XXX_MODEL_AG934X)
  548. reg = 0x4;
  549. else if (priv->model == AG7XXX_MODEL_AG953X)
  550. reg = 0x2;
  551. else if (priv->model == AG7XXX_MODEL_AG956X)
  552. reg = 0x7;
  553. if (priv->model == AG7XXX_MODEL_AG934X ||
  554. priv->model == AG7XXX_MODEL_AG953X ||
  555. priv->model == AG7XXX_MODEL_AG956X) {
  556. writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | reg,
  557. priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
  558. writel(reg, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
  559. return 0;
  560. }
  561. for (i = 0; i < 10; i++) {
  562. writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | div,
  563. priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
  564. writel(div, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
  565. /* Check the switch */
  566. ret = ag7xxx_switch_reg_read(priv->bus, 0x10c, &reg);
  567. if (ret)
  568. continue;
  569. if (reg != 0x18007fff)
  570. continue;
  571. return 0;
  572. }
  573. return -EINVAL;
  574. }
  575. static int ag933x_phy_setup_wan(struct udevice *dev)
  576. {
  577. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  578. /* Configure switch port 4 (GMAC0) */
  579. return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000);
  580. }
  581. static int ag933x_phy_setup_lan(struct udevice *dev)
  582. {
  583. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  584. int i, ret;
  585. u32 reg;
  586. /* Reset the switch */
  587. ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
  588. if (ret)
  589. return ret;
  590. reg |= BIT(31);
  591. ret = ag7xxx_switch_reg_write(priv->bus, 0, reg);
  592. if (ret)
  593. return ret;
  594. do {
  595. ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
  596. if (ret)
  597. return ret;
  598. } while (reg & BIT(31));
  599. /* Configure switch ports 0...3 (GMAC1) */
  600. for (i = 0; i < 4; i++) {
  601. ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000);
  602. if (ret)
  603. return ret;
  604. }
  605. /* Enable CPU port */
  606. ret = ag7xxx_switch_reg_write(priv->bus, 0x78, BIT(8));
  607. if (ret)
  608. return ret;
  609. for (i = 0; i < 4; i++) {
  610. ret = ag7xxx_switch_reg_write(priv->bus, i * 0x100, BIT(9));
  611. if (ret)
  612. return ret;
  613. }
  614. /* QM Control */
  615. ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
  616. if (ret)
  617. return ret;
  618. /* Disable Atheros header */
  619. ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
  620. if (ret)
  621. return ret;
  622. /* Tag priority mapping */
  623. ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
  624. if (ret)
  625. return ret;
  626. /* Enable ARP packets to the CPU */
  627. ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, &reg);
  628. if (ret)
  629. return ret;
  630. reg |= 0x100000;
  631. ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg);
  632. if (ret)
  633. return ret;
  634. return 0;
  635. }
  636. static int ag953x_phy_setup_wan(struct udevice *dev)
  637. {
  638. int ret;
  639. u32 reg = 0;
  640. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  641. /* Set wan port connect to GE0 */
  642. ret = ag7xxx_switch_reg_read(priv->bus, 0x8, &reg);
  643. if (ret)
  644. return ret;
  645. ret = ag7xxx_switch_reg_write(priv->bus, 0x8, reg | BIT(28));
  646. if (ret)
  647. return ret;
  648. /* Configure switch port 4 (GMAC0) */
  649. ret = ag7xxx_switch_write(priv->bus, 4, MII_BMCR, 0x9000);
  650. if (ret)
  651. return ret;
  652. return 0;
  653. }
  654. static int ag953x_phy_setup_lan(struct udevice *dev)
  655. {
  656. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  657. int i, ret;
  658. u32 reg = 0;
  659. /* Reset the switch */
  660. ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
  661. if (ret)
  662. return ret;
  663. ret = ag7xxx_switch_reg_write(priv->bus, 0, reg | BIT(31));
  664. if (ret)
  665. return ret;
  666. do {
  667. ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
  668. if (ret)
  669. return ret;
  670. } while (reg & BIT(31));
  671. ret = ag7xxx_switch_reg_write(priv->bus, 0x100, 0x4e);
  672. if (ret)
  673. return ret;
  674. /* Set GMII mode */
  675. ret = ag7xxx_switch_reg_read(priv->bus, 0x4, &reg);
  676. if (ret)
  677. return ret;
  678. ret = ag7xxx_switch_reg_write(priv->bus, 0x4, reg | BIT(6));
  679. if (ret)
  680. return ret;
  681. /* Configure switch ports 0...4 (GMAC1) */
  682. for (i = 0; i < 5; i++) {
  683. ret = ag7xxx_switch_write(priv->bus, i, MII_BMCR, 0x9000);
  684. if (ret)
  685. return ret;
  686. }
  687. for (i = 0; i < 5; i++) {
  688. ret = ag7xxx_switch_reg_write(priv->bus, (i + 2) * 0x100, BIT(9));
  689. if (ret)
  690. return ret;
  691. }
  692. /* QM Control */
  693. ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
  694. if (ret)
  695. return ret;
  696. /* Disable Atheros header */
  697. ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
  698. if (ret)
  699. return ret;
  700. /* Tag priority mapping */
  701. ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
  702. if (ret)
  703. return ret;
  704. /* Enable ARP packets to the CPU */
  705. ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, &reg);
  706. if (ret)
  707. return ret;
  708. ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg | 0x100000);
  709. if (ret)
  710. return ret;
  711. /* Enable broadcast packets to the CPU */
  712. ret = ag7xxx_switch_reg_read(priv->bus, 0x2c, &reg);
  713. if (ret)
  714. return ret;
  715. ret = ag7xxx_switch_reg_write(priv->bus, 0x2c, reg | BIT(25) | BIT(26));
  716. if (ret)
  717. return ret;
  718. return 0;
  719. }
  720. static int ag933x_phy_setup_reset_set(struct udevice *dev, int port)
  721. {
  722. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  723. int ret;
  724. if (priv->model == AG7XXX_MODEL_AG953X ||
  725. priv->model == AG7XXX_MODEL_AG956X) {
  726. ret = ag7xxx_switch_write(priv->bus, port, MII_ADVERTISE,
  727. ADVERTISE_ALL);
  728. } else {
  729. ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE,
  730. ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
  731. ADVERTISE_PAUSE_ASYM);
  732. }
  733. if (ret)
  734. return ret;
  735. if (priv->model == AG7XXX_MODEL_AG934X) {
  736. ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000,
  737. ADVERTISE_1000FULL);
  738. if (ret)
  739. return ret;
  740. } else if (priv->model == AG7XXX_MODEL_AG956X) {
  741. ret = ag7xxx_switch_write(priv->bus, port, MII_CTRL1000,
  742. ADVERTISE_1000FULL);
  743. if (ret)
  744. return ret;
  745. }
  746. if (priv->model == AG7XXX_MODEL_AG953X ||
  747. priv->model == AG7XXX_MODEL_AG956X)
  748. return ag7xxx_switch_write(priv->bus, port, MII_BMCR,
  749. BMCR_ANENABLE | BMCR_RESET);
  750. return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR,
  751. BMCR_ANENABLE | BMCR_RESET);
  752. }
  753. static int ag933x_phy_setup_reset_fin(struct udevice *dev, int port)
  754. {
  755. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  756. int ret;
  757. u16 reg;
  758. if (priv->model == AG7XXX_MODEL_AG953X ||
  759. priv->model == AG7XXX_MODEL_AG956X) {
  760. do {
  761. ret = ag7xxx_switch_read(priv->bus, port, MII_BMCR, &reg);
  762. if (ret < 0)
  763. return ret;
  764. mdelay(10);
  765. } while (reg & BMCR_RESET);
  766. } else {
  767. do {
  768. ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR);
  769. if (ret < 0)
  770. return ret;
  771. mdelay(10);
  772. } while (ret & BMCR_RESET);
  773. }
  774. return 0;
  775. }
  776. static int ag933x_phy_setup_common(struct udevice *dev)
  777. {
  778. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  779. int i, ret, phymax;
  780. u16 reg;
  781. if (priv->model == AG7XXX_MODEL_AG933X)
  782. phymax = 4;
  783. else if (priv->model == AG7XXX_MODEL_AG934X ||
  784. priv->model == AG7XXX_MODEL_AG953X ||
  785. priv->model == AG7XXX_MODEL_AG956X)
  786. phymax = 5;
  787. else
  788. return -EINVAL;
  789. if (priv->interface == PHY_INTERFACE_MODE_RMII) {
  790. ret = ag933x_phy_setup_reset_set(dev, phymax);
  791. if (ret)
  792. return ret;
  793. ret = ag933x_phy_setup_reset_fin(dev, phymax);
  794. if (ret)
  795. return ret;
  796. /* Read out link status */
  797. if (priv->model == AG7XXX_MODEL_AG953X)
  798. ret = ag7xxx_switch_read(priv->bus, phymax, MII_MIPSCR, &reg);
  799. else
  800. ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR);
  801. if (ret < 0)
  802. return ret;
  803. return 0;
  804. }
  805. /* Switch ports */
  806. for (i = 0; i < phymax; i++) {
  807. ret = ag933x_phy_setup_reset_set(dev, i);
  808. if (ret)
  809. return ret;
  810. }
  811. for (i = 0; i < phymax; i++) {
  812. ret = ag933x_phy_setup_reset_fin(dev, i);
  813. if (ret)
  814. return ret;
  815. }
  816. for (i = 0; i < phymax; i++) {
  817. /* Read out link status */
  818. if (priv->model == AG7XXX_MODEL_AG953X ||
  819. priv->model == AG7XXX_MODEL_AG956X)
  820. ret = ag7xxx_switch_read(priv->bus, i, MII_MIPSCR, &reg);
  821. else
  822. ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR);
  823. if (ret < 0)
  824. return ret;
  825. }
  826. return 0;
  827. }
  828. static int ag934x_phy_setup(struct udevice *dev)
  829. {
  830. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  831. int i, ret;
  832. u32 reg;
  833. ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f);
  834. if (ret)
  835. return ret;
  836. ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x40000000);
  837. if (ret)
  838. return ret;
  839. ret = ag7xxx_switch_reg_write(priv->bus, 0x4, 0x07600000);
  840. if (ret)
  841. return ret;
  842. ret = ag7xxx_switch_reg_write(priv->bus, 0xc, 0x01000000);
  843. if (ret)
  844. return ret;
  845. ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e);
  846. if (ret)
  847. return ret;
  848. /* AR8327/AR8328 v1.0 fixup */
  849. ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
  850. if (ret)
  851. return ret;
  852. if ((reg & 0xffff) == 0x1201) {
  853. for (i = 0; i < 5; i++) {
  854. ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x0);
  855. if (ret)
  856. return ret;
  857. ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x02ea);
  858. if (ret)
  859. return ret;
  860. ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x3d);
  861. if (ret)
  862. return ret;
  863. ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x68a0);
  864. if (ret)
  865. return ret;
  866. }
  867. }
  868. ret = ag7xxx_switch_reg_read(priv->bus, 0x66c, &reg);
  869. if (ret)
  870. return ret;
  871. reg &= ~0x70000;
  872. ret = ag7xxx_switch_reg_write(priv->bus, 0x66c, reg);
  873. if (ret)
  874. return ret;
  875. return 0;
  876. }
  877. static int ag956x_phy_setup(struct udevice *dev)
  878. {
  879. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  880. int i, ret;
  881. u32 reg, ctrl;
  882. ret = ag7xxx_switch_reg_read(priv->bus, 0x0, &reg);
  883. if (ret)
  884. return ret;
  885. if ((reg & 0xffff) >= 0x1301)
  886. ctrl = 0xc74164de;
  887. else
  888. ctrl = 0xc74164d0;
  889. ret = ag7xxx_switch_reg_write(priv->bus, 0x4, BIT(7));
  890. if (ret)
  891. return ret;
  892. ret = ag7xxx_switch_reg_write(priv->bus, 0xe0, ctrl);
  893. if (ret)
  894. return ret;
  895. ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f);
  896. if (ret)
  897. return ret;
  898. /*
  899. * Values suggested by the switch team when s17 in sgmii
  900. * configuration. 0x10(S17_PWS_REG) = 0x602613a0
  901. */
  902. ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x602613a0);
  903. if (ret)
  904. return ret;
  905. ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e);
  906. if (ret)
  907. return ret;
  908. /* AR8337/AR8334 v1.0 fixup */
  909. ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
  910. if (ret)
  911. return ret;
  912. if ((reg & 0xffff) == 0x1301) {
  913. for (i = 0; i < 5; i++) {
  914. /* Turn on Gigabit clock */
  915. ret = ag7xxx_switch_write(priv->bus, i, 0x1d, 0x3d);
  916. if (ret)
  917. return ret;
  918. ret = ag7xxx_switch_write(priv->bus, i, 0x1e, 0x6820);
  919. if (ret)
  920. return ret;
  921. }
  922. }
  923. return 0;
  924. }
  925. static int ag7xxx_mac_probe(struct udevice *dev)
  926. {
  927. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  928. int ret;
  929. ag7xxx_hw_setup(dev);
  930. ret = ag7xxx_mii_setup(dev);
  931. if (ret)
  932. return ret;
  933. ag7xxx_eth_write_hwaddr(dev);
  934. if (priv->model == AG7XXX_MODEL_AG933X) {
  935. if (priv->interface == PHY_INTERFACE_MODE_RMII)
  936. ret = ag933x_phy_setup_wan(dev);
  937. else
  938. ret = ag933x_phy_setup_lan(dev);
  939. } else if (priv->model == AG7XXX_MODEL_AG953X) {
  940. if (priv->interface == PHY_INTERFACE_MODE_RMII)
  941. ret = ag953x_phy_setup_wan(dev);
  942. else
  943. ret = ag953x_phy_setup_lan(dev);
  944. } else if (priv->model == AG7XXX_MODEL_AG934X) {
  945. ret = ag934x_phy_setup(dev);
  946. } else if (priv->model == AG7XXX_MODEL_AG956X) {
  947. ret = ag956x_phy_setup(dev);
  948. } else {
  949. return -EINVAL;
  950. }
  951. if (ret)
  952. return ret;
  953. return ag933x_phy_setup_common(dev);
  954. }
  955. static int ag7xxx_mdio_probe(struct udevice *dev)
  956. {
  957. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  958. struct mii_dev *bus = mdio_alloc();
  959. if (!bus)
  960. return -ENOMEM;
  961. bus->read = ag7xxx_mdio_read;
  962. bus->write = ag7xxx_mdio_write;
  963. snprintf(bus->name, sizeof(bus->name), dev->name);
  964. bus->priv = (void *)priv;
  965. return mdio_register(bus);
  966. }
  967. static int ag7xxx_get_phy_iface_offset(struct udevice *dev)
  968. {
  969. int offset;
  970. offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), "phy");
  971. if (offset <= 0) {
  972. debug("%s: PHY OF node not found (ret=%i)\n", __func__, offset);
  973. return -EINVAL;
  974. }
  975. offset = fdt_parent_offset(gd->fdt_blob, offset);
  976. if (offset <= 0) {
  977. debug("%s: PHY OF node parent MDIO bus not found (ret=%i)\n",
  978. __func__, offset);
  979. return -EINVAL;
  980. }
  981. offset = fdt_parent_offset(gd->fdt_blob, offset);
  982. if (offset <= 0) {
  983. debug("%s: PHY MDIO OF node parent MAC not found (ret=%i)\n",
  984. __func__, offset);
  985. return -EINVAL;
  986. }
  987. return offset;
  988. }
  989. static int ag7xxx_eth_probe(struct udevice *dev)
  990. {
  991. struct eth_pdata *pdata = dev_get_plat(dev);
  992. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  993. void __iomem *iobase, *phyiobase;
  994. int ret, phyreg;
  995. /* Decoding of convoluted PHY wiring on Atheros MIPS. */
  996. ret = ag7xxx_get_phy_iface_offset(dev);
  997. if (ret <= 0)
  998. return ret;
  999. phyreg = fdtdec_get_int(gd->fdt_blob, ret, "reg", -1);
  1000. iobase = map_physmem(pdata->iobase, 0x200, MAP_NOCACHE);
  1001. phyiobase = map_physmem(phyreg, 0x200, MAP_NOCACHE);
  1002. debug("%s, iobase=%p, phyiobase=%p, priv=%p\n",
  1003. __func__, iobase, phyiobase, priv);
  1004. priv->regs = iobase;
  1005. priv->phyregs = phyiobase;
  1006. priv->interface = pdata->phy_interface;
  1007. priv->model = dev_get_driver_data(dev);
  1008. ret = ag7xxx_mdio_probe(dev);
  1009. if (ret)
  1010. return ret;
  1011. priv->bus = miiphy_get_dev_by_name(dev->name);
  1012. ret = ag7xxx_mac_probe(dev);
  1013. debug("%s, ret=%d\n", __func__, ret);
  1014. return ret;
  1015. }
  1016. static int ag7xxx_eth_remove(struct udevice *dev)
  1017. {
  1018. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  1019. free(priv->phydev);
  1020. mdio_unregister(priv->bus);
  1021. mdio_free(priv->bus);
  1022. return 0;
  1023. }
  1024. static const struct eth_ops ag7xxx_eth_ops = {
  1025. .start = ag7xxx_eth_start,
  1026. .send = ag7xxx_eth_send,
  1027. .recv = ag7xxx_eth_recv,
  1028. .free_pkt = ag7xxx_eth_free_pkt,
  1029. .stop = ag7xxx_eth_stop,
  1030. .write_hwaddr = ag7xxx_eth_write_hwaddr,
  1031. };
  1032. static int ag7xxx_eth_of_to_plat(struct udevice *dev)
  1033. {
  1034. struct eth_pdata *pdata = dev_get_plat(dev);
  1035. const char *phy_mode;
  1036. int ret;
  1037. pdata->iobase = dev_read_addr(dev);
  1038. pdata->phy_interface = -1;
  1039. /* Decoding of convoluted PHY wiring on Atheros MIPS. */
  1040. ret = ag7xxx_get_phy_iface_offset(dev);
  1041. if (ret <= 0)
  1042. return ret;
  1043. phy_mode = fdt_getprop(gd->fdt_blob, ret, "phy-mode", NULL);
  1044. if (phy_mode)
  1045. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  1046. if (pdata->phy_interface == -1) {
  1047. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  1048. return -EINVAL;
  1049. }
  1050. return 0;
  1051. }
  1052. static const struct udevice_id ag7xxx_eth_ids[] = {
  1053. { .compatible = "qca,ag933x-mac", .data = AG7XXX_MODEL_AG933X },
  1054. { .compatible = "qca,ag934x-mac", .data = AG7XXX_MODEL_AG934X },
  1055. { .compatible = "qca,ag953x-mac", .data = AG7XXX_MODEL_AG953X },
  1056. { .compatible = "qca,ag956x-mac", .data = AG7XXX_MODEL_AG956X },
  1057. { }
  1058. };
  1059. U_BOOT_DRIVER(eth_ag7xxx) = {
  1060. .name = "eth_ag7xxx",
  1061. .id = UCLASS_ETH,
  1062. .of_match = ag7xxx_eth_ids,
  1063. .of_to_plat = ag7xxx_eth_of_to_plat,
  1064. .probe = ag7xxx_eth_probe,
  1065. .remove = ag7xxx_eth_remove,
  1066. .ops = &ag7xxx_eth_ops,
  1067. .priv_auto = sizeof(struct ar7xxx_eth_priv),
  1068. .plat_auto = sizeof(struct eth_pdata),
  1069. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  1070. };