jedec_flash.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Michael Schwingen, <michael@schwingen.org>
  5. *
  6. * based in great part on jedec_probe.c from linux kernel:
  7. * (C) 2000 Red Hat. GPL'd.
  8. * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
  9. */
  10. /* The DEBUG define must be before common to enable debugging */
  11. /*#define DEBUG*/
  12. #include <common.h>
  13. #include <flash.h>
  14. #include <log.h>
  15. #include <asm/processor.h>
  16. #include <asm/io.h>
  17. #include <asm/byteorder.h>
  18. #define P_ID_AMD_STD CFI_CMDSET_AMD_LEGACY
  19. /* AMD */
  20. #define AM29DL800BB 0x22CB
  21. #define AM29DL800BT 0x224A
  22. #define AM29F400BB 0x22AB
  23. #define AM29F800BB 0x2258
  24. #define AM29F800BT 0x22D6
  25. #define AM29LV400BB 0x22BA
  26. #define AM29LV400BT 0x22B9
  27. #define AM29LV800BB 0x225B
  28. #define AM29LV800BT 0x22DA
  29. #define AM29LV160DT 0x22C4
  30. #define AM29LV160DB 0x2249
  31. #define AM29F017D 0x003D
  32. #define AM29F016D 0x00AD
  33. #define AM29F080 0x00D5
  34. #define AM29F040 0x00A4
  35. #define AM29LV040B 0x004F
  36. #define AM29F032B 0x0041
  37. #define AM29F002T 0x00B0
  38. /* SST */
  39. #define SST39LF800 0x2781
  40. #define SST39LF160 0x2782
  41. #define SST39VF1601 0x234b
  42. #define SST39LF512 0x00D4
  43. #define SST39LF010 0x00D5
  44. #define SST39LF020 0x00D6
  45. #define SST39LF040 0x00D7
  46. #define SST39SF010A 0x00B5
  47. #define SST39SF020A 0x00B6
  48. /* STM */
  49. #define STM29F400BB 0x00D6
  50. /* MXIC */
  51. #define MX29LV040 0x004F
  52. /* WINBOND */
  53. #define W39L040A 0x00D6
  54. /* AMIC */
  55. #define A29L040 0x0092
  56. /* EON */
  57. #define EN29LV040A 0x004F
  58. /*
  59. * Unlock address sets for AMD command sets.
  60. * Intel command sets use the MTD_UADDR_UNNECESSARY.
  61. * Each identifier, except MTD_UADDR_UNNECESSARY, and
  62. * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[].
  63. * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure
  64. * initialization need not require initializing all of the
  65. * unlock addresses for all bit widths.
  66. */
  67. enum uaddr {
  68. MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */
  69. MTD_UADDR_0x0555_0x02AA,
  70. MTD_UADDR_0x0555_0x0AAA,
  71. MTD_UADDR_0x5555_0x2AAA,
  72. MTD_UADDR_0x0AAA_0x0555,
  73. MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */
  74. MTD_UADDR_UNNECESSARY, /* Does not require any address */
  75. };
  76. struct unlock_addr {
  77. u32 addr1;
  78. u32 addr2;
  79. };
  80. /*
  81. * I don't like the fact that the first entry in unlock_addrs[]
  82. * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
  83. * should not be used. The problem is that structures with
  84. * initializers have extra fields initialized to 0. It is _very_
  85. * desireable to have the unlock address entries for unsupported
  86. * data widths automatically initialized - that means that
  87. * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here
  88. * must go unused.
  89. */
  90. static const struct unlock_addr unlock_addrs[] = {
  91. [MTD_UADDR_NOT_SUPPORTED] = {
  92. .addr1 = 0xffff,
  93. .addr2 = 0xffff
  94. },
  95. [MTD_UADDR_0x0555_0x02AA] = {
  96. .addr1 = 0x0555,
  97. .addr2 = 0x02aa
  98. },
  99. [MTD_UADDR_0x0555_0x0AAA] = {
  100. .addr1 = 0x0555,
  101. .addr2 = 0x0aaa
  102. },
  103. [MTD_UADDR_0x5555_0x2AAA] = {
  104. .addr1 = 0x5555,
  105. .addr2 = 0x2aaa
  106. },
  107. [MTD_UADDR_0x0AAA_0x0555] = {
  108. .addr1 = 0x0AAA,
  109. .addr2 = 0x0555
  110. },
  111. [MTD_UADDR_DONT_CARE] = {
  112. .addr1 = 0x0000, /* Doesn't matter which address */
  113. .addr2 = 0x0000 /* is used - must be last entry */
  114. },
  115. [MTD_UADDR_UNNECESSARY] = {
  116. .addr1 = 0x0000,
  117. .addr2 = 0x0000
  118. }
  119. };
  120. struct amd_flash_info {
  121. const __u16 mfr_id;
  122. const __u16 dev_id;
  123. const char *name;
  124. const int DevSize;
  125. const int NumEraseRegions;
  126. const int CmdSet;
  127. const __u8 uaddr[4]; /* unlock addrs for 8, 16, 32, 64 */
  128. const ulong regions[6];
  129. };
  130. #define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
  131. #define SIZE_64KiB 16
  132. #define SIZE_128KiB 17
  133. #define SIZE_256KiB 18
  134. #define SIZE_512KiB 19
  135. #define SIZE_1MiB 20
  136. #define SIZE_2MiB 21
  137. #define SIZE_4MiB 22
  138. #define SIZE_8MiB 23
  139. static const struct amd_flash_info jedec_table[] = {
  140. #ifdef CONFIG_SYS_FLASH_LEGACY_256Kx8
  141. {
  142. .mfr_id = (u16)SST_MANUFACT,
  143. .dev_id = SST39LF020,
  144. .name = "SST 39LF020",
  145. .uaddr = {
  146. [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
  147. },
  148. .DevSize = SIZE_256KiB,
  149. .CmdSet = P_ID_AMD_STD,
  150. .NumEraseRegions= 1,
  151. .regions = {
  152. ERASEINFO(0x01000,64),
  153. }
  154. },
  155. #endif
  156. #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx8
  157. {
  158. .mfr_id = (u16)AMD_MANUFACT,
  159. .dev_id = AM29LV040B,
  160. .name = "AMD AM29LV040B",
  161. .uaddr = {
  162. [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
  163. },
  164. .DevSize = SIZE_512KiB,
  165. .CmdSet = P_ID_AMD_STD,
  166. .NumEraseRegions= 1,
  167. .regions = {
  168. ERASEINFO(0x10000,8),
  169. }
  170. },
  171. {
  172. .mfr_id = (u16)SST_MANUFACT,
  173. .dev_id = SST39LF040,
  174. .name = "SST 39LF040",
  175. .uaddr = {
  176. [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
  177. },
  178. .DevSize = SIZE_512KiB,
  179. .CmdSet = P_ID_AMD_STD,
  180. .NumEraseRegions= 1,
  181. .regions = {
  182. ERASEINFO(0x01000,128),
  183. }
  184. },
  185. {
  186. .mfr_id = (u16)STM_MANUFACT,
  187. .dev_id = STM_ID_M29W040B,
  188. .name = "ST Micro M29W040B",
  189. .uaddr = {
  190. [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
  191. },
  192. .DevSize = SIZE_512KiB,
  193. .CmdSet = P_ID_AMD_STD,
  194. .NumEraseRegions= 1,
  195. .regions = {
  196. ERASEINFO(0x10000,8),
  197. }
  198. },
  199. {
  200. .mfr_id = (u16)MX_MANUFACT,
  201. .dev_id = MX29LV040,
  202. .name = "MXIC MX29LV040",
  203. .uaddr = {
  204. [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
  205. },
  206. .DevSize = SIZE_512KiB,
  207. .CmdSet = P_ID_AMD_STD,
  208. .NumEraseRegions= 1,
  209. .regions = {
  210. ERASEINFO(0x10000, 8),
  211. }
  212. },
  213. {
  214. .mfr_id = (u16)WINB_MANUFACT,
  215. .dev_id = W39L040A,
  216. .name = "WINBOND W39L040A",
  217. .uaddr = {
  218. [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
  219. },
  220. .DevSize = SIZE_512KiB,
  221. .CmdSet = P_ID_AMD_STD,
  222. .NumEraseRegions= 1,
  223. .regions = {
  224. ERASEINFO(0x10000, 8),
  225. }
  226. },
  227. {
  228. .mfr_id = (u16)AMIC_MANUFACT,
  229. .dev_id = A29L040,
  230. .name = "AMIC A29L040",
  231. .uaddr = {
  232. [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
  233. },
  234. .DevSize = SIZE_512KiB,
  235. .CmdSet = P_ID_AMD_STD,
  236. .NumEraseRegions= 1,
  237. .regions = {
  238. ERASEINFO(0x10000, 8),
  239. }
  240. },
  241. {
  242. .mfr_id = (u16)EON_MANUFACT,
  243. .dev_id = EN29LV040A,
  244. .name = "EON EN29LV040A",
  245. .uaddr = {
  246. [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
  247. },
  248. .DevSize = SIZE_512KiB,
  249. .CmdSet = P_ID_AMD_STD,
  250. .NumEraseRegions= 1,
  251. .regions = {
  252. ERASEINFO(0x10000, 8),
  253. }
  254. },
  255. #endif
  256. #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16
  257. {
  258. .mfr_id = (u16)AMD_MANUFACT,
  259. .dev_id = AM29F400BB,
  260. .name = "AMD AM29F400BB",
  261. .uaddr = {
  262. [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
  263. },
  264. .DevSize = SIZE_512KiB,
  265. .CmdSet = CFI_CMDSET_AMD_LEGACY,
  266. .NumEraseRegions= 4,
  267. .regions = {
  268. ERASEINFO(0x04000, 1),
  269. ERASEINFO(0x02000, 2),
  270. ERASEINFO(0x08000, 1),
  271. ERASEINFO(0x10000, 7),
  272. }
  273. },
  274. {
  275. .mfr_id = (u16)AMD_MANUFACT,
  276. .dev_id = AM29LV400BB,
  277. .name = "AMD AM29LV400BB",
  278. .uaddr = {
  279. [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
  280. },
  281. .DevSize = SIZE_512KiB,
  282. .CmdSet = CFI_CMDSET_AMD_LEGACY,
  283. .NumEraseRegions= 4,
  284. .regions = {
  285. ERASEINFO(0x04000,1),
  286. ERASEINFO(0x02000,2),
  287. ERASEINFO(0x08000,1),
  288. ERASEINFO(0x10000,7),
  289. }
  290. },
  291. {
  292. .mfr_id = (u16)AMD_MANUFACT,
  293. .dev_id = AM29LV800BB,
  294. .name = "AMD AM29LV800BB",
  295. .uaddr = {
  296. [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
  297. },
  298. .DevSize = SIZE_1MiB,
  299. .CmdSet = CFI_CMDSET_AMD_LEGACY,
  300. .NumEraseRegions= 4,
  301. .regions = {
  302. ERASEINFO(0x04000, 1),
  303. ERASEINFO(0x02000, 2),
  304. ERASEINFO(0x08000, 1),
  305. ERASEINFO(0x10000, 15),
  306. }
  307. },
  308. {
  309. .mfr_id = (u16)AMD_MANUFACT,
  310. .dev_id = AM29LV800BT,
  311. .name = "AMD AM29LV800BT",
  312. .uaddr = {
  313. [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
  314. },
  315. .DevSize = SIZE_1MiB,
  316. .CmdSet = CFI_CMDSET_AMD_LEGACY,
  317. .NumEraseRegions= 4,
  318. .regions = {
  319. ERASEINFO(0x10000, 15),
  320. ERASEINFO(0x08000, 1),
  321. ERASEINFO(0x02000, 2),
  322. ERASEINFO(0x04000, 1),
  323. }
  324. },
  325. {
  326. .mfr_id = (u16)MX_MANUFACT,
  327. .dev_id = AM29LV800BT,
  328. .name = "MXIC MX29LV800BT",
  329. .uaddr = {
  330. [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
  331. },
  332. .DevSize = SIZE_1MiB,
  333. .CmdSet = CFI_CMDSET_AMD_LEGACY,
  334. .NumEraseRegions= 4,
  335. .regions = {
  336. ERASEINFO(0x10000, 15),
  337. ERASEINFO(0x08000, 1),
  338. ERASEINFO(0x02000, 2),
  339. ERASEINFO(0x04000, 1),
  340. }
  341. },
  342. {
  343. .mfr_id = (u16)EON_ALT_MANU,
  344. .dev_id = AM29LV800BT,
  345. .name = "EON EN29LV800BT",
  346. .uaddr = {
  347. [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
  348. },
  349. .DevSize = SIZE_1MiB,
  350. .CmdSet = CFI_CMDSET_AMD_LEGACY,
  351. .NumEraseRegions= 4,
  352. .regions = {
  353. ERASEINFO(0x10000, 15),
  354. ERASEINFO(0x08000, 1),
  355. ERASEINFO(0x02000, 2),
  356. ERASEINFO(0x04000, 1),
  357. }
  358. },
  359. {
  360. .mfr_id = (u16)STM_MANUFACT,
  361. .dev_id = STM29F400BB,
  362. .name = "ST Micro M29F400BB",
  363. .uaddr = {
  364. [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
  365. },
  366. .DevSize = SIZE_512KiB,
  367. .CmdSet = CFI_CMDSET_AMD_LEGACY,
  368. .NumEraseRegions = 4,
  369. .regions = {
  370. ERASEINFO(0x04000, 1),
  371. ERASEINFO(0x02000, 2),
  372. ERASEINFO(0x08000, 1),
  373. ERASEINFO(0x10000, 7),
  374. }
  375. },
  376. #endif
  377. };
  378. static inline void fill_info(flash_info_t *info, const struct amd_flash_info *jedec_entry, ulong base)
  379. {
  380. int i,j;
  381. int sect_cnt;
  382. int size_ratio;
  383. int total_size;
  384. enum uaddr uaddr_idx;
  385. size_ratio = info->portwidth / info->chipwidth;
  386. debug("Found JEDEC Flash: %s\n", jedec_entry->name);
  387. info->vendor = jedec_entry->CmdSet;
  388. /* Todo: do we need device-specific timeouts? */
  389. info->erase_blk_tout = 30000;
  390. info->buffer_write_tout = 1000;
  391. info->write_tout = 100;
  392. info->name = jedec_entry->name;
  393. /* copy unlock addresses from device table to CFI info struct. This
  394. is just here because the addresses are in the table anyway - if
  395. the flash is not detected due to wrong unlock addresses,
  396. flash_detect_legacy would have to try all of them before we even
  397. get here. */
  398. switch(info->chipwidth) {
  399. case FLASH_CFI_8BIT:
  400. uaddr_idx = jedec_entry->uaddr[0];
  401. break;
  402. case FLASH_CFI_16BIT:
  403. uaddr_idx = jedec_entry->uaddr[1];
  404. break;
  405. case FLASH_CFI_32BIT:
  406. uaddr_idx = jedec_entry->uaddr[2];
  407. break;
  408. default:
  409. uaddr_idx = MTD_UADDR_NOT_SUPPORTED;
  410. break;
  411. }
  412. debug("unlock address index %d\n", uaddr_idx);
  413. info->addr_unlock1 = unlock_addrs[uaddr_idx].addr1;
  414. info->addr_unlock2 = unlock_addrs[uaddr_idx].addr2;
  415. debug("unlock addresses are 0x%lx/0x%lx\n",
  416. info->addr_unlock1, info->addr_unlock2);
  417. sect_cnt = 0;
  418. total_size = 0;
  419. for (i = 0; i < jedec_entry->NumEraseRegions; i++) {
  420. ulong erase_region_size = jedec_entry->regions[i] >> 8;
  421. ulong erase_region_count = (jedec_entry->regions[i] & 0xff) + 1;
  422. total_size += erase_region_size * erase_region_count;
  423. debug("erase_region_count = %ld erase_region_size = %ld\n",
  424. erase_region_count, erase_region_size);
  425. for (j = 0; j < erase_region_count; j++) {
  426. if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) {
  427. printf("ERROR: too many flash sectors\n");
  428. break;
  429. }
  430. info->start[sect_cnt] = base;
  431. base += (erase_region_size * size_ratio);
  432. sect_cnt++;
  433. }
  434. }
  435. info->sector_count = sect_cnt;
  436. info->size = total_size * size_ratio;
  437. }
  438. /*-----------------------------------------------------------------------
  439. * match jedec ids against table. If a match is found, fill flash_info entry
  440. */
  441. int jedec_flash_match(flash_info_t *info, ulong base)
  442. {
  443. int ret = 0;
  444. int i;
  445. ulong mask = 0xFFFF;
  446. if (info->chipwidth == 1)
  447. mask = 0xFF;
  448. for (i = 0; i < ARRAY_SIZE(jedec_table); i++) {
  449. if ((jedec_table[i].mfr_id & mask) == (info->manufacturer_id & mask) &&
  450. (jedec_table[i].dev_id & mask) == (info->device_id & mask)) {
  451. fill_info(info, &jedec_table[i], base);
  452. ret = 1;
  453. break;
  454. }
  455. }
  456. return ret;
  457. }