sunxi_mmc.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2011
  4. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  5. * Aaron <leafy.myeh@allwinnertech.com>
  6. *
  7. * MMC driver for allwinner sunxi platform.
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <log.h>
  13. #include <malloc.h>
  14. #include <mmc.h>
  15. #include <clk.h>
  16. #include <reset.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/gpio.h>
  21. #include <asm/arch/mmc.h>
  22. #include <asm-generic/gpio.h>
  23. #include <linux/delay.h>
  24. #ifndef CCM_MMC_CTRL_MODE_SEL_NEW
  25. #define CCM_MMC_CTRL_MODE_SEL_NEW 0
  26. #endif
  27. struct sunxi_mmc_plat {
  28. struct mmc_config cfg;
  29. struct mmc mmc;
  30. };
  31. struct sunxi_mmc_priv {
  32. unsigned mmc_no;
  33. uint32_t *mclkreg;
  34. unsigned fatal_err;
  35. struct gpio_desc cd_gpio; /* Change Detect GPIO */
  36. struct sunxi_mmc *reg;
  37. struct mmc_config cfg;
  38. };
  39. #if !CONFIG_IS_ENABLED(DM_MMC)
  40. /* support 4 mmc hosts */
  41. struct sunxi_mmc_priv mmc_host[4];
  42. static int sunxi_mmc_getcd_gpio(int sdc_no)
  43. {
  44. switch (sdc_no) {
  45. case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
  46. case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
  47. case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
  48. case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
  49. }
  50. return -EINVAL;
  51. }
  52. static int mmc_resource_init(int sdc_no)
  53. {
  54. struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
  55. struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  56. int cd_pin, ret = 0;
  57. debug("init mmc %d resource\n", sdc_no);
  58. switch (sdc_no) {
  59. case 0:
  60. priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
  61. priv->mclkreg = &ccm->sd0_clk_cfg;
  62. break;
  63. case 1:
  64. priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
  65. priv->mclkreg = &ccm->sd1_clk_cfg;
  66. break;
  67. case 2:
  68. priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
  69. priv->mclkreg = &ccm->sd2_clk_cfg;
  70. break;
  71. #ifdef SUNXI_MMC3_BASE
  72. case 3:
  73. priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
  74. priv->mclkreg = &ccm->sd3_clk_cfg;
  75. break;
  76. #endif
  77. default:
  78. printf("Wrong mmc number %d\n", sdc_no);
  79. return -1;
  80. }
  81. priv->mmc_no = sdc_no;
  82. cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
  83. if (cd_pin >= 0) {
  84. ret = gpio_request(cd_pin, "mmc_cd");
  85. if (!ret) {
  86. sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
  87. ret = gpio_direction_input(cd_pin);
  88. }
  89. }
  90. return ret;
  91. }
  92. #endif
  93. /*
  94. * All A64 and later MMC controllers feature auto-calibration. This would
  95. * normally be detected via the compatible string, but we need something
  96. * which works in the SPL as well.
  97. */
  98. static bool sunxi_mmc_can_calibrate(void)
  99. {
  100. return IS_ENABLED(CONFIG_MACH_SUN50I) ||
  101. IS_ENABLED(CONFIG_MACH_SUN50I_H5) ||
  102. IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
  103. IS_ENABLED(CONFIG_MACH_SUN8I_R40);
  104. }
  105. static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
  106. {
  107. unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
  108. bool new_mode = IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE);
  109. u32 val = 0;
  110. /* A83T support new mode only on eMMC */
  111. if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
  112. new_mode = false;
  113. if (hz <= 24000000) {
  114. pll = CCM_MMC_CTRL_OSCM24;
  115. pll_hz = 24000000;
  116. } else {
  117. #ifdef CONFIG_MACH_SUN9I
  118. pll = CCM_MMC_CTRL_PLL_PERIPH0;
  119. pll_hz = clock_get_pll4_periph0();
  120. #else
  121. /*
  122. * SoCs since the A64 (H5, H6, H616) actually use the doubled
  123. * rate of PLL6/PERIPH0 as an input clock, but compensate for
  124. * that with a fixed post-divider of 2 in the mod clock.
  125. * This cancels each other out, so for simplicity we just
  126. * pretend it's always PLL6 without a post divider here.
  127. */
  128. pll = CCM_MMC_CTRL_PLL6;
  129. pll_hz = clock_get_pll6();
  130. #endif
  131. }
  132. div = pll_hz / hz;
  133. if (pll_hz % hz)
  134. div++;
  135. n = 0;
  136. while (div > 16) {
  137. n++;
  138. div = (div + 1) / 2;
  139. }
  140. if (n > 3) {
  141. printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
  142. hz);
  143. return -1;
  144. }
  145. /* determine delays */
  146. if (hz <= 400000) {
  147. oclk_dly = 0;
  148. sclk_dly = 0;
  149. } else if (hz <= 25000000) {
  150. oclk_dly = 0;
  151. sclk_dly = 5;
  152. } else {
  153. if (IS_ENABLED(CONFIG_MACH_SUN9I)) {
  154. if (hz <= 52000000)
  155. oclk_dly = 5;
  156. else
  157. oclk_dly = 2;
  158. } else {
  159. if (hz <= 52000000)
  160. oclk_dly = 3;
  161. else
  162. oclk_dly = 1;
  163. }
  164. sclk_dly = 4;
  165. }
  166. if (new_mode) {
  167. val |= CCM_MMC_CTRL_MODE_SEL_NEW;
  168. setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
  169. }
  170. if (!sunxi_mmc_can_calibrate()) {
  171. /*
  172. * Use hardcoded delay values if controller doesn't support
  173. * calibration
  174. */
  175. val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
  176. CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
  177. }
  178. writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
  179. CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
  180. debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
  181. priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
  182. return 0;
  183. }
  184. static int mmc_update_clk(struct sunxi_mmc_priv *priv)
  185. {
  186. unsigned int cmd;
  187. unsigned timeout_msecs = 2000;
  188. unsigned long start = get_timer(0);
  189. cmd = SUNXI_MMC_CMD_START |
  190. SUNXI_MMC_CMD_UPCLK_ONLY |
  191. SUNXI_MMC_CMD_WAIT_PRE_OVER;
  192. writel(cmd, &priv->reg->cmd);
  193. while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
  194. if (get_timer(start) > timeout_msecs)
  195. return -1;
  196. }
  197. /* clock update sets various irq status bits, clear these */
  198. writel(readl(&priv->reg->rint), &priv->reg->rint);
  199. return 0;
  200. }
  201. static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
  202. {
  203. unsigned rval = readl(&priv->reg->clkcr);
  204. /* Disable Clock */
  205. rval &= ~SUNXI_MMC_CLK_ENABLE;
  206. writel(rval, &priv->reg->clkcr);
  207. if (mmc_update_clk(priv))
  208. return -1;
  209. /* Set mod_clk to new rate */
  210. if (mmc_set_mod_clk(priv, mmc->clock))
  211. return -1;
  212. /* Clear internal divider */
  213. rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
  214. writel(rval, &priv->reg->clkcr);
  215. #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
  216. /* A64 supports calibration of delays on MMC controller and we
  217. * have to set delay of zero before starting calibration.
  218. * Allwinner BSP driver sets a delay only in the case of
  219. * using HS400 which is not supported by mainline U-Boot or
  220. * Linux at the moment
  221. */
  222. if (sunxi_mmc_can_calibrate())
  223. writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
  224. #endif
  225. /* Re-enable Clock */
  226. rval |= SUNXI_MMC_CLK_ENABLE;
  227. writel(rval, &priv->reg->clkcr);
  228. if (mmc_update_clk(priv))
  229. return -1;
  230. return 0;
  231. }
  232. static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
  233. struct mmc *mmc)
  234. {
  235. debug("set ios: bus_width: %x, clock: %d\n",
  236. mmc->bus_width, mmc->clock);
  237. /* Change clock first */
  238. if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
  239. priv->fatal_err = 1;
  240. return -EINVAL;
  241. }
  242. /* Change bus width */
  243. if (mmc->bus_width == 8)
  244. writel(0x2, &priv->reg->width);
  245. else if (mmc->bus_width == 4)
  246. writel(0x1, &priv->reg->width);
  247. else
  248. writel(0x0, &priv->reg->width);
  249. return 0;
  250. }
  251. #if !CONFIG_IS_ENABLED(DM_MMC)
  252. static int sunxi_mmc_core_init(struct mmc *mmc)
  253. {
  254. struct sunxi_mmc_priv *priv = mmc->priv;
  255. /* Reset controller */
  256. writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
  257. udelay(1000);
  258. return 0;
  259. }
  260. #endif
  261. static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
  262. struct mmc_data *data)
  263. {
  264. const int reading = !!(data->flags & MMC_DATA_READ);
  265. const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
  266. SUNXI_MMC_STATUS_FIFO_FULL;
  267. unsigned i;
  268. unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
  269. unsigned word_cnt = (data->blocksize * data->blocks) >> 2;
  270. unsigned timeout_msecs = word_cnt >> 6;
  271. uint32_t status;
  272. unsigned long start;
  273. if (timeout_msecs < 2000)
  274. timeout_msecs = 2000;
  275. /* Always read / write data through the CPU */
  276. setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
  277. start = get_timer(0);
  278. for (i = 0; i < word_cnt;) {
  279. unsigned int in_fifo;
  280. while ((status = readl(&priv->reg->status)) & status_bit) {
  281. if (get_timer(start) > timeout_msecs)
  282. return -1;
  283. }
  284. /*
  285. * For writing we do not easily know the FIFO size, so have
  286. * to check the FIFO status after every word written.
  287. * TODO: For optimisation we could work out a minimum FIFO
  288. * size across all SoCs, and use that together with the current
  289. * fill level to write chunks of words.
  290. */
  291. if (!reading) {
  292. writel(buff[i++], &priv->reg->fifo);
  293. continue;
  294. }
  295. /*
  296. * The status register holds the current FIFO level, so we
  297. * can be sure to collect as many words from the FIFO
  298. * register without checking the status register after every
  299. * read. That saves half of the costly MMIO reads, effectively
  300. * doubling the read performance.
  301. * Some SoCs (A20) report a level of 0 if the FIFO is
  302. * completely full (value masked out?). Use a safe minimal
  303. * FIFO size in this case.
  304. */
  305. in_fifo = SUNXI_MMC_STATUS_FIFO_LEVEL(status);
  306. if (in_fifo == 0 && (status & SUNXI_MMC_STATUS_FIFO_FULL))
  307. in_fifo = 32;
  308. for (; in_fifo > 0; in_fifo--)
  309. buff[i++] = readl_relaxed(&priv->reg->fifo);
  310. dmb();
  311. }
  312. return 0;
  313. }
  314. static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
  315. uint timeout_msecs, uint done_bit, const char *what)
  316. {
  317. unsigned int status;
  318. unsigned long start = get_timer(0);
  319. do {
  320. status = readl(&priv->reg->rint);
  321. if ((get_timer(start) > timeout_msecs) ||
  322. (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
  323. debug("%s timeout %x\n", what,
  324. status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
  325. return -ETIMEDOUT;
  326. }
  327. } while (!(status & done_bit));
  328. return 0;
  329. }
  330. static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
  331. struct mmc *mmc, struct mmc_cmd *cmd,
  332. struct mmc_data *data)
  333. {
  334. unsigned int cmdval = SUNXI_MMC_CMD_START;
  335. unsigned int timeout_msecs;
  336. int error = 0;
  337. unsigned int status = 0;
  338. unsigned int bytecnt = 0;
  339. if (priv->fatal_err)
  340. return -1;
  341. if (cmd->resp_type & MMC_RSP_BUSY)
  342. debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
  343. if (cmd->cmdidx == 12)
  344. return 0;
  345. if (!cmd->cmdidx)
  346. cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
  347. if (cmd->resp_type & MMC_RSP_PRESENT)
  348. cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
  349. if (cmd->resp_type & MMC_RSP_136)
  350. cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
  351. if (cmd->resp_type & MMC_RSP_CRC)
  352. cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
  353. if (data) {
  354. if ((u32)(long)data->dest & 0x3) {
  355. error = -1;
  356. goto out;
  357. }
  358. cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
  359. if (data->flags & MMC_DATA_WRITE)
  360. cmdval |= SUNXI_MMC_CMD_WRITE;
  361. if (data->blocks > 1)
  362. cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
  363. writel(data->blocksize, &priv->reg->blksz);
  364. writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
  365. }
  366. debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
  367. cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
  368. writel(cmd->cmdarg, &priv->reg->arg);
  369. if (!data)
  370. writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
  371. /*
  372. * transfer data and check status
  373. * STATREG[2] : FIFO empty
  374. * STATREG[3] : FIFO full
  375. */
  376. if (data) {
  377. int ret = 0;
  378. bytecnt = data->blocksize * data->blocks;
  379. debug("trans data %d bytes\n", bytecnt);
  380. writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
  381. ret = mmc_trans_data_by_cpu(priv, mmc, data);
  382. if (ret) {
  383. error = readl(&priv->reg->rint) &
  384. SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
  385. error = -ETIMEDOUT;
  386. goto out;
  387. }
  388. }
  389. error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
  390. "cmd");
  391. if (error)
  392. goto out;
  393. if (data) {
  394. timeout_msecs = 120;
  395. debug("cacl timeout %x msec\n", timeout_msecs);
  396. error = mmc_rint_wait(priv, mmc, timeout_msecs,
  397. data->blocks > 1 ?
  398. SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
  399. SUNXI_MMC_RINT_DATA_OVER,
  400. "data");
  401. if (error)
  402. goto out;
  403. }
  404. if (cmd->resp_type & MMC_RSP_BUSY) {
  405. unsigned long start = get_timer(0);
  406. timeout_msecs = 2000;
  407. do {
  408. status = readl(&priv->reg->status);
  409. if (get_timer(start) > timeout_msecs) {
  410. debug("busy timeout\n");
  411. error = -ETIMEDOUT;
  412. goto out;
  413. }
  414. } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
  415. }
  416. if (cmd->resp_type & MMC_RSP_136) {
  417. cmd->response[0] = readl(&priv->reg->resp3);
  418. cmd->response[1] = readl(&priv->reg->resp2);
  419. cmd->response[2] = readl(&priv->reg->resp1);
  420. cmd->response[3] = readl(&priv->reg->resp0);
  421. debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
  422. cmd->response[3], cmd->response[2],
  423. cmd->response[1], cmd->response[0]);
  424. } else {
  425. cmd->response[0] = readl(&priv->reg->resp0);
  426. debug("mmc resp 0x%08x\n", cmd->response[0]);
  427. }
  428. out:
  429. if (error < 0) {
  430. writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
  431. mmc_update_clk(priv);
  432. }
  433. writel(0xffffffff, &priv->reg->rint);
  434. writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
  435. &priv->reg->gctrl);
  436. return error;
  437. }
  438. #if !CONFIG_IS_ENABLED(DM_MMC)
  439. static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
  440. {
  441. struct sunxi_mmc_priv *priv = mmc->priv;
  442. return sunxi_mmc_set_ios_common(priv, mmc);
  443. }
  444. static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
  445. struct mmc_data *data)
  446. {
  447. struct sunxi_mmc_priv *priv = mmc->priv;
  448. return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
  449. }
  450. static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
  451. {
  452. struct sunxi_mmc_priv *priv = mmc->priv;
  453. int cd_pin;
  454. cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
  455. if (cd_pin < 0)
  456. return 1;
  457. return !gpio_get_value(cd_pin);
  458. }
  459. static const struct mmc_ops sunxi_mmc_ops = {
  460. .send_cmd = sunxi_mmc_send_cmd_legacy,
  461. .set_ios = sunxi_mmc_set_ios_legacy,
  462. .init = sunxi_mmc_core_init,
  463. .getcd = sunxi_mmc_getcd_legacy,
  464. };
  465. struct mmc *sunxi_mmc_init(int sdc_no)
  466. {
  467. struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  468. struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
  469. struct mmc_config *cfg = &priv->cfg;
  470. int ret;
  471. memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
  472. cfg->name = "SUNXI SD/MMC";
  473. cfg->ops = &sunxi_mmc_ops;
  474. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  475. cfg->host_caps = MMC_MODE_4BIT;
  476. if ((IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_MACH_SUN8I) ||
  477. IS_ENABLED(CONFIG_SUN50I_GEN_H6)) && (sdc_no == 2))
  478. cfg->host_caps = MMC_MODE_8BIT;
  479. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  480. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  481. cfg->f_min = 400000;
  482. cfg->f_max = 52000000;
  483. if (mmc_resource_init(sdc_no) != 0)
  484. return NULL;
  485. /* config ahb clock */
  486. debug("init mmc %d clock and io\n", sdc_no);
  487. #if !defined(CONFIG_SUN50I_GEN_H6)
  488. setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
  489. #ifdef CONFIG_SUNXI_GEN_SUN6I
  490. /* unassert reset */
  491. setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
  492. #endif
  493. #if defined(CONFIG_MACH_SUN9I)
  494. /* sun9i has a mmc-common module, also set the gate and reset there */
  495. writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
  496. SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
  497. #endif
  498. #else /* CONFIG_SUN50I_GEN_H6 */
  499. setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
  500. /* unassert reset */
  501. setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
  502. #endif
  503. ret = mmc_set_mod_clk(priv, 24000000);
  504. if (ret)
  505. return NULL;
  506. return mmc_create(cfg, priv);
  507. }
  508. #else
  509. static int sunxi_mmc_set_ios(struct udevice *dev)
  510. {
  511. struct sunxi_mmc_plat *plat = dev_get_plat(dev);
  512. struct sunxi_mmc_priv *priv = dev_get_priv(dev);
  513. return sunxi_mmc_set_ios_common(priv, &plat->mmc);
  514. }
  515. static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  516. struct mmc_data *data)
  517. {
  518. struct sunxi_mmc_plat *plat = dev_get_plat(dev);
  519. struct sunxi_mmc_priv *priv = dev_get_priv(dev);
  520. return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
  521. }
  522. static int sunxi_mmc_getcd(struct udevice *dev)
  523. {
  524. struct mmc *mmc = mmc_get_mmc_dev(dev);
  525. struct sunxi_mmc_priv *priv = dev_get_priv(dev);
  526. /* If polling, assume that the card is always present. */
  527. if ((mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE) ||
  528. (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL))
  529. return 1;
  530. if (dm_gpio_is_valid(&priv->cd_gpio)) {
  531. int cd_state = dm_gpio_get_value(&priv->cd_gpio);
  532. if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
  533. return !cd_state;
  534. else
  535. return cd_state;
  536. }
  537. return 1;
  538. }
  539. static const struct dm_mmc_ops sunxi_mmc_ops = {
  540. .send_cmd = sunxi_mmc_send_cmd,
  541. .set_ios = sunxi_mmc_set_ios,
  542. .get_cd = sunxi_mmc_getcd,
  543. };
  544. static unsigned get_mclk_offset(void)
  545. {
  546. if (IS_ENABLED(CONFIG_MACH_SUN9I_A80))
  547. return 0x410;
  548. if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
  549. return 0x830;
  550. return 0x88;
  551. };
  552. static int sunxi_mmc_probe(struct udevice *dev)
  553. {
  554. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  555. struct sunxi_mmc_plat *plat = dev_get_plat(dev);
  556. struct sunxi_mmc_priv *priv = dev_get_priv(dev);
  557. struct reset_ctl_bulk reset_bulk;
  558. struct clk gate_clk;
  559. struct mmc_config *cfg = &plat->cfg;
  560. struct ofnode_phandle_args args;
  561. u32 *ccu_reg;
  562. int ret;
  563. cfg->name = dev->name;
  564. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  565. cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
  566. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  567. cfg->f_min = 400000;
  568. cfg->f_max = 52000000;
  569. ret = mmc_of_parse(dev, cfg);
  570. if (ret)
  571. return ret;
  572. priv->reg = dev_read_addr_ptr(dev);
  573. /* We don't have a sunxi clock driver so find the clock address here */
  574. ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
  575. 1, &args);
  576. if (ret)
  577. return ret;
  578. ccu_reg = (u32 *)(uintptr_t)ofnode_get_addr(args.node);
  579. priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
  580. priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4;
  581. ret = clk_get_by_name(dev, "ahb", &gate_clk);
  582. if (!ret)
  583. clk_enable(&gate_clk);
  584. ret = reset_get_bulk(dev, &reset_bulk);
  585. if (!ret)
  586. reset_deassert_bulk(&reset_bulk);
  587. ret = mmc_set_mod_clk(priv, 24000000);
  588. if (ret)
  589. return ret;
  590. /* This GPIO is optional */
  591. if (!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
  592. GPIOD_IS_IN)) {
  593. int cd_pin = gpio_get_number(&priv->cd_gpio);
  594. sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
  595. }
  596. upriv->mmc = &plat->mmc;
  597. /* Reset controller */
  598. writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
  599. udelay(1000);
  600. return 0;
  601. }
  602. static int sunxi_mmc_bind(struct udevice *dev)
  603. {
  604. struct sunxi_mmc_plat *plat = dev_get_plat(dev);
  605. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  606. }
  607. static const struct udevice_id sunxi_mmc_ids[] = {
  608. { .compatible = "allwinner,sun4i-a10-mmc" },
  609. { .compatible = "allwinner,sun5i-a13-mmc" },
  610. { .compatible = "allwinner,sun7i-a20-mmc" },
  611. { .compatible = "allwinner,sun8i-a83t-emmc" },
  612. { .compatible = "allwinner,sun9i-a80-mmc" },
  613. { .compatible = "allwinner,sun50i-a64-mmc" },
  614. { .compatible = "allwinner,sun50i-a64-emmc" },
  615. { .compatible = "allwinner,sun50i-h6-mmc" },
  616. { .compatible = "allwinner,sun50i-h6-emmc" },
  617. { .compatible = "allwinner,sun50i-a100-mmc" },
  618. { .compatible = "allwinner,sun50i-a100-emmc" },
  619. { /* sentinel */ }
  620. };
  621. U_BOOT_DRIVER(sunxi_mmc_drv) = {
  622. .name = "sunxi_mmc",
  623. .id = UCLASS_MMC,
  624. .of_match = sunxi_mmc_ids,
  625. .bind = sunxi_mmc_bind,
  626. .probe = sunxi_mmc_probe,
  627. .ops = &sunxi_mmc_ops,
  628. .plat_auto = sizeof(struct sunxi_mmc_plat),
  629. .priv_auto = sizeof(struct sunxi_mmc_priv),
  630. };
  631. #endif