stm32_sdmmc2.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  4. * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
  5. */
  6. #define LOG_CATEGORY UCLASS_MMC
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <cpu_func.h>
  10. #include <dm.h>
  11. #include <fdtdec.h>
  12. #include <log.h>
  13. #include <malloc.h>
  14. #include <asm/bitops.h>
  15. #include <asm/cache.h>
  16. #include <dm/device_compat.h>
  17. #include <linux/bitops.h>
  18. #include <linux/delay.h>
  19. #include <linux/libfdt.h>
  20. #include <mmc.h>
  21. #include <reset.h>
  22. #include <asm/io.h>
  23. #include <asm/gpio.h>
  24. #include <linux/iopoll.h>
  25. #include <watchdog.h>
  26. struct stm32_sdmmc2_plat {
  27. struct mmc_config cfg;
  28. struct mmc mmc;
  29. };
  30. struct stm32_sdmmc2_priv {
  31. fdt_addr_t base;
  32. struct clk clk;
  33. struct reset_ctl reset_ctl;
  34. struct gpio_desc cd_gpio;
  35. u32 clk_reg_msk;
  36. u32 pwr_reg_msk;
  37. };
  38. struct stm32_sdmmc2_ctx {
  39. u32 cache_start;
  40. u32 cache_end;
  41. u32 data_length;
  42. bool dpsm_abort;
  43. };
  44. /* SDMMC REGISTERS OFFSET */
  45. #define SDMMC_POWER 0x00 /* SDMMC power control */
  46. #define SDMMC_CLKCR 0x04 /* SDMMC clock control */
  47. #define SDMMC_ARG 0x08 /* SDMMC argument */
  48. #define SDMMC_CMD 0x0C /* SDMMC command */
  49. #define SDMMC_RESP1 0x14 /* SDMMC response 1 */
  50. #define SDMMC_RESP2 0x18 /* SDMMC response 2 */
  51. #define SDMMC_RESP3 0x1C /* SDMMC response 3 */
  52. #define SDMMC_RESP4 0x20 /* SDMMC response 4 */
  53. #define SDMMC_DTIMER 0x24 /* SDMMC data timer */
  54. #define SDMMC_DLEN 0x28 /* SDMMC data length */
  55. #define SDMMC_DCTRL 0x2C /* SDMMC data control */
  56. #define SDMMC_DCOUNT 0x30 /* SDMMC data counter */
  57. #define SDMMC_STA 0x34 /* SDMMC status */
  58. #define SDMMC_ICR 0x38 /* SDMMC interrupt clear */
  59. #define SDMMC_MASK 0x3C /* SDMMC mask */
  60. #define SDMMC_IDMACTRL 0x50 /* SDMMC DMA control */
  61. #define SDMMC_IDMABASE0 0x58 /* SDMMC DMA buffer 0 base address */
  62. /* SDMMC_POWER register */
  63. #define SDMMC_POWER_PWRCTRL_MASK GENMASK(1, 0)
  64. #define SDMMC_POWER_PWRCTRL_OFF 0
  65. #define SDMMC_POWER_PWRCTRL_CYCLE 2
  66. #define SDMMC_POWER_PWRCTRL_ON 3
  67. #define SDMMC_POWER_VSWITCH BIT(2)
  68. #define SDMMC_POWER_VSWITCHEN BIT(3)
  69. #define SDMMC_POWER_DIRPOL BIT(4)
  70. /* SDMMC_CLKCR register */
  71. #define SDMMC_CLKCR_CLKDIV GENMASK(9, 0)
  72. #define SDMMC_CLKCR_CLKDIV_MAX SDMMC_CLKCR_CLKDIV
  73. #define SDMMC_CLKCR_PWRSAV BIT(12)
  74. #define SDMMC_CLKCR_WIDBUS_4 BIT(14)
  75. #define SDMMC_CLKCR_WIDBUS_8 BIT(15)
  76. #define SDMMC_CLKCR_NEGEDGE BIT(16)
  77. #define SDMMC_CLKCR_HWFC_EN BIT(17)
  78. #define SDMMC_CLKCR_DDR BIT(18)
  79. #define SDMMC_CLKCR_BUSSPEED BIT(19)
  80. #define SDMMC_CLKCR_SELCLKRX_MASK GENMASK(21, 20)
  81. #define SDMMC_CLKCR_SELCLKRX_CK 0
  82. #define SDMMC_CLKCR_SELCLKRX_CKIN BIT(20)
  83. #define SDMMC_CLKCR_SELCLKRX_FBCK BIT(21)
  84. /* SDMMC_CMD register */
  85. #define SDMMC_CMD_CMDINDEX GENMASK(5, 0)
  86. #define SDMMC_CMD_CMDTRANS BIT(6)
  87. #define SDMMC_CMD_CMDSTOP BIT(7)
  88. #define SDMMC_CMD_WAITRESP GENMASK(9, 8)
  89. #define SDMMC_CMD_WAITRESP_0 BIT(8)
  90. #define SDMMC_CMD_WAITRESP_1 BIT(9)
  91. #define SDMMC_CMD_WAITINT BIT(10)
  92. #define SDMMC_CMD_WAITPEND BIT(11)
  93. #define SDMMC_CMD_CPSMEN BIT(12)
  94. #define SDMMC_CMD_DTHOLD BIT(13)
  95. #define SDMMC_CMD_BOOTMODE BIT(14)
  96. #define SDMMC_CMD_BOOTEN BIT(15)
  97. #define SDMMC_CMD_CMDSUSPEND BIT(16)
  98. /* SDMMC_DCTRL register */
  99. #define SDMMC_DCTRL_DTEN BIT(0)
  100. #define SDMMC_DCTRL_DTDIR BIT(1)
  101. #define SDMMC_DCTRL_DTMODE GENMASK(3, 2)
  102. #define SDMMC_DCTRL_DBLOCKSIZE GENMASK(7, 4)
  103. #define SDMMC_DCTRL_DBLOCKSIZE_SHIFT 4
  104. #define SDMMC_DCTRL_RWSTART BIT(8)
  105. #define SDMMC_DCTRL_RWSTOP BIT(9)
  106. #define SDMMC_DCTRL_RWMOD BIT(10)
  107. #define SDMMC_DCTRL_SDMMCEN BIT(11)
  108. #define SDMMC_DCTRL_BOOTACKEN BIT(12)
  109. #define SDMMC_DCTRL_FIFORST BIT(13)
  110. /* SDMMC_STA register */
  111. #define SDMMC_STA_CCRCFAIL BIT(0)
  112. #define SDMMC_STA_DCRCFAIL BIT(1)
  113. #define SDMMC_STA_CTIMEOUT BIT(2)
  114. #define SDMMC_STA_DTIMEOUT BIT(3)
  115. #define SDMMC_STA_TXUNDERR BIT(4)
  116. #define SDMMC_STA_RXOVERR BIT(5)
  117. #define SDMMC_STA_CMDREND BIT(6)
  118. #define SDMMC_STA_CMDSENT BIT(7)
  119. #define SDMMC_STA_DATAEND BIT(8)
  120. #define SDMMC_STA_DHOLD BIT(9)
  121. #define SDMMC_STA_DBCKEND BIT(10)
  122. #define SDMMC_STA_DABORT BIT(11)
  123. #define SDMMC_STA_DPSMACT BIT(12)
  124. #define SDMMC_STA_CPSMACT BIT(13)
  125. #define SDMMC_STA_TXFIFOHE BIT(14)
  126. #define SDMMC_STA_RXFIFOHF BIT(15)
  127. #define SDMMC_STA_TXFIFOF BIT(16)
  128. #define SDMMC_STA_RXFIFOF BIT(17)
  129. #define SDMMC_STA_TXFIFOE BIT(18)
  130. #define SDMMC_STA_RXFIFOE BIT(19)
  131. #define SDMMC_STA_BUSYD0 BIT(20)
  132. #define SDMMC_STA_BUSYD0END BIT(21)
  133. #define SDMMC_STA_SDMMCIT BIT(22)
  134. #define SDMMC_STA_ACKFAIL BIT(23)
  135. #define SDMMC_STA_ACKTIMEOUT BIT(24)
  136. #define SDMMC_STA_VSWEND BIT(25)
  137. #define SDMMC_STA_CKSTOP BIT(26)
  138. #define SDMMC_STA_IDMATE BIT(27)
  139. #define SDMMC_STA_IDMABTC BIT(28)
  140. /* SDMMC_ICR register */
  141. #define SDMMC_ICR_CCRCFAILC BIT(0)
  142. #define SDMMC_ICR_DCRCFAILC BIT(1)
  143. #define SDMMC_ICR_CTIMEOUTC BIT(2)
  144. #define SDMMC_ICR_DTIMEOUTC BIT(3)
  145. #define SDMMC_ICR_TXUNDERRC BIT(4)
  146. #define SDMMC_ICR_RXOVERRC BIT(5)
  147. #define SDMMC_ICR_CMDRENDC BIT(6)
  148. #define SDMMC_ICR_CMDSENTC BIT(7)
  149. #define SDMMC_ICR_DATAENDC BIT(8)
  150. #define SDMMC_ICR_DHOLDC BIT(9)
  151. #define SDMMC_ICR_DBCKENDC BIT(10)
  152. #define SDMMC_ICR_DABORTC BIT(11)
  153. #define SDMMC_ICR_BUSYD0ENDC BIT(21)
  154. #define SDMMC_ICR_SDMMCITC BIT(22)
  155. #define SDMMC_ICR_ACKFAILC BIT(23)
  156. #define SDMMC_ICR_ACKTIMEOUTC BIT(24)
  157. #define SDMMC_ICR_VSWENDC BIT(25)
  158. #define SDMMC_ICR_CKSTOPC BIT(26)
  159. #define SDMMC_ICR_IDMATEC BIT(27)
  160. #define SDMMC_ICR_IDMABTCC BIT(28)
  161. #define SDMMC_ICR_STATIC_FLAGS ((GENMASK(28, 21)) | (GENMASK(11, 0)))
  162. /* SDMMC_MASK register */
  163. #define SDMMC_MASK_CCRCFAILIE BIT(0)
  164. #define SDMMC_MASK_DCRCFAILIE BIT(1)
  165. #define SDMMC_MASK_CTIMEOUTIE BIT(2)
  166. #define SDMMC_MASK_DTIMEOUTIE BIT(3)
  167. #define SDMMC_MASK_TXUNDERRIE BIT(4)
  168. #define SDMMC_MASK_RXOVERRIE BIT(5)
  169. #define SDMMC_MASK_CMDRENDIE BIT(6)
  170. #define SDMMC_MASK_CMDSENTIE BIT(7)
  171. #define SDMMC_MASK_DATAENDIE BIT(8)
  172. #define SDMMC_MASK_DHOLDIE BIT(9)
  173. #define SDMMC_MASK_DBCKENDIE BIT(10)
  174. #define SDMMC_MASK_DABORTIE BIT(11)
  175. #define SDMMC_MASK_TXFIFOHEIE BIT(14)
  176. #define SDMMC_MASK_RXFIFOHFIE BIT(15)
  177. #define SDMMC_MASK_RXFIFOFIE BIT(17)
  178. #define SDMMC_MASK_TXFIFOEIE BIT(18)
  179. #define SDMMC_MASK_BUSYD0ENDIE BIT(21)
  180. #define SDMMC_MASK_SDMMCITIE BIT(22)
  181. #define SDMMC_MASK_ACKFAILIE BIT(23)
  182. #define SDMMC_MASK_ACKTIMEOUTIE BIT(24)
  183. #define SDMMC_MASK_VSWENDIE BIT(25)
  184. #define SDMMC_MASK_CKSTOPIE BIT(26)
  185. #define SDMMC_MASK_IDMABTCIE BIT(28)
  186. /* SDMMC_IDMACTRL register */
  187. #define SDMMC_IDMACTRL_IDMAEN BIT(0)
  188. #define SDMMC_CMD_TIMEOUT 0xFFFFFFFF
  189. #define SDMMC_BUSYD0END_TIMEOUT_US 2000000
  190. static void stm32_sdmmc2_start_data(struct udevice *dev,
  191. struct mmc_data *data,
  192. struct stm32_sdmmc2_ctx *ctx)
  193. {
  194. struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
  195. u32 data_ctrl, idmabase0;
  196. /* Configure the SDMMC DPSM (Data Path State Machine) */
  197. data_ctrl = (__ilog2(data->blocksize) <<
  198. SDMMC_DCTRL_DBLOCKSIZE_SHIFT) &
  199. SDMMC_DCTRL_DBLOCKSIZE;
  200. if (data->flags & MMC_DATA_READ) {
  201. data_ctrl |= SDMMC_DCTRL_DTDIR;
  202. idmabase0 = (u32)data->dest;
  203. } else {
  204. idmabase0 = (u32)data->src;
  205. }
  206. /* Set the SDMMC DataLength value */
  207. writel(ctx->data_length, priv->base + SDMMC_DLEN);
  208. /* Write to SDMMC DCTRL */
  209. writel(data_ctrl, priv->base + SDMMC_DCTRL);
  210. /* Cache align */
  211. ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
  212. ctx->cache_end = roundup(idmabase0 + ctx->data_length,
  213. ARCH_DMA_MINALIGN);
  214. /*
  215. * Flush data cache before DMA start (clean and invalidate)
  216. * Clean also needed for read
  217. * Avoid issue on buffer not cached-aligned
  218. */
  219. flush_dcache_range(ctx->cache_start, ctx->cache_end);
  220. /* Enable internal DMA */
  221. writel(idmabase0, priv->base + SDMMC_IDMABASE0);
  222. writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
  223. }
  224. static void stm32_sdmmc2_start_cmd(struct udevice *dev,
  225. struct mmc_cmd *cmd, u32 cmd_param,
  226. struct stm32_sdmmc2_ctx *ctx)
  227. {
  228. struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
  229. u32 timeout = 0;
  230. if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
  231. writel(0, priv->base + SDMMC_CMD);
  232. cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
  233. if (cmd->resp_type & MMC_RSP_PRESENT) {
  234. if (cmd->resp_type & MMC_RSP_136)
  235. cmd_param |= SDMMC_CMD_WAITRESP;
  236. else if (cmd->resp_type & MMC_RSP_CRC)
  237. cmd_param |= SDMMC_CMD_WAITRESP_0;
  238. else
  239. cmd_param |= SDMMC_CMD_WAITRESP_1;
  240. }
  241. /*
  242. * SDMMC_DTIME must be set in two case:
  243. * - on data transfert.
  244. * - on busy request.
  245. * If not done or too short, the dtimeout flag occurs and DPSM stays
  246. * enabled/busy and waits for abort (stop transmission cmd).
  247. * Next data command is not possible whereas DPSM is activated.
  248. */
  249. if (ctx->data_length) {
  250. timeout = SDMMC_CMD_TIMEOUT;
  251. } else {
  252. writel(0, priv->base + SDMMC_DCTRL);
  253. if (cmd->resp_type & MMC_RSP_BUSY)
  254. timeout = SDMMC_CMD_TIMEOUT;
  255. }
  256. /* Set the SDMMC Data TimeOut value */
  257. writel(timeout, priv->base + SDMMC_DTIMER);
  258. /* Clear flags */
  259. writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
  260. /* Set SDMMC argument value */
  261. writel(cmd->cmdarg, priv->base + SDMMC_ARG);
  262. /* Set SDMMC command parameters */
  263. writel(cmd_param, priv->base + SDMMC_CMD);
  264. }
  265. static int stm32_sdmmc2_end_cmd(struct udevice *dev,
  266. struct mmc_cmd *cmd,
  267. struct stm32_sdmmc2_ctx *ctx)
  268. {
  269. struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
  270. u32 mask = SDMMC_STA_CTIMEOUT;
  271. u32 status;
  272. int ret;
  273. if (cmd->resp_type & MMC_RSP_PRESENT) {
  274. mask |= SDMMC_STA_CMDREND;
  275. if (cmd->resp_type & MMC_RSP_CRC)
  276. mask |= SDMMC_STA_CCRCFAIL;
  277. } else {
  278. mask |= SDMMC_STA_CMDSENT;
  279. }
  280. /* Polling status register */
  281. ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask,
  282. 10000);
  283. if (ret < 0) {
  284. dev_dbg(dev, "timeout reading SDMMC_STA register\n");
  285. ctx->dpsm_abort = true;
  286. return ret;
  287. }
  288. /* Check status */
  289. if (status & SDMMC_STA_CTIMEOUT) {
  290. dev_dbg(dev, "error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
  291. status, cmd->cmdidx);
  292. ctx->dpsm_abort = true;
  293. return -ETIMEDOUT;
  294. }
  295. if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
  296. dev_dbg(dev, "error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
  297. status, cmd->cmdidx);
  298. ctx->dpsm_abort = true;
  299. return -EILSEQ;
  300. }
  301. if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
  302. cmd->response[0] = readl(priv->base + SDMMC_RESP1);
  303. if (cmd->resp_type & MMC_RSP_136) {
  304. cmd->response[1] = readl(priv->base + SDMMC_RESP2);
  305. cmd->response[2] = readl(priv->base + SDMMC_RESP3);
  306. cmd->response[3] = readl(priv->base + SDMMC_RESP4);
  307. }
  308. /* Wait for BUSYD0END flag if busy status is detected */
  309. if (cmd->resp_type & MMC_RSP_BUSY &&
  310. status & SDMMC_STA_BUSYD0) {
  311. mask = SDMMC_STA_DTIMEOUT | SDMMC_STA_BUSYD0END;
  312. /* Polling status register */
  313. ret = readl_poll_timeout(priv->base + SDMMC_STA,
  314. status, status & mask,
  315. SDMMC_BUSYD0END_TIMEOUT_US);
  316. if (ret < 0) {
  317. dev_dbg(dev, "timeout reading SDMMC_STA\n");
  318. ctx->dpsm_abort = true;
  319. return ret;
  320. }
  321. if (status & SDMMC_STA_DTIMEOUT) {
  322. dev_dbg(dev,
  323. "error SDMMC_STA_DTIMEOUT (0x%x)\n",
  324. status);
  325. ctx->dpsm_abort = true;
  326. return -ETIMEDOUT;
  327. }
  328. }
  329. }
  330. return 0;
  331. }
  332. static int stm32_sdmmc2_end_data(struct udevice *dev,
  333. struct mmc_cmd *cmd,
  334. struct mmc_data *data,
  335. struct stm32_sdmmc2_ctx *ctx)
  336. {
  337. struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
  338. u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
  339. SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
  340. u32 status;
  341. if (data->flags & MMC_DATA_READ)
  342. mask |= SDMMC_STA_RXOVERR;
  343. else
  344. mask |= SDMMC_STA_TXUNDERR;
  345. status = readl(priv->base + SDMMC_STA);
  346. while (!(status & mask))
  347. status = readl(priv->base + SDMMC_STA);
  348. /*
  349. * Need invalidate the dcache again to avoid any
  350. * cache-refill during the DMA operations (pre-fetching)
  351. */
  352. if (data->flags & MMC_DATA_READ)
  353. invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
  354. if (status & SDMMC_STA_DCRCFAIL) {
  355. dev_dbg(dev, "error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
  356. status, cmd->cmdidx);
  357. if (readl(priv->base + SDMMC_DCOUNT))
  358. ctx->dpsm_abort = true;
  359. return -EILSEQ;
  360. }
  361. if (status & SDMMC_STA_DTIMEOUT) {
  362. dev_dbg(dev, "error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
  363. status, cmd->cmdidx);
  364. ctx->dpsm_abort = true;
  365. return -ETIMEDOUT;
  366. }
  367. if (status & SDMMC_STA_TXUNDERR) {
  368. dev_dbg(dev, "error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
  369. status, cmd->cmdidx);
  370. ctx->dpsm_abort = true;
  371. return -EIO;
  372. }
  373. if (status & SDMMC_STA_RXOVERR) {
  374. dev_dbg(dev, "error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
  375. status, cmd->cmdidx);
  376. ctx->dpsm_abort = true;
  377. return -EIO;
  378. }
  379. if (status & SDMMC_STA_IDMATE) {
  380. dev_dbg(dev, "error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
  381. status, cmd->cmdidx);
  382. ctx->dpsm_abort = true;
  383. return -EIO;
  384. }
  385. return 0;
  386. }
  387. static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  388. struct mmc_data *data)
  389. {
  390. struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
  391. struct stm32_sdmmc2_ctx ctx;
  392. u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
  393. int ret, retry = 3;
  394. WATCHDOG_RESET();
  395. retry_cmd:
  396. ctx.data_length = 0;
  397. ctx.dpsm_abort = false;
  398. if (data) {
  399. ctx.data_length = data->blocks * data->blocksize;
  400. stm32_sdmmc2_start_data(dev, data, &ctx);
  401. }
  402. stm32_sdmmc2_start_cmd(dev, cmd, cmdat, &ctx);
  403. dev_dbg(dev, "send cmd %d data: 0x%x @ 0x%x\n",
  404. cmd->cmdidx, data ? ctx.data_length : 0, (unsigned int)data);
  405. ret = stm32_sdmmc2_end_cmd(dev, cmd, &ctx);
  406. if (data && !ret)
  407. ret = stm32_sdmmc2_end_data(dev, cmd, data, &ctx);
  408. /* Clear flags */
  409. writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
  410. if (data)
  411. writel(0x0, priv->base + SDMMC_IDMACTRL);
  412. /*
  413. * To stop Data Path State Machine, a stop_transmission command
  414. * shall be send on cmd or data errors.
  415. */
  416. if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
  417. struct mmc_cmd stop_cmd;
  418. stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
  419. stop_cmd.cmdarg = 0;
  420. stop_cmd.resp_type = MMC_RSP_R1b;
  421. dev_dbg(dev, "send STOP command to abort dpsm treatments\n");
  422. ctx.data_length = 0;
  423. stm32_sdmmc2_start_cmd(dev, &stop_cmd,
  424. SDMMC_CMD_CMDSTOP, &ctx);
  425. stm32_sdmmc2_end_cmd(dev, &stop_cmd, &ctx);
  426. writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
  427. }
  428. if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
  429. dev_err(dev, "cmd %d failed, retrying ...\n", cmd->cmdidx);
  430. retry--;
  431. goto retry_cmd;
  432. }
  433. dev_dbg(dev, "end for CMD %d, ret = %d\n", cmd->cmdidx, ret);
  434. return ret;
  435. }
  436. /*
  437. * Reset the SDMMC with the RCC.SDMMCxRST register bit.
  438. * This will reset the SDMMC to the reset state and the CPSM and DPSM
  439. * to the Idle state. SDMMC is disabled, Signals Hiz.
  440. */
  441. static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
  442. {
  443. /* Reset */
  444. reset_assert(&priv->reset_ctl);
  445. udelay(2);
  446. reset_deassert(&priv->reset_ctl);
  447. /* init the needed SDMMC register after reset */
  448. writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
  449. }
  450. /*
  451. * Set the SDMMC in power-cycle state.
  452. * This will make that the SDMMC_D[7:0],
  453. * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being
  454. * supplied through the signal lines.
  455. */
  456. static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv)
  457. {
  458. if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) ==
  459. SDMMC_POWER_PWRCTRL_CYCLE)
  460. return;
  461. stm32_sdmmc2_reset(priv);
  462. }
  463. /*
  464. * set the SDMMC state Power-on: the card is clocked
  465. * manage the SDMMC state control:
  466. * Reset => Power-Cycle => Power-Off => Power
  467. * PWRCTRL=10 PWCTRL=00 PWCTRL=11
  468. */
  469. static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
  470. {
  471. u32 pwrctrl =
  472. readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK;
  473. if (pwrctrl == SDMMC_POWER_PWRCTRL_ON)
  474. return;
  475. /* warning: same PWRCTRL value after reset and for power-off state
  476. * it is the reset state here = the only managed by the driver
  477. */
  478. if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) {
  479. writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
  480. priv->base + SDMMC_POWER);
  481. }
  482. /*
  483. * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE
  484. * switch to Power-Off state: SDMCC disable, signals drive 1
  485. */
  486. writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk,
  487. priv->base + SDMMC_POWER);
  488. /* After the 1ms delay set the SDMMC to power-on */
  489. mdelay(1);
  490. writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk,
  491. priv->base + SDMMC_POWER);
  492. /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */
  493. }
  494. #define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
  495. static int stm32_sdmmc2_set_ios(struct udevice *dev)
  496. {
  497. struct mmc *mmc = mmc_get_mmc_dev(dev);
  498. struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
  499. u32 desired = mmc->clock;
  500. u32 sys_clock = clk_get_rate(&priv->clk);
  501. u32 clk = 0;
  502. dev_dbg(dev, "bus_with = %d, clock = %d\n",
  503. mmc->bus_width, mmc->clock);
  504. if (mmc->clk_disable)
  505. stm32_sdmmc2_pwrcycle(priv);
  506. else
  507. stm32_sdmmc2_pwron(priv);
  508. /*
  509. * clk_div = 0 => command and data generated on SDMMCCLK falling edge
  510. * clk_div > 0 and NEGEDGE = 0 => command and data generated on
  511. * SDMMCCLK rising edge
  512. * clk_div > 0 and NEGEDGE = 1 => command and data generated on
  513. * SDMMCCLK falling edge
  514. */
  515. if (desired && ((sys_clock > desired) ||
  516. IS_RISING_EDGE(priv->clk_reg_msk))) {
  517. clk = DIV_ROUND_UP(sys_clock, 2 * desired);
  518. if (clk > SDMMC_CLKCR_CLKDIV_MAX)
  519. clk = SDMMC_CLKCR_CLKDIV_MAX;
  520. }
  521. if (mmc->bus_width == 4)
  522. clk |= SDMMC_CLKCR_WIDBUS_4;
  523. if (mmc->bus_width == 8)
  524. clk |= SDMMC_CLKCR_WIDBUS_8;
  525. writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
  526. priv->base + SDMMC_CLKCR);
  527. return 0;
  528. }
  529. static int stm32_sdmmc2_getcd(struct udevice *dev)
  530. {
  531. struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
  532. dev_dbg(dev, "%s called\n", __func__);
  533. if (dm_gpio_is_valid(&priv->cd_gpio))
  534. return dm_gpio_get_value(&priv->cd_gpio);
  535. return 1;
  536. }
  537. static int stm32_sdmmc2_host_power_cycle(struct udevice *dev)
  538. {
  539. struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
  540. writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
  541. priv->base + SDMMC_POWER);
  542. return 0;
  543. }
  544. static const struct dm_mmc_ops stm32_sdmmc2_ops = {
  545. .send_cmd = stm32_sdmmc2_send_cmd,
  546. .set_ios = stm32_sdmmc2_set_ios,
  547. .get_cd = stm32_sdmmc2_getcd,
  548. .host_power_cycle = stm32_sdmmc2_host_power_cycle,
  549. };
  550. static int stm32_sdmmc2_probe(struct udevice *dev)
  551. {
  552. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  553. struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
  554. struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
  555. struct mmc_config *cfg = &plat->cfg;
  556. int ret;
  557. priv->base = dev_read_addr(dev);
  558. if (priv->base == FDT_ADDR_T_NONE)
  559. return -EINVAL;
  560. if (dev_read_bool(dev, "st,neg-edge"))
  561. priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
  562. if (dev_read_bool(dev, "st,sig-dir"))
  563. priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
  564. if (dev_read_bool(dev, "st,use-ckin"))
  565. priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
  566. ret = clk_get_by_index(dev, 0, &priv->clk);
  567. if (ret)
  568. return ret;
  569. ret = clk_enable(&priv->clk);
  570. if (ret)
  571. goto clk_free;
  572. ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
  573. if (ret)
  574. goto clk_disable;
  575. gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
  576. GPIOD_IS_IN);
  577. cfg->f_min = 400000;
  578. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  579. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  580. cfg->name = "STM32 SD/MMC";
  581. cfg->host_caps = 0;
  582. cfg->f_max = 52000000;
  583. mmc_of_parse(dev, cfg);
  584. upriv->mmc = &plat->mmc;
  585. /* SDMMC init */
  586. stm32_sdmmc2_reset(priv);
  587. return 0;
  588. clk_disable:
  589. clk_disable(&priv->clk);
  590. clk_free:
  591. clk_free(&priv->clk);
  592. return ret;
  593. }
  594. static int stm32_sdmmc_bind(struct udevice *dev)
  595. {
  596. struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
  597. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  598. }
  599. static const struct udevice_id stm32_sdmmc2_ids[] = {
  600. { .compatible = "st,stm32-sdmmc2" },
  601. { }
  602. };
  603. U_BOOT_DRIVER(stm32_sdmmc2) = {
  604. .name = "stm32_sdmmc2",
  605. .id = UCLASS_MMC,
  606. .of_match = stm32_sdmmc2_ids,
  607. .ops = &stm32_sdmmc2_ops,
  608. .probe = stm32_sdmmc2_probe,
  609. .bind = stm32_sdmmc_bind,
  610. .priv_auto = sizeof(struct stm32_sdmmc2_priv),
  611. .plat_auto = sizeof(struct stm32_sdmmc2_plat),
  612. };