socfpga_dw_mmc.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Altera Corporation <www.altera.com>
  4. */
  5. #include <common.h>
  6. #include <log.h>
  7. #include <asm/arch/clock_manager.h>
  8. #include <asm/arch/secure_reg_helper.h>
  9. #include <asm/arch/system_manager.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <dwmmc.h>
  13. #include <errno.h>
  14. #include <fdtdec.h>
  15. #include <asm/global_data.h>
  16. #include <dm/device_compat.h>
  17. #include <linux/intel-smc.h>
  18. #include <linux/libfdt.h>
  19. #include <linux/err.h>
  20. #include <malloc.h>
  21. #include <reset.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. struct socfpga_dwmci_plat {
  24. struct mmc_config cfg;
  25. struct mmc mmc;
  26. };
  27. /* socfpga implmentation specific driver private data */
  28. struct dwmci_socfpga_priv_data {
  29. struct dwmci_host host;
  30. unsigned int drvsel;
  31. unsigned int smplsel;
  32. };
  33. static void socfpga_dwmci_reset(struct udevice *dev)
  34. {
  35. struct reset_ctl_bulk reset_bulk;
  36. int ret;
  37. ret = reset_get_bulk(dev, &reset_bulk);
  38. if (ret) {
  39. dev_warn(dev, "Can't get reset: %d\n", ret);
  40. return;
  41. }
  42. reset_deassert_bulk(&reset_bulk);
  43. }
  44. static int socfpga_dwmci_clksel(struct dwmci_host *host)
  45. {
  46. struct dwmci_socfpga_priv_data *priv = host->priv;
  47. u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
  48. ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
  49. /* Disable SDMMC clock. */
  50. clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
  51. CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  52. debug("%s: drvsel %d smplsel %d\n", __func__,
  53. priv->drvsel, priv->smplsel);
  54. #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
  55. int ret;
  56. ret = socfpga_secure_reg_write32(SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC,
  57. sdmmc_mask);
  58. if (ret) {
  59. printf("DWMMC: Failed to set clksel via SMC call");
  60. return ret;
  61. }
  62. #else
  63. writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
  64. debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
  65. readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
  66. #endif
  67. /* Enable SDMMC clock */
  68. setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
  69. CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  70. return 0;
  71. }
  72. static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
  73. {
  74. struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
  75. struct dwmci_host *host = &priv->host;
  76. #if CONFIG_IS_ENABLED(CLK)
  77. struct clk clk;
  78. int ret;
  79. ret = clk_get_by_index(dev, 1, &clk);
  80. if (ret)
  81. return ret;
  82. host->bus_hz = clk_get_rate(&clk);
  83. clk_free(&clk);
  84. #else
  85. /* Fixed clock divide by 4 which due to the SDMMC wrapper */
  86. host->bus_hz = cm_get_mmc_controller_clk_hz();
  87. #endif
  88. if (host->bus_hz == 0) {
  89. printf("DWMMC: MMC clock is zero!");
  90. return -EINVAL;
  91. }
  92. return 0;
  93. }
  94. static int socfpga_dwmmc_of_to_plat(struct udevice *dev)
  95. {
  96. struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
  97. struct dwmci_host *host = &priv->host;
  98. int fifo_depth;
  99. fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  100. "fifo-depth", 0);
  101. if (fifo_depth < 0) {
  102. printf("DWMMC: Can't get FIFO depth\n");
  103. return -EINVAL;
  104. }
  105. host->name = dev->name;
  106. host->ioaddr = dev_read_addr_ptr(dev);
  107. host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  108. "bus-width", 4);
  109. host->clksel = socfpga_dwmci_clksel;
  110. /*
  111. * TODO(sjg@chromium.org): Remove the need for this hack.
  112. * We only have one dwmmc block on gen5 SoCFPGA.
  113. */
  114. host->dev_index = 0;
  115. host->fifoth_val = MSIZE(0x2) |
  116. RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
  117. priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
  118. "drvsel", 3);
  119. priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
  120. "smplsel", 0);
  121. host->priv = priv;
  122. host->fifo_mode = dev_read_bool(dev, "fifo-mode");
  123. return 0;
  124. }
  125. static int socfpga_dwmmc_probe(struct udevice *dev)
  126. {
  127. #ifdef CONFIG_BLK
  128. struct socfpga_dwmci_plat *plat = dev_get_plat(dev);
  129. #endif
  130. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  131. struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
  132. struct dwmci_host *host = &priv->host;
  133. int ret;
  134. ret = socfpga_dwmmc_get_clk_rate(dev);
  135. if (ret)
  136. return ret;
  137. socfpga_dwmci_reset(dev);
  138. #ifdef CONFIG_BLK
  139. dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
  140. host->mmc = &plat->mmc;
  141. #else
  142. ret = add_dwmci(host, host->bus_hz, 400000);
  143. if (ret)
  144. return ret;
  145. #endif
  146. host->mmc->priv = &priv->host;
  147. upriv->mmc = host->mmc;
  148. host->mmc->dev = dev;
  149. return dwmci_probe(dev);
  150. }
  151. static int socfpga_dwmmc_bind(struct udevice *dev)
  152. {
  153. #ifdef CONFIG_BLK
  154. struct socfpga_dwmci_plat *plat = dev_get_plat(dev);
  155. int ret;
  156. ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
  157. if (ret)
  158. return ret;
  159. #endif
  160. return 0;
  161. }
  162. static const struct udevice_id socfpga_dwmmc_ids[] = {
  163. { .compatible = "altr,socfpga-dw-mshc" },
  164. { }
  165. };
  166. U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
  167. .name = "socfpga_dwmmc",
  168. .id = UCLASS_MMC,
  169. .of_match = socfpga_dwmmc_ids,
  170. .of_to_plat = socfpga_dwmmc_of_to_plat,
  171. .ops = &dm_dwmci_ops,
  172. .bind = socfpga_dwmmc_bind,
  173. .probe = socfpga_dwmmc_probe,
  174. .priv_auto = sizeof(struct dwmci_socfpga_priv_data),
  175. .plat_auto = sizeof(struct socfpga_dwmci_plat),
  176. };