s5p_sdhci.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012 SAMSUNG Electronics
  4. * Jaehoon Chung <jh80.chung@samsung.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <log.h>
  9. #include <malloc.h>
  10. #include <sdhci.h>
  11. #include <fdtdec.h>
  12. #include <asm/global_data.h>
  13. #include <linux/libfdt.h>
  14. #include <asm/gpio.h>
  15. #include <asm/arch/mmc.h>
  16. #include <asm/arch/clk.h>
  17. #include <errno.h>
  18. #include <asm/arch/pinmux.h>
  19. #ifdef CONFIG_DM_MMC
  20. struct s5p_sdhci_plat {
  21. struct mmc_config cfg;
  22. struct mmc mmc;
  23. };
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #endif
  26. static char *S5P_NAME = "SAMSUNG SDHCI";
  27. static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
  28. {
  29. unsigned long val, ctrl;
  30. /*
  31. * SELCLKPADDS[17:16]
  32. * 00 = 2mA
  33. * 01 = 4mA
  34. * 10 = 7mA
  35. * 11 = 9mA
  36. */
  37. sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4);
  38. val = sdhci_readl(host, SDHCI_CONTROL2);
  39. val &= SDHCI_CTRL2_SELBASECLK_MASK(3);
  40. val |= SDHCI_CTRL2_ENSTAASYNCCLR |
  41. SDHCI_CTRL2_ENCMDCNFMSK |
  42. SDHCI_CTRL2_ENFBCLKRX |
  43. SDHCI_CTRL2_ENCLKOUTHOLD;
  44. sdhci_writel(host, val, SDHCI_CONTROL2);
  45. /*
  46. * FCSEL3[31] FCSEL2[23] FCSEL1[15] FCSEL0[7]
  47. * FCSel[1:0] : Rx Feedback Clock Delay Control
  48. * Inverter delay means10ns delay if SDCLK 50MHz setting
  49. * 01 = Delay1 (basic delay)
  50. * 11 = Delay2 (basic delay + 2ns)
  51. * 00 = Delay3 (inverter delay)
  52. * 10 = Delay4 (inverter delay + 2ns)
  53. */
  54. val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1;
  55. sdhci_writel(host, val, SDHCI_CONTROL3);
  56. /*
  57. * SELBASECLK[5:4]
  58. * 00/01 = HCLK
  59. * 10 = EPLL
  60. * 11 = XTI or XEXTCLK
  61. */
  62. ctrl = sdhci_readl(host, SDHCI_CONTROL2);
  63. ctrl &= ~SDHCI_CTRL2_SELBASECLK_MASK(0x3);
  64. ctrl |= SDHCI_CTRL2_SELBASECLK_MASK(0x2);
  65. sdhci_writel(host, ctrl, SDHCI_CONTROL2);
  66. }
  67. static void s5p_set_clock(struct sdhci_host *host, u32 div)
  68. {
  69. /* ToDo : Use the Clock Framework */
  70. set_mmc_clk(host->index, div);
  71. }
  72. static const struct sdhci_ops s5p_sdhci_ops = {
  73. .set_clock = &s5p_set_clock,
  74. .set_control_reg = &s5p_sdhci_set_control_reg,
  75. };
  76. static int s5p_sdhci_core_init(struct sdhci_host *host)
  77. {
  78. host->name = S5P_NAME;
  79. host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
  80. SDHCI_QUIRK_32BIT_DMA_ADDR |
  81. SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
  82. host->max_clk = 52000000;
  83. host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  84. host->ops = &s5p_sdhci_ops;
  85. if (host->bus_width == 8)
  86. host->host_caps |= MMC_MODE_8BIT;
  87. #ifndef CONFIG_BLK
  88. return add_sdhci(host, 0, 400000);
  89. #else
  90. return 0;
  91. #endif
  92. }
  93. int s5p_sdhci_init(u32 regbase, int index, int bus_width)
  94. {
  95. struct sdhci_host *host = calloc(1, sizeof(struct sdhci_host));
  96. if (!host) {
  97. printf("sdhci__host allocation fail!\n");
  98. return -ENOMEM;
  99. }
  100. host->ioaddr = (void *)regbase;
  101. host->index = index;
  102. host->bus_width = bus_width;
  103. return s5p_sdhci_core_init(host);
  104. }
  105. static int do_sdhci_init(struct sdhci_host *host)
  106. {
  107. int dev_id, flag, ret;
  108. flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
  109. dev_id = host->index + PERIPH_ID_SDMMC0;
  110. ret = exynos_pinmux_config(dev_id, flag);
  111. if (ret) {
  112. printf("external SD not configured\n");
  113. return ret;
  114. }
  115. if (dm_gpio_is_valid(&host->pwr_gpio)) {
  116. dm_gpio_set_value(&host->pwr_gpio, 1);
  117. ret = exynos_pinmux_config(dev_id, flag);
  118. if (ret) {
  119. debug("MMC not configured\n");
  120. return ret;
  121. }
  122. }
  123. if (dm_gpio_is_valid(&host->cd_gpio)) {
  124. ret = dm_gpio_get_value(&host->cd_gpio);
  125. if (ret) {
  126. debug("no SD card detected (%d)\n", ret);
  127. return -ENODEV;
  128. }
  129. }
  130. return s5p_sdhci_core_init(host);
  131. }
  132. static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host)
  133. {
  134. int bus_width, dev_id;
  135. unsigned int base;
  136. /* Get device id */
  137. dev_id = pinmux_decode_periph_id(blob, node);
  138. if (dev_id < PERIPH_ID_SDMMC0 || dev_id > PERIPH_ID_SDMMC3) {
  139. debug("MMC: Can't get device id\n");
  140. return -EINVAL;
  141. }
  142. host->index = dev_id - PERIPH_ID_SDMMC0;
  143. /* Get bus width */
  144. bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
  145. if (bus_width <= 0) {
  146. debug("MMC: Can't get bus-width\n");
  147. return -EINVAL;
  148. }
  149. host->bus_width = bus_width;
  150. /* Get the base address from the device node */
  151. base = fdtdec_get_addr(blob, node, "reg");
  152. if (!base) {
  153. debug("MMC: Can't get base address\n");
  154. return -EINVAL;
  155. }
  156. host->ioaddr = (void *)base;
  157. gpio_request_by_name_nodev(offset_to_ofnode(node), "pwr-gpios", 0,
  158. &host->pwr_gpio, GPIOD_IS_OUT);
  159. gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios", 0,
  160. &host->cd_gpio, GPIOD_IS_IN);
  161. return 0;
  162. }
  163. #ifdef CONFIG_DM_MMC
  164. static int s5p_sdhci_probe(struct udevice *dev)
  165. {
  166. struct s5p_sdhci_plat *plat = dev_get_plat(dev);
  167. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  168. struct sdhci_host *host = dev_get_priv(dev);
  169. int ret;
  170. ret = sdhci_get_config(gd->fdt_blob, dev_of_offset(dev), host);
  171. if (ret)
  172. return ret;
  173. ret = do_sdhci_init(host);
  174. if (ret)
  175. return ret;
  176. ret = mmc_of_parse(dev, &plat->cfg);
  177. if (ret)
  178. return ret;
  179. host->mmc = &plat->mmc;
  180. host->mmc->dev = dev;
  181. ret = sdhci_setup_cfg(&plat->cfg, host, 0, 400000);
  182. if (ret)
  183. return ret;
  184. host->mmc->priv = host;
  185. upriv->mmc = host->mmc;
  186. return sdhci_probe(dev);
  187. }
  188. static int s5p_sdhci_bind(struct udevice *dev)
  189. {
  190. struct s5p_sdhci_plat *plat = dev_get_plat(dev);
  191. int ret;
  192. ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
  193. if (ret)
  194. return ret;
  195. return 0;
  196. }
  197. static const struct udevice_id s5p_sdhci_ids[] = {
  198. { .compatible = "samsung,exynos4412-sdhci"},
  199. { }
  200. };
  201. U_BOOT_DRIVER(s5p_sdhci_drv) = {
  202. .name = "s5p_sdhci",
  203. .id = UCLASS_MMC,
  204. .of_match = s5p_sdhci_ids,
  205. .bind = s5p_sdhci_bind,
  206. .ops = &sdhci_ops,
  207. .probe = s5p_sdhci_probe,
  208. .priv_auto = sizeof(struct sdhci_host),
  209. .plat_auto = sizeof(struct s5p_sdhci_plat),
  210. };
  211. #endif /* CONFIG_DM_MMC */