rockchip_sdhci.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd
  4. *
  5. * Rockchip SD Host Controller Interface
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <dm/ofnode.h>
  11. #include <dt-structs.h>
  12. #include <linux/delay.h>
  13. #include <linux/err.h>
  14. #include <linux/libfdt.h>
  15. #include <linux/iopoll.h>
  16. #include <malloc.h>
  17. #include <mapmem.h>
  18. #include "mmc_private.h"
  19. #include <sdhci.h>
  20. #include <syscon.h>
  21. #include <asm/arch-rockchip/clock.h>
  22. #include <asm/arch-rockchip/hardware.h>
  23. /* 400KHz is max freq for card ID etc. Use that as min */
  24. #define EMMC_MIN_FREQ 400000
  25. #define KHz (1000)
  26. #define MHz (1000 * KHz)
  27. #define SDHCI_TUNING_LOOP_COUNT 40
  28. #define PHYCTRL_CALDONE_MASK 0x1
  29. #define PHYCTRL_CALDONE_SHIFT 0x6
  30. #define PHYCTRL_CALDONE_DONE 0x1
  31. #define PHYCTRL_DLLRDY_MASK 0x1
  32. #define PHYCTRL_DLLRDY_SHIFT 0x5
  33. #define PHYCTRL_DLLRDY_DONE 0x1
  34. #define PHYCTRL_FREQSEL_200M 0x0
  35. #define PHYCTRL_FREQSEL_50M 0x1
  36. #define PHYCTRL_FREQSEL_100M 0x2
  37. #define PHYCTRL_FREQSEL_150M 0x3
  38. #define PHYCTRL_DLL_LOCK_WO_TMOUT(x) \
  39. ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
  40. PHYCTRL_DLLRDY_DONE)
  41. /* Rockchip specific Registers */
  42. #define DWCMSHC_EMMC_DLL_CTRL 0x800
  43. #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
  44. #define DWCMSHC_EMMC_DLL_RXCLK 0x804
  45. #define DWCMSHC_EMMC_DLL_TXCLK 0x808
  46. #define DWCMSHC_EMMC_DLL_STRBIN 0x80c
  47. #define DWCMSHC_EMMC_DLL_STATUS0 0x840
  48. #define DWCMSHC_EMMC_DLL_STATUS1 0x844
  49. #define DWCMSHC_EMMC_DLL_START BIT(0)
  50. #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
  51. #define DWCMSHC_EMMC_DLL_START_POINT 16
  52. #define DWCMSHC_EMMC_DLL_START_DEFAULT 5
  53. #define DWCMSHC_EMMC_DLL_INC_VALUE 2
  54. #define DWCMSHC_EMMC_DLL_INC 8
  55. #define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
  56. #define DLL_TXCLK_TAPNUM_DEFAULT 0x10
  57. #define DLL_STRBIN_TAPNUM_DEFAULT 0x3
  58. #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
  59. #define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
  60. #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
  61. #define DLL_RXCLK_NO_INVERTER 1
  62. #define DLL_RXCLK_INVERTER 0
  63. #define DWCMSHC_ENHANCED_STROBE BIT(8)
  64. #define DLL_LOCK_WO_TMOUT(x) \
  65. ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
  66. (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
  67. #define ROCKCHIP_MAX_CLKS 3
  68. struct rockchip_sdhc_plat {
  69. struct mmc_config cfg;
  70. struct mmc mmc;
  71. };
  72. struct rockchip_emmc_phy {
  73. u32 emmcphy_con[7];
  74. u32 reserved;
  75. u32 emmcphy_status;
  76. };
  77. struct rockchip_sdhc {
  78. struct sdhci_host host;
  79. struct udevice *dev;
  80. void *base;
  81. struct rockchip_emmc_phy *phy;
  82. struct clk emmc_clk;
  83. };
  84. struct sdhci_data {
  85. int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock);
  86. int (*emmc_phy_init)(struct udevice *dev);
  87. int (*get_phy)(struct udevice *dev);
  88. };
  89. static int rk3399_emmc_phy_init(struct udevice *dev)
  90. {
  91. return 0;
  92. }
  93. static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
  94. {
  95. u32 caldone, dllrdy, freqsel;
  96. writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]);
  97. writel(RK_CLRSETBITS(1 << 11, 1 << 11), &phy->emmcphy_con[0]);
  98. writel(RK_CLRSETBITS(0xf << 7, 6 << 7), &phy->emmcphy_con[0]);
  99. /*
  100. * According to the user manual, calpad calibration
  101. * cycle takes more than 2us without the minimal recommended
  102. * value, so we may need a little margin here
  103. */
  104. udelay(3);
  105. writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]);
  106. /*
  107. * According to the user manual, it asks driver to
  108. * wait 5us for calpad busy trimming. But it seems that
  109. * 5us of caldone isn't enough for all cases.
  110. */
  111. udelay(500);
  112. caldone = readl(&phy->emmcphy_status);
  113. caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
  114. if (caldone != PHYCTRL_CALDONE_DONE) {
  115. printf("%s: caldone timeout.\n", __func__);
  116. return;
  117. }
  118. /* Set the frequency of the DLL operation */
  119. if (clock < 75 * MHz)
  120. freqsel = PHYCTRL_FREQSEL_50M;
  121. else if (clock < 125 * MHz)
  122. freqsel = PHYCTRL_FREQSEL_100M;
  123. else if (clock < 175 * MHz)
  124. freqsel = PHYCTRL_FREQSEL_150M;
  125. else
  126. freqsel = PHYCTRL_FREQSEL_200M;
  127. /* Set the frequency of the DLL operation */
  128. writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]);
  129. writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]);
  130. read_poll_timeout(readl, &phy->emmcphy_status, dllrdy,
  131. PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1, 5000);
  132. }
  133. static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy)
  134. {
  135. writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]);
  136. writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]);
  137. }
  138. static int rk3399_emmc_get_phy(struct udevice *dev)
  139. {
  140. struct rockchip_sdhc *priv = dev_get_priv(dev);
  141. ofnode phy_node;
  142. void *grf_base;
  143. u32 grf_phy_offset, phandle;
  144. phandle = dev_read_u32_default(dev, "phys", 0);
  145. phy_node = ofnode_get_by_phandle(phandle);
  146. if (!ofnode_valid(phy_node)) {
  147. debug("Not found emmc phy device\n");
  148. return -ENODEV;
  149. }
  150. grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  151. if (grf_base < 0) {
  152. printf("%s Get syscon grf failed", __func__);
  153. return -ENODEV;
  154. }
  155. grf_phy_offset = ofnode_read_u32_default(phy_node, "reg", 0);
  156. priv->phy = (struct rockchip_emmc_phy *)(grf_base + grf_phy_offset);
  157. return 0;
  158. }
  159. static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
  160. {
  161. struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
  162. int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
  163. if (cycle_phy)
  164. rk3399_emmc_phy_power_off(priv->phy);
  165. sdhci_set_clock(host->mmc, clock);
  166. if (cycle_phy)
  167. rk3399_emmc_phy_power_on(priv->phy, clock);
  168. return 0;
  169. }
  170. static int rk3568_emmc_phy_init(struct udevice *dev)
  171. {
  172. struct rockchip_sdhc *prv = dev_get_priv(dev);
  173. struct sdhci_host *host = &prv->host;
  174. u32 extra;
  175. extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
  176. sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
  177. return 0;
  178. }
  179. static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
  180. {
  181. struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
  182. int val, ret;
  183. u32 extra;
  184. if (clock > host->max_clk)
  185. clock = host->max_clk;
  186. if (clock)
  187. clk_set_rate(&priv->emmc_clk, clock);
  188. sdhci_set_clock(host->mmc, clock);
  189. if (clock >= 100 * MHz) {
  190. /* reset DLL */
  191. sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL);
  192. udelay(1);
  193. sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
  194. /* Init DLL settings */
  195. extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
  196. DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC |
  197. DWCMSHC_EMMC_DLL_START;
  198. sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
  199. ret = read_poll_timeout(readl, host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
  200. val, DLL_LOCK_WO_TMOUT(val), 1, 500);
  201. if (ret)
  202. return ret;
  203. extra = DWCMSHC_EMMC_DLL_DLYENA |
  204. DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
  205. sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
  206. extra = DWCMSHC_EMMC_DLL_DLYENA |
  207. DLL_TXCLK_TAPNUM_DEFAULT |
  208. DLL_TXCLK_TAPNUM_FROM_SW;
  209. sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
  210. extra = DWCMSHC_EMMC_DLL_DLYENA |
  211. DLL_STRBIN_TAPNUM_DEFAULT;
  212. sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
  213. } else {
  214. /* reset the clock phase when the frequency is lower than 100MHz */
  215. sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
  216. extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
  217. sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
  218. sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
  219. sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
  220. }
  221. return 0;
  222. }
  223. static int rk3568_emmc_get_phy(struct udevice *dev)
  224. {
  225. return 0;
  226. }
  227. static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
  228. {
  229. struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
  230. struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
  231. struct mmc *mmc = host->mmc;
  232. uint clock = mmc->tran_speed;
  233. u32 reg;
  234. if (!clock)
  235. clock = mmc->clock;
  236. if (data->emmc_set_clock)
  237. data->emmc_set_clock(host, clock);
  238. if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) {
  239. reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  240. reg &= ~SDHCI_CTRL_UHS_MASK;
  241. reg |= SDHCI_CTRL_HS400;
  242. sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
  243. } else {
  244. sdhci_set_uhs_timing(host);
  245. }
  246. return 0;
  247. }
  248. static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
  249. {
  250. struct sdhci_host *host = dev_get_priv(mmc->dev);
  251. char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
  252. struct mmc_cmd cmd;
  253. u32 ctrl, blk_size;
  254. int ret = 0;
  255. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  256. ctrl |= SDHCI_CTRL_EXEC_TUNING;
  257. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  258. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
  259. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
  260. blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64);
  261. if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && host->mmc->bus_width == 8)
  262. blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128);
  263. sdhci_writew(host, blk_size, SDHCI_BLOCK_SIZE);
  264. sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
  265. cmd.cmdidx = opcode;
  266. cmd.resp_type = MMC_RSP_R1;
  267. cmd.cmdarg = 0;
  268. do {
  269. if (tuning_loop_counter-- == 0)
  270. break;
  271. mmc_send_cmd(mmc, &cmd, NULL);
  272. if (opcode == MMC_CMD_SEND_TUNING_BLOCK)
  273. /*
  274. * For tuning command, do not do busy loop. As tuning
  275. * is happening (CLK-DATA latching for setup/hold time
  276. * requirements), give time to complete
  277. */
  278. udelay(1);
  279. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  280. } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
  281. if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
  282. printf("%s:Tuning failed\n", __func__);
  283. ret = -EIO;
  284. }
  285. if (tuning_loop_counter < 0) {
  286. ctrl &= ~SDHCI_CTRL_TUNED_CLK;
  287. sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
  288. }
  289. /* Enable only interrupts served by the SD controller */
  290. sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, SDHCI_INT_ENABLE);
  291. /* Mask all sdhci interrupt sources */
  292. sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
  293. return ret;
  294. }
  295. static struct sdhci_ops rockchip_sdhci_ops = {
  296. .set_ios_post = rockchip_sdhci_set_ios_post,
  297. .platform_execute_tuning = &rockchip_sdhci_execute_tuning,
  298. };
  299. static int rockchip_sdhci_probe(struct udevice *dev)
  300. {
  301. struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev);
  302. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  303. struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
  304. struct rockchip_sdhc *prv = dev_get_priv(dev);
  305. struct mmc_config *cfg = &plat->cfg;
  306. struct sdhci_host *host = &prv->host;
  307. struct clk clk;
  308. int ret;
  309. host->max_clk = cfg->f_max;
  310. ret = clk_get_by_index(dev, 0, &clk);
  311. if (!ret) {
  312. ret = clk_set_rate(&clk, host->max_clk);
  313. if (IS_ERR_VALUE(ret))
  314. printf("%s clk set rate fail!\n", __func__);
  315. } else {
  316. printf("%s fail to get clk\n", __func__);
  317. }
  318. prv->emmc_clk = clk;
  319. prv->dev = dev;
  320. if (data->get_phy) {
  321. ret = data->get_phy(dev);
  322. if (ret)
  323. return ret;
  324. }
  325. if (data->emmc_phy_init) {
  326. ret = data->emmc_phy_init(dev);
  327. if (ret)
  328. return ret;
  329. }
  330. host->ops = &rockchip_sdhci_ops;
  331. host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
  332. host->mmc = &plat->mmc;
  333. host->mmc->priv = &prv->host;
  334. host->mmc->dev = dev;
  335. upriv->mmc = host->mmc;
  336. ret = sdhci_setup_cfg(cfg, host, cfg->f_max, EMMC_MIN_FREQ);
  337. if (ret)
  338. return ret;
  339. return sdhci_probe(dev);
  340. }
  341. static int rockchip_sdhci_of_to_plat(struct udevice *dev)
  342. {
  343. struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
  344. struct sdhci_host *host = dev_get_priv(dev);
  345. struct mmc_config *cfg = &plat->cfg;
  346. int ret;
  347. host->name = dev->name;
  348. host->ioaddr = dev_read_addr_ptr(dev);
  349. ret = mmc_of_parse(dev, cfg);
  350. if (ret)
  351. return ret;
  352. return 0;
  353. }
  354. static int rockchip_sdhci_bind(struct udevice *dev)
  355. {
  356. struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
  357. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  358. }
  359. static const struct sdhci_data rk3399_data = {
  360. .emmc_set_clock = rk3399_sdhci_emmc_set_clock,
  361. .get_phy = rk3399_emmc_get_phy,
  362. .emmc_phy_init = rk3399_emmc_phy_init,
  363. };
  364. static const struct sdhci_data rk3568_data = {
  365. .emmc_set_clock = rk3568_sdhci_emmc_set_clock,
  366. .get_phy = rk3568_emmc_get_phy,
  367. .emmc_phy_init = rk3568_emmc_phy_init,
  368. };
  369. static const struct udevice_id sdhci_ids[] = {
  370. {
  371. .compatible = "arasan,sdhci-5.1",
  372. .data = (ulong)&rk3399_data,
  373. },
  374. {
  375. .compatible = "rockchip,rk3568-dwcmshc",
  376. .data = (ulong)&rk3568_data,
  377. },
  378. { }
  379. };
  380. U_BOOT_DRIVER(arasan_sdhci_drv) = {
  381. .name = "rockchip_sdhci_5_1",
  382. .id = UCLASS_MMC,
  383. .of_match = sdhci_ids,
  384. .of_to_plat = rockchip_sdhci_of_to_plat,
  385. .ops = &sdhci_ops,
  386. .bind = rockchip_sdhci_bind,
  387. .probe = rockchip_sdhci_probe,
  388. .priv_auto = sizeof(struct rockchip_sdhc),
  389. .plat_auto = sizeof(struct rockchip_sdhc_plat),
  390. };