mtk-sd.c 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek SD/MMC Card Interface driver
  4. *
  5. * Copyright (C) 2018 MediaTek Inc.
  6. * Author: Weijie Gao <weijie.gao@mediatek.com>
  7. */
  8. #include <clk.h>
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <mmc.h>
  12. #include <errno.h>
  13. #include <malloc.h>
  14. #include <mapmem.h>
  15. #include <stdbool.h>
  16. #include <asm/gpio.h>
  17. #include <dm/device_compat.h>
  18. #include <dm/pinctrl.h>
  19. #include <linux/bitops.h>
  20. #include <linux/io.h>
  21. #include <linux/iopoll.h>
  22. /* MSDC_CFG */
  23. #define MSDC_CFG_HS400_CK_MODE_EXT BIT(22)
  24. #define MSDC_CFG_CKMOD_EXT_M 0x300000
  25. #define MSDC_CFG_CKMOD_EXT_S 20
  26. #define MSDC_CFG_CKDIV_EXT_M 0xfff00
  27. #define MSDC_CFG_CKDIV_EXT_S 8
  28. #define MSDC_CFG_HS400_CK_MODE BIT(18)
  29. #define MSDC_CFG_CKMOD_M 0x30000
  30. #define MSDC_CFG_CKMOD_S 16
  31. #define MSDC_CFG_CKDIV_M 0xff00
  32. #define MSDC_CFG_CKDIV_S 8
  33. #define MSDC_CFG_CKSTB BIT(7)
  34. #define MSDC_CFG_PIO BIT(3)
  35. #define MSDC_CFG_RST BIT(2)
  36. #define MSDC_CFG_CKPDN BIT(1)
  37. #define MSDC_CFG_MODE BIT(0)
  38. /* MSDC_IOCON */
  39. #define MSDC_IOCON_W_DSPL BIT(8)
  40. #define MSDC_IOCON_DSPL BIT(2)
  41. #define MSDC_IOCON_RSPL BIT(1)
  42. /* MSDC_PS */
  43. #define MSDC_PS_DAT0 BIT(16)
  44. #define MSDC_PS_CDDBCE_M 0xf000
  45. #define MSDC_PS_CDDBCE_S 12
  46. #define MSDC_PS_CDSTS BIT(1)
  47. #define MSDC_PS_CDEN BIT(0)
  48. /* #define MSDC_INT(EN) */
  49. #define MSDC_INT_ACMDRDY BIT(3)
  50. #define MSDC_INT_ACMDTMO BIT(4)
  51. #define MSDC_INT_ACMDCRCERR BIT(5)
  52. #define MSDC_INT_CMDRDY BIT(8)
  53. #define MSDC_INT_CMDTMO BIT(9)
  54. #define MSDC_INT_RSPCRCERR BIT(10)
  55. #define MSDC_INT_XFER_COMPL BIT(12)
  56. #define MSDC_INT_DATTMO BIT(14)
  57. #define MSDC_INT_DATCRCERR BIT(15)
  58. /* MSDC_FIFOCS */
  59. #define MSDC_FIFOCS_CLR BIT(31)
  60. #define MSDC_FIFOCS_TXCNT_M 0xff0000
  61. #define MSDC_FIFOCS_TXCNT_S 16
  62. #define MSDC_FIFOCS_RXCNT_M 0xff
  63. #define MSDC_FIFOCS_RXCNT_S 0
  64. /* #define SDC_CFG */
  65. #define SDC_CFG_DTOC_M 0xff000000
  66. #define SDC_CFG_DTOC_S 24
  67. #define SDC_CFG_SDIOIDE BIT(20)
  68. #define SDC_CFG_SDIO BIT(19)
  69. #define SDC_CFG_BUSWIDTH_M 0x30000
  70. #define SDC_CFG_BUSWIDTH_S 16
  71. /* SDC_CMD */
  72. #define SDC_CMD_BLK_LEN_M 0xfff0000
  73. #define SDC_CMD_BLK_LEN_S 16
  74. #define SDC_CMD_STOP BIT(14)
  75. #define SDC_CMD_WR BIT(13)
  76. #define SDC_CMD_DTYPE_M 0x1800
  77. #define SDC_CMD_DTYPE_S 11
  78. #define SDC_CMD_RSPTYP_M 0x380
  79. #define SDC_CMD_RSPTYP_S 7
  80. #define SDC_CMD_CMD_M 0x3f
  81. #define SDC_CMD_CMD_S 0
  82. /* SDC_STS */
  83. #define SDC_STS_CMDBUSY BIT(1)
  84. #define SDC_STS_SDCBUSY BIT(0)
  85. /* SDC_ADV_CFG0 */
  86. #define SDC_RX_ENHANCE_EN BIT(20)
  87. /* PATCH_BIT0 */
  88. #define MSDC_INT_DAT_LATCH_CK_SEL_M 0x380
  89. #define MSDC_INT_DAT_LATCH_CK_SEL_S 7
  90. /* PATCH_BIT1 */
  91. #define MSDC_PB1_STOP_DLY_M 0xf00
  92. #define MSDC_PB1_STOP_DLY_S 8
  93. /* PATCH_BIT2 */
  94. #define MSDC_PB2_CRCSTSENSEL_M 0xe0000000
  95. #define MSDC_PB2_CRCSTSENSEL_S 29
  96. #define MSDC_PB2_CFGCRCSTS BIT(28)
  97. #define MSDC_PB2_RESPSTSENSEL_M 0x70000
  98. #define MSDC_PB2_RESPSTSENSEL_S 16
  99. #define MSDC_PB2_CFGRESP BIT(15)
  100. #define MSDC_PB2_RESPWAIT_M 0x0c
  101. #define MSDC_PB2_RESPWAIT_S 2
  102. /* MSDC_PAD_CTRL0 */
  103. #define MSDC_PAD_CTRL0_CLKRDSEL_M 0xff000000
  104. #define MSDC_PAD_CTRL0_CLKRDSEL_S 24
  105. #define MSDC_PAD_CTRL0_CLKTDSEL BIT(20)
  106. #define MSDC_PAD_CTRL0_CLKIES BIT(19)
  107. #define MSDC_PAD_CTRL0_CLKSMT BIT(18)
  108. #define MSDC_PAD_CTRL0_CLKPU BIT(17)
  109. #define MSDC_PAD_CTRL0_CLKPD BIT(16)
  110. #define MSDC_PAD_CTRL0_CLKSR BIT(8)
  111. #define MSDC_PAD_CTRL0_CLKDRVP_M 0x70
  112. #define MSDC_PAD_CTRL0_CLKDRVP_S 4
  113. #define MSDC_PAD_CTRL0_CLKDRVN_M 0x7
  114. #define MSDC_PAD_CTRL0_CLKDRVN_S 0
  115. /* MSDC_PAD_CTRL1 */
  116. #define MSDC_PAD_CTRL1_CMDRDSEL_M 0xff000000
  117. #define MSDC_PAD_CTRL1_CMDRDSEL_S 24
  118. #define MSDC_PAD_CTRL1_CMDTDSEL BIT(20)
  119. #define MSDC_PAD_CTRL1_CMDIES BIT(19)
  120. #define MSDC_PAD_CTRL1_CMDSMT BIT(18)
  121. #define MSDC_PAD_CTRL1_CMDPU BIT(17)
  122. #define MSDC_PAD_CTRL1_CMDPD BIT(16)
  123. #define MSDC_PAD_CTRL1_CMDSR BIT(8)
  124. #define MSDC_PAD_CTRL1_CMDDRVP_M 0x70
  125. #define MSDC_PAD_CTRL1_CMDDRVP_S 4
  126. #define MSDC_PAD_CTRL1_CMDDRVN_M 0x7
  127. #define MSDC_PAD_CTRL1_CMDDRVN_S 0
  128. /* MSDC_PAD_CTRL2 */
  129. #define MSDC_PAD_CTRL2_DATRDSEL_M 0xff000000
  130. #define MSDC_PAD_CTRL2_DATRDSEL_S 24
  131. #define MSDC_PAD_CTRL2_DATTDSEL BIT(20)
  132. #define MSDC_PAD_CTRL2_DATIES BIT(19)
  133. #define MSDC_PAD_CTRL2_DATSMT BIT(18)
  134. #define MSDC_PAD_CTRL2_DATPU BIT(17)
  135. #define MSDC_PAD_CTRL2_DATPD BIT(16)
  136. #define MSDC_PAD_CTRL2_DATSR BIT(8)
  137. #define MSDC_PAD_CTRL2_DATDRVP_M 0x70
  138. #define MSDC_PAD_CTRL2_DATDRVP_S 4
  139. #define MSDC_PAD_CTRL2_DATDRVN_M 0x7
  140. #define MSDC_PAD_CTRL2_DATDRVN_S 0
  141. /* PAD_TUNE */
  142. #define MSDC_PAD_TUNE_CLKTDLY_M 0xf8000000
  143. #define MSDC_PAD_TUNE_CLKTDLY_S 27
  144. #define MSDC_PAD_TUNE_CMDRRDLY_M 0x7c00000
  145. #define MSDC_PAD_TUNE_CMDRRDLY_S 22
  146. #define MSDC_PAD_TUNE_CMD_SEL BIT(21)
  147. #define MSDC_PAD_TUNE_CMDRDLY_M 0x1f0000
  148. #define MSDC_PAD_TUNE_CMDRDLY_S 16
  149. #define MSDC_PAD_TUNE_RXDLYSEL BIT(15)
  150. #define MSDC_PAD_TUNE_RD_SEL BIT(13)
  151. #define MSDC_PAD_TUNE_DATRRDLY_M 0x1f00
  152. #define MSDC_PAD_TUNE_DATRRDLY_S 8
  153. #define MSDC_PAD_TUNE_DATWRDLY_M 0x1f
  154. #define MSDC_PAD_TUNE_DATWRDLY_S 0
  155. #define PAD_CMD_TUNE_RX_DLY3 0x3E
  156. #define PAD_CMD_TUNE_RX_DLY3_S 1
  157. /* PAD_TUNE0 */
  158. #define MSDC_PAD_TUNE0_DAT0RDDLY_M 0x1f000000
  159. #define MSDC_PAD_TUNE0_DAT0RDDLY_S 24
  160. #define MSDC_PAD_TUNE0_DAT1RDDLY_M 0x1f0000
  161. #define MSDC_PAD_TUNE0_DAT1RDDLY_S 16
  162. #define MSDC_PAD_TUNE0_DAT2RDDLY_M 0x1f00
  163. #define MSDC_PAD_TUNE0_DAT2RDDLY_S 8
  164. #define MSDC_PAD_TUNE0_DAT3RDDLY_M 0x1f
  165. #define MSDC_PAD_TUNE0_DAT3RDDLY_S 0
  166. /* PAD_TUNE1 */
  167. #define MSDC_PAD_TUNE1_DAT4RDDLY_M 0x1f000000
  168. #define MSDC_PAD_TUNE1_DAT4RDDLY_S 24
  169. #define MSDC_PAD_TUNE1_DAT5RDDLY_M 0x1f0000
  170. #define MSDC_PAD_TUNE1_DAT5RDDLY_S 16
  171. #define MSDC_PAD_TUNE1_DAT6RDDLY_M 0x1f00
  172. #define MSDC_PAD_TUNE1_DAT6RDDLY_S 8
  173. #define MSDC_PAD_TUNE1_DAT7RDDLY_M 0x1f
  174. #define MSDC_PAD_TUNE1_DAT7RDDLY_S 0
  175. /* EMMC50_CFG0 */
  176. #define EMMC50_CFG_CFCSTS_SEL BIT(4)
  177. /* SDC_FIFO_CFG */
  178. #define SDC_FIFO_CFG_WRVALIDSEL BIT(24)
  179. #define SDC_FIFO_CFG_RDVALIDSEL BIT(25)
  180. /* EMMC_TOP_CONTROL mask */
  181. #define PAD_RXDLY_SEL BIT(0)
  182. #define DELAY_EN BIT(1)
  183. #define PAD_DAT_RD_RXDLY2 (0x1f << 2)
  184. #define PAD_DAT_RD_RXDLY (0x1f << 7)
  185. #define PAD_DAT_RD_RXDLY_S 7
  186. #define PAD_DAT_RD_RXDLY2_SEL BIT(12)
  187. #define PAD_DAT_RD_RXDLY_SEL BIT(13)
  188. #define DATA_K_VALUE_SEL BIT(14)
  189. #define SDC_RX_ENH_EN BIT(15)
  190. /* EMMC_TOP_CMD mask */
  191. #define PAD_CMD_RXDLY2 (0x1f << 0)
  192. #define PAD_CMD_RXDLY (0x1f << 5)
  193. #define PAD_CMD_RXDLY_S 5
  194. #define PAD_CMD_RD_RXDLY2_SEL BIT(10)
  195. #define PAD_CMD_RD_RXDLY_SEL BIT(11)
  196. #define PAD_CMD_TX_DLY (0x1f << 12)
  197. /* SDC_CFG_BUSWIDTH */
  198. #define MSDC_BUS_1BITS 0x0
  199. #define MSDC_BUS_4BITS 0x1
  200. #define MSDC_BUS_8BITS 0x2
  201. #define MSDC_FIFO_SIZE 128
  202. #define PAD_DELAY_MAX 32
  203. #define DEFAULT_CD_DEBOUNCE 8
  204. #define SCLK_CYCLES_SHIFT 20
  205. #define MIN_BUS_CLK 200000
  206. #define CMD_INTS_MASK \
  207. (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO)
  208. #define DATA_INTS_MASK \
  209. (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR)
  210. /* Register offset */
  211. struct mtk_sd_regs {
  212. u32 msdc_cfg;
  213. u32 msdc_iocon;
  214. u32 msdc_ps;
  215. u32 msdc_int;
  216. u32 msdc_inten;
  217. u32 msdc_fifocs;
  218. u32 msdc_txdata;
  219. u32 msdc_rxdata;
  220. u32 reserved0[4];
  221. u32 sdc_cfg;
  222. u32 sdc_cmd;
  223. u32 sdc_arg;
  224. u32 sdc_sts;
  225. u32 sdc_resp[4];
  226. u32 sdc_blk_num;
  227. u32 sdc_vol_chg;
  228. u32 sdc_csts;
  229. u32 sdc_csts_en;
  230. u32 sdc_datcrc_sts;
  231. u32 sdc_adv_cfg0;
  232. u32 reserved1[2];
  233. u32 emmc_cfg0;
  234. u32 emmc_cfg1;
  235. u32 emmc_sts;
  236. u32 emmc_iocon;
  237. u32 sd_acmd_resp;
  238. u32 sd_acmd19_trg;
  239. u32 sd_acmd19_sts;
  240. u32 dma_sa_high4bit;
  241. u32 dma_sa;
  242. u32 dma_ca;
  243. u32 dma_ctrl;
  244. u32 dma_cfg;
  245. u32 sw_dbg_sel;
  246. u32 sw_dbg_out;
  247. u32 dma_length;
  248. u32 reserved2;
  249. u32 patch_bit0;
  250. u32 patch_bit1;
  251. u32 patch_bit2;
  252. u32 reserved3;
  253. u32 dat0_tune_crc;
  254. u32 dat1_tune_crc;
  255. u32 dat2_tune_crc;
  256. u32 dat3_tune_crc;
  257. u32 cmd_tune_crc;
  258. u32 sdio_tune_wind;
  259. u32 reserved4[2];
  260. u32 pad_ctrl0;
  261. u32 pad_ctrl1;
  262. u32 pad_ctrl2;
  263. u32 pad_tune;
  264. u32 pad_tune0;
  265. u32 pad_tune1;
  266. u32 dat_rd_dly[4];
  267. u32 reserved5[2];
  268. u32 hw_dbg_sel;
  269. u32 main_ver;
  270. u32 eco_ver;
  271. u32 reserved6[27];
  272. u32 pad_ds_tune;
  273. u32 pad_cmd_tune;
  274. u32 reserved7[30];
  275. u32 emmc50_cfg0;
  276. u32 reserved8[7];
  277. u32 sdc_fifo_cfg;
  278. };
  279. struct msdc_top_regs {
  280. u32 emmc_top_control;
  281. u32 emmc_top_cmd;
  282. u32 emmc50_pad_ctl0;
  283. u32 emmc50_pad_ds_tune;
  284. u32 emmc50_pad_dat0_tune;
  285. u32 emmc50_pad_dat1_tune;
  286. u32 emmc50_pad_dat2_tune;
  287. u32 emmc50_pad_dat3_tune;
  288. u32 emmc50_pad_dat4_tune;
  289. u32 emmc50_pad_dat5_tune;
  290. u32 emmc50_pad_dat6_tune;
  291. u32 emmc50_pad_dat7_tune;
  292. };
  293. struct msdc_compatible {
  294. u8 clk_div_bits;
  295. bool pad_tune0;
  296. bool async_fifo;
  297. bool data_tune;
  298. bool busy_check;
  299. bool stop_clk_fix;
  300. bool enhance_rx;
  301. bool builtin_pad_ctrl;
  302. bool default_pad_dly;
  303. };
  304. struct msdc_delay_phase {
  305. u8 maxlen;
  306. u8 start;
  307. u8 final_phase;
  308. };
  309. struct msdc_plat {
  310. struct mmc_config cfg;
  311. struct mmc mmc;
  312. };
  313. struct msdc_tune_para {
  314. u32 iocon;
  315. u32 pad_tune;
  316. u32 pad_cmd_tune;
  317. };
  318. struct msdc_host {
  319. struct mtk_sd_regs *base;
  320. struct msdc_top_regs *top_base;
  321. struct mmc *mmc;
  322. struct msdc_compatible *dev_comp;
  323. struct clk src_clk; /* for SD/MMC bus clock */
  324. struct clk src_clk_cg; /* optional, MSDC source clock control gate */
  325. struct clk h_clk; /* MSDC core clock */
  326. u32 src_clk_freq; /* source clock */
  327. u32 mclk; /* mmc framework required bus clock */
  328. u32 sclk; /* actual calculated bus clock */
  329. /* operation timeout clocks */
  330. u32 timeout_ns;
  331. u32 timeout_clks;
  332. /* tuning options */
  333. u32 hs400_ds_delay;
  334. u32 hs200_cmd_int_delay;
  335. u32 hs200_write_int_delay;
  336. u32 latch_ck;
  337. u32 r_smpl; /* sample edge */
  338. bool hs400_mode;
  339. /* whether to use gpio detection or built-in hw detection */
  340. bool builtin_cd;
  341. bool cd_active_high;
  342. /* card detection / write protection GPIOs */
  343. #if CONFIG_IS_ENABLED(DM_GPIO)
  344. struct gpio_desc gpio_wp;
  345. struct gpio_desc gpio_cd;
  346. #endif
  347. uint last_resp_type;
  348. uint last_data_write;
  349. enum bus_mode timing;
  350. struct msdc_tune_para def_tune_para;
  351. struct msdc_tune_para saved_tune_para;
  352. };
  353. static void msdc_reset_hw(struct msdc_host *host)
  354. {
  355. u32 reg;
  356. setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST);
  357. readl_poll_timeout(&host->base->msdc_cfg, reg,
  358. !(reg & MSDC_CFG_RST), 1000000);
  359. }
  360. static void msdc_fifo_clr(struct msdc_host *host)
  361. {
  362. u32 reg;
  363. setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR);
  364. readl_poll_timeout(&host->base->msdc_fifocs, reg,
  365. !(reg & MSDC_FIFOCS_CLR), 1000000);
  366. }
  367. static u32 msdc_fifo_rx_bytes(struct msdc_host *host)
  368. {
  369. return (readl(&host->base->msdc_fifocs) &
  370. MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S;
  371. }
  372. static u32 msdc_fifo_tx_bytes(struct msdc_host *host)
  373. {
  374. return (readl(&host->base->msdc_fifocs) &
  375. MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S;
  376. }
  377. static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd)
  378. {
  379. u32 resp;
  380. switch (cmd->resp_type) {
  381. /* Actually, R1, R5, R6, R7 are the same */
  382. case MMC_RSP_R1:
  383. resp = 0x1;
  384. break;
  385. case MMC_RSP_R1b:
  386. resp = 0x7;
  387. break;
  388. case MMC_RSP_R2:
  389. resp = 0x2;
  390. break;
  391. case MMC_RSP_R3:
  392. resp = 0x3;
  393. break;
  394. case MMC_RSP_NONE:
  395. default:
  396. resp = 0x0;
  397. break;
  398. }
  399. return resp;
  400. }
  401. static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
  402. struct mmc_cmd *cmd,
  403. struct mmc_data *data)
  404. {
  405. u32 opcode = cmd->cmdidx;
  406. u32 resp_type = msdc_cmd_find_resp(host, cmd);
  407. uint blocksize = 0;
  408. u32 dtype = 0;
  409. u32 rawcmd = 0;
  410. switch (opcode) {
  411. case MMC_CMD_WRITE_MULTIPLE_BLOCK:
  412. case MMC_CMD_READ_MULTIPLE_BLOCK:
  413. dtype = 2;
  414. break;
  415. case MMC_CMD_WRITE_SINGLE_BLOCK:
  416. case MMC_CMD_READ_SINGLE_BLOCK:
  417. case SD_CMD_APP_SEND_SCR:
  418. case MMC_CMD_SEND_TUNING_BLOCK:
  419. case MMC_CMD_SEND_TUNING_BLOCK_HS200:
  420. dtype = 1;
  421. break;
  422. case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
  423. case SD_CMD_SEND_IF_COND: /* same as MMC_CMD_SEND_EXT_CSD */
  424. case SD_CMD_APP_SD_STATUS: /* same as MMC_CMD_SEND_STATUS */
  425. if (data)
  426. dtype = 1;
  427. }
  428. if (data) {
  429. if (data->flags == MMC_DATA_WRITE)
  430. rawcmd |= SDC_CMD_WR;
  431. if (data->blocks > 1)
  432. dtype = 2;
  433. blocksize = data->blocksize;
  434. }
  435. rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) |
  436. ((resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M) |
  437. ((blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M) |
  438. ((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M);
  439. if (opcode == MMC_CMD_STOP_TRANSMISSION)
  440. rawcmd |= SDC_CMD_STOP;
  441. return rawcmd;
  442. }
  443. static int msdc_cmd_done(struct msdc_host *host, int events,
  444. struct mmc_cmd *cmd)
  445. {
  446. u32 *rsp = cmd->response;
  447. int ret = 0;
  448. if (cmd->resp_type & MMC_RSP_PRESENT) {
  449. if (cmd->resp_type & MMC_RSP_136) {
  450. rsp[0] = readl(&host->base->sdc_resp[3]);
  451. rsp[1] = readl(&host->base->sdc_resp[2]);
  452. rsp[2] = readl(&host->base->sdc_resp[1]);
  453. rsp[3] = readl(&host->base->sdc_resp[0]);
  454. } else {
  455. rsp[0] = readl(&host->base->sdc_resp[0]);
  456. }
  457. }
  458. if (!(events & MSDC_INT_CMDRDY)) {
  459. if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
  460. cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
  461. /*
  462. * should not clear fifo/interrupt as the tune data
  463. * may have alreay come.
  464. */
  465. msdc_reset_hw(host);
  466. if (events & MSDC_INT_CMDTMO)
  467. ret = -ETIMEDOUT;
  468. else
  469. ret = -EIO;
  470. }
  471. return ret;
  472. }
  473. static bool msdc_cmd_is_ready(struct msdc_host *host)
  474. {
  475. int ret;
  476. u32 reg;
  477. /* The max busy time we can endure is 20ms */
  478. ret = readl_poll_timeout(&host->base->sdc_sts, reg,
  479. !(reg & SDC_STS_CMDBUSY), 20000);
  480. if (ret) {
  481. pr_err("CMD bus busy detected\n");
  482. msdc_reset_hw(host);
  483. return false;
  484. }
  485. if (host->last_resp_type == MMC_RSP_R1b && host->last_data_write) {
  486. ret = readl_poll_timeout(&host->base->msdc_ps, reg,
  487. reg & MSDC_PS_DAT0, 1000000);
  488. if (ret) {
  489. pr_err("Card stuck in programming state!\n");
  490. msdc_reset_hw(host);
  491. return false;
  492. }
  493. }
  494. return true;
  495. }
  496. static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
  497. struct mmc_data *data)
  498. {
  499. u32 rawcmd;
  500. u32 status;
  501. u32 blocks = 0;
  502. int ret;
  503. if (!msdc_cmd_is_ready(host))
  504. return -EIO;
  505. if ((readl(&host->base->msdc_fifocs) &
  506. MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S ||
  507. (readl(&host->base->msdc_fifocs) &
  508. MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) {
  509. pr_err("TX/RX FIFO non-empty before start of IO. Reset\n");
  510. msdc_reset_hw(host);
  511. }
  512. msdc_fifo_clr(host);
  513. host->last_resp_type = cmd->resp_type;
  514. host->last_data_write = 0;
  515. rawcmd = msdc_cmd_prepare_raw_cmd(host, cmd, data);
  516. if (data)
  517. blocks = data->blocks;
  518. writel(CMD_INTS_MASK, &host->base->msdc_int);
  519. writel(DATA_INTS_MASK, &host->base->msdc_int);
  520. writel(blocks, &host->base->sdc_blk_num);
  521. writel(cmd->cmdarg, &host->base->sdc_arg);
  522. writel(rawcmd, &host->base->sdc_cmd);
  523. ret = readl_poll_timeout(&host->base->msdc_int, status,
  524. status & CMD_INTS_MASK, 1000000);
  525. if (ret)
  526. status = MSDC_INT_CMDTMO;
  527. return msdc_cmd_done(host, status, cmd);
  528. }
  529. static void msdc_fifo_read(struct msdc_host *host, u8 *buf, u32 size)
  530. {
  531. u32 *wbuf;
  532. while ((size_t)buf % 4) {
  533. *buf++ = readb(&host->base->msdc_rxdata);
  534. size--;
  535. }
  536. wbuf = (u32 *)buf;
  537. while (size >= 4) {
  538. *wbuf++ = readl(&host->base->msdc_rxdata);
  539. size -= 4;
  540. }
  541. buf = (u8 *)wbuf;
  542. while (size) {
  543. *buf++ = readb(&host->base->msdc_rxdata);
  544. size--;
  545. }
  546. }
  547. static void msdc_fifo_write(struct msdc_host *host, const u8 *buf, u32 size)
  548. {
  549. const u32 *wbuf;
  550. while ((size_t)buf % 4) {
  551. writeb(*buf++, &host->base->msdc_txdata);
  552. size--;
  553. }
  554. wbuf = (const u32 *)buf;
  555. while (size >= 4) {
  556. writel(*wbuf++, &host->base->msdc_txdata);
  557. size -= 4;
  558. }
  559. buf = (const u8 *)wbuf;
  560. while (size) {
  561. writeb(*buf++, &host->base->msdc_txdata);
  562. size--;
  563. }
  564. }
  565. static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size)
  566. {
  567. u32 status;
  568. u32 chksz;
  569. int ret = 0;
  570. while (1) {
  571. status = readl(&host->base->msdc_int);
  572. writel(status, &host->base->msdc_int);
  573. status &= DATA_INTS_MASK;
  574. if (status & MSDC_INT_DATCRCERR) {
  575. ret = -EIO;
  576. break;
  577. }
  578. if (status & MSDC_INT_DATTMO) {
  579. ret = -ETIMEDOUT;
  580. break;
  581. }
  582. chksz = min(size, (u32)MSDC_FIFO_SIZE);
  583. if (msdc_fifo_rx_bytes(host) >= chksz) {
  584. msdc_fifo_read(host, ptr, chksz);
  585. ptr += chksz;
  586. size -= chksz;
  587. }
  588. if (status & MSDC_INT_XFER_COMPL) {
  589. if (size) {
  590. pr_err("data not fully read\n");
  591. ret = -EIO;
  592. }
  593. break;
  594. }
  595. }
  596. return ret;
  597. }
  598. static int msdc_pio_write(struct msdc_host *host, const u8 *ptr, u32 size)
  599. {
  600. u32 status;
  601. u32 chksz;
  602. int ret = 0;
  603. while (1) {
  604. status = readl(&host->base->msdc_int);
  605. writel(status, &host->base->msdc_int);
  606. status &= DATA_INTS_MASK;
  607. if (status & MSDC_INT_DATCRCERR) {
  608. ret = -EIO;
  609. break;
  610. }
  611. if (status & MSDC_INT_DATTMO) {
  612. ret = -ETIMEDOUT;
  613. break;
  614. }
  615. if (status & MSDC_INT_XFER_COMPL) {
  616. if (size) {
  617. pr_err("data not fully written\n");
  618. ret = -EIO;
  619. }
  620. break;
  621. }
  622. chksz = min(size, (u32)MSDC_FIFO_SIZE);
  623. if (MSDC_FIFO_SIZE - msdc_fifo_tx_bytes(host) >= chksz) {
  624. msdc_fifo_write(host, ptr, chksz);
  625. ptr += chksz;
  626. size -= chksz;
  627. }
  628. }
  629. return ret;
  630. }
  631. static int msdc_start_data(struct msdc_host *host, struct mmc_data *data)
  632. {
  633. u32 size;
  634. int ret;
  635. if (data->flags == MMC_DATA_WRITE)
  636. host->last_data_write = 1;
  637. size = data->blocks * data->blocksize;
  638. if (data->flags == MMC_DATA_WRITE)
  639. ret = msdc_pio_write(host, (const u8 *)data->src, size);
  640. else
  641. ret = msdc_pio_read(host, (u8 *)data->dest, size);
  642. if (ret) {
  643. msdc_reset_hw(host);
  644. msdc_fifo_clr(host);
  645. }
  646. return ret;
  647. }
  648. static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  649. struct mmc_data *data)
  650. {
  651. struct msdc_host *host = dev_get_priv(dev);
  652. int cmd_ret, data_ret;
  653. cmd_ret = msdc_start_command(host, cmd, data);
  654. if (cmd_ret &&
  655. !(cmd_ret == -EIO &&
  656. (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  657. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)))
  658. return cmd_ret;
  659. if (data) {
  660. data_ret = msdc_start_data(host, data);
  661. if (cmd_ret)
  662. return cmd_ret;
  663. else
  664. return data_ret;
  665. }
  666. return 0;
  667. }
  668. static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
  669. {
  670. u32 timeout, clk_ns, shift = SCLK_CYCLES_SHIFT;
  671. u32 mode = 0;
  672. host->timeout_ns = ns;
  673. host->timeout_clks = clks;
  674. if (host->sclk == 0) {
  675. timeout = 0;
  676. } else {
  677. clk_ns = 1000000000UL / host->sclk;
  678. timeout = (ns + clk_ns - 1) / clk_ns + clks;
  679. /* unit is 1048576 sclk cycles */
  680. timeout = (timeout + (0x1 << shift) - 1) >> shift;
  681. if (host->dev_comp->clk_div_bits == 8)
  682. mode = (readl(&host->base->msdc_cfg) &
  683. MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S;
  684. else
  685. mode = (readl(&host->base->msdc_cfg) &
  686. MSDC_CFG_CKMOD_EXT_M) >> MSDC_CFG_CKMOD_EXT_S;
  687. /* DDR mode will double the clk cycles for data timeout */
  688. timeout = mode >= 2 ? timeout * 2 : timeout;
  689. timeout = timeout > 1 ? timeout - 1 : 0;
  690. timeout = timeout > 255 ? 255 : timeout;
  691. }
  692. clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
  693. timeout << SDC_CFG_DTOC_S);
  694. }
  695. static void msdc_set_buswidth(struct msdc_host *host, u32 width)
  696. {
  697. u32 val = readl(&host->base->sdc_cfg);
  698. val &= ~SDC_CFG_BUSWIDTH_M;
  699. switch (width) {
  700. default:
  701. case 1:
  702. val |= (MSDC_BUS_1BITS << SDC_CFG_BUSWIDTH_S);
  703. break;
  704. case 4:
  705. val |= (MSDC_BUS_4BITS << SDC_CFG_BUSWIDTH_S);
  706. break;
  707. case 8:
  708. val |= (MSDC_BUS_8BITS << SDC_CFG_BUSWIDTH_S);
  709. break;
  710. }
  711. writel(val, &host->base->sdc_cfg);
  712. }
  713. static void msdc_set_mclk(struct udevice *dev,
  714. struct msdc_host *host, enum bus_mode timing, u32 hz)
  715. {
  716. u32 mode;
  717. u32 div;
  718. u32 sclk;
  719. u32 reg;
  720. if (!hz) {
  721. host->mclk = 0;
  722. clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
  723. return;
  724. }
  725. if (host->dev_comp->clk_div_bits == 8)
  726. clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_HS400_CK_MODE);
  727. else
  728. clrbits_le32(&host->base->msdc_cfg,
  729. MSDC_CFG_HS400_CK_MODE_EXT);
  730. if (timing == UHS_DDR50 || timing == MMC_DDR_52 ||
  731. timing == MMC_HS_400) {
  732. if (timing == MMC_HS_400)
  733. mode = 0x3;
  734. else
  735. mode = 0x2; /* ddr mode and use divisor */
  736. if (hz >= (host->src_clk_freq >> 2)) {
  737. div = 0; /* mean div = 1/4 */
  738. sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
  739. } else {
  740. div = (host->src_clk_freq + ((hz << 2) - 1)) /
  741. (hz << 2);
  742. sclk = (host->src_clk_freq >> 2) / div;
  743. div = (div >> 1);
  744. }
  745. if (timing == MMC_HS_400 && hz >= (host->src_clk_freq >> 1)) {
  746. if (host->dev_comp->clk_div_bits == 8)
  747. setbits_le32(&host->base->msdc_cfg,
  748. MSDC_CFG_HS400_CK_MODE);
  749. else
  750. setbits_le32(&host->base->msdc_cfg,
  751. MSDC_CFG_HS400_CK_MODE_EXT);
  752. sclk = host->src_clk_freq >> 1;
  753. div = 0; /* div is ignore when bit18 is set */
  754. }
  755. } else if (hz >= host->src_clk_freq) {
  756. mode = 0x1; /* no divisor */
  757. div = 0;
  758. sclk = host->src_clk_freq;
  759. } else {
  760. mode = 0x0; /* use divisor */
  761. if (hz >= (host->src_clk_freq >> 1)) {
  762. div = 0; /* mean div = 1/2 */
  763. sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
  764. } else {
  765. div = (host->src_clk_freq + ((hz << 2) - 1)) /
  766. (hz << 2);
  767. sclk = (host->src_clk_freq >> 2) / div;
  768. }
  769. }
  770. clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
  771. if (host->dev_comp->clk_div_bits == 8) {
  772. div = min(div, (u32)(MSDC_CFG_CKDIV_M >> MSDC_CFG_CKDIV_S));
  773. clrsetbits_le32(&host->base->msdc_cfg,
  774. MSDC_CFG_CKMOD_M | MSDC_CFG_CKDIV_M,
  775. (mode << MSDC_CFG_CKMOD_S) |
  776. (div << MSDC_CFG_CKDIV_S));
  777. } else {
  778. div = min(div, (u32)(MSDC_CFG_CKDIV_EXT_M >>
  779. MSDC_CFG_CKDIV_EXT_S));
  780. clrsetbits_le32(&host->base->msdc_cfg,
  781. MSDC_CFG_CKMOD_EXT_M | MSDC_CFG_CKDIV_EXT_M,
  782. (mode << MSDC_CFG_CKMOD_EXT_S) |
  783. (div << MSDC_CFG_CKDIV_EXT_S));
  784. }
  785. readl_poll_timeout(&host->base->msdc_cfg, reg,
  786. reg & MSDC_CFG_CKSTB, 1000000);
  787. setbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
  788. host->sclk = sclk;
  789. host->mclk = hz;
  790. host->timing = timing;
  791. /* needed because clk changed. */
  792. msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
  793. /*
  794. * mmc_select_hs400() will drop to 50Mhz and High speed mode,
  795. * tune result of hs200/200Mhz is not suitable for 50Mhz
  796. */
  797. if (host->sclk <= 52000000) {
  798. writel(host->def_tune_para.iocon, &host->base->msdc_iocon);
  799. writel(host->def_tune_para.pad_tune,
  800. &host->base->pad_tune);
  801. } else {
  802. writel(host->saved_tune_para.iocon, &host->base->msdc_iocon);
  803. writel(host->saved_tune_para.pad_tune,
  804. &host->base->pad_tune);
  805. }
  806. dev_dbg(dev, "sclk: %d, timing: %d\n", host->sclk, timing);
  807. }
  808. static int msdc_ops_set_ios(struct udevice *dev)
  809. {
  810. struct msdc_plat *plat = dev_get_plat(dev);
  811. struct msdc_host *host = dev_get_priv(dev);
  812. struct mmc *mmc = &plat->mmc;
  813. uint clock = mmc->clock;
  814. msdc_set_buswidth(host, mmc->bus_width);
  815. if (mmc->clk_disable)
  816. clock = 0;
  817. else if (clock < mmc->cfg->f_min)
  818. clock = mmc->cfg->f_min;
  819. if (host->mclk != clock || host->timing != mmc->selected_mode)
  820. msdc_set_mclk(dev, host, mmc->selected_mode, clock);
  821. return 0;
  822. }
  823. static int msdc_ops_get_cd(struct udevice *dev)
  824. {
  825. struct msdc_host *host = dev_get_priv(dev);
  826. u32 val;
  827. if (host->builtin_cd) {
  828. val = readl(&host->base->msdc_ps);
  829. val = !!(val & MSDC_PS_CDSTS);
  830. return !val ^ host->cd_active_high;
  831. }
  832. #if CONFIG_IS_ENABLED(DM_GPIO)
  833. if (!host->gpio_cd.dev)
  834. return 1;
  835. return dm_gpio_get_value(&host->gpio_cd);
  836. #else
  837. return 1;
  838. #endif
  839. }
  840. static int msdc_ops_get_wp(struct udevice *dev)
  841. {
  842. #if CONFIG_IS_ENABLED(DM_GPIO)
  843. struct msdc_host *host = dev_get_priv(dev);
  844. if (!host->gpio_wp.dev)
  845. return 0;
  846. return !dm_gpio_get_value(&host->gpio_wp);
  847. #else
  848. return 0;
  849. #endif
  850. }
  851. #ifdef MMC_SUPPORTS_TUNING
  852. static u32 test_delay_bit(u32 delay, u32 bit)
  853. {
  854. bit %= PAD_DELAY_MAX;
  855. return delay & (1 << bit);
  856. }
  857. static int get_delay_len(u32 delay, u32 start_bit)
  858. {
  859. int i;
  860. for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
  861. if (test_delay_bit(delay, start_bit + i) == 0)
  862. return i;
  863. }
  864. return PAD_DELAY_MAX - start_bit;
  865. }
  866. static struct msdc_delay_phase get_best_delay(struct udevice *dev,
  867. struct msdc_host *host, u32 delay)
  868. {
  869. int start = 0, len = 0;
  870. int start_final = 0, len_final = 0;
  871. u8 final_phase = 0xff;
  872. struct msdc_delay_phase delay_phase = { 0, };
  873. if (delay == 0) {
  874. dev_err(dev, "phase error: [map:%x]\n", delay);
  875. delay_phase.final_phase = final_phase;
  876. return delay_phase;
  877. }
  878. while (start < PAD_DELAY_MAX) {
  879. len = get_delay_len(delay, start);
  880. if (len_final < len) {
  881. start_final = start;
  882. len_final = len;
  883. }
  884. start += len ? len : 1;
  885. if (len >= 12 && start_final < 4)
  886. break;
  887. }
  888. /* The rule is to find the smallest delay cell */
  889. if (start_final == 0)
  890. final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
  891. else
  892. final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
  893. dev_info(dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
  894. delay, len_final, final_phase);
  895. delay_phase.maxlen = len_final;
  896. delay_phase.start = start_final;
  897. delay_phase.final_phase = final_phase;
  898. return delay_phase;
  899. }
  900. static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
  901. {
  902. void __iomem *tune_reg = &host->base->pad_tune;
  903. if (host->dev_comp->pad_tune0)
  904. tune_reg = &host->base->pad_tune0;
  905. if (host->top_base)
  906. clrsetbits_le32(&host->top_base->emmc_top_cmd, PAD_CMD_RXDLY,
  907. value << PAD_CMD_RXDLY_S);
  908. else
  909. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
  910. value << MSDC_PAD_TUNE_CMDRDLY_S);
  911. }
  912. static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
  913. {
  914. void __iomem *tune_reg = &host->base->pad_tune;
  915. if (host->dev_comp->pad_tune0)
  916. tune_reg = &host->base->pad_tune0;
  917. if (host->top_base)
  918. clrsetbits_le32(&host->top_base->emmc_top_control,
  919. PAD_DAT_RD_RXDLY, value << PAD_DAT_RD_RXDLY_S);
  920. else
  921. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
  922. value << MSDC_PAD_TUNE_DATRRDLY_S);
  923. }
  924. static int hs400_tune_response(struct udevice *dev, u32 opcode)
  925. {
  926. struct msdc_plat *plat = dev_get_plat(dev);
  927. struct msdc_host *host = dev_get_priv(dev);
  928. struct mmc *mmc = &plat->mmc;
  929. u32 cmd_delay = 0;
  930. struct msdc_delay_phase final_cmd_delay = { 0, };
  931. u8 final_delay;
  932. void __iomem *tune_reg = &host->base->pad_cmd_tune;
  933. int cmd_err;
  934. int i, j;
  935. setbits_le32(&host->base->pad_cmd_tune, BIT(0));
  936. if (mmc->selected_mode == MMC_HS_200 ||
  937. mmc->selected_mode == UHS_SDR104)
  938. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
  939. host->hs200_cmd_int_delay <<
  940. MSDC_PAD_TUNE_CMDRRDLY_S);
  941. if (host->r_smpl)
  942. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
  943. else
  944. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
  945. for (i = 0; i < PAD_DELAY_MAX; i++) {
  946. clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
  947. i << PAD_CMD_TUNE_RX_DLY3_S);
  948. for (j = 0; j < 3; j++) {
  949. mmc_send_tuning(mmc, opcode, &cmd_err);
  950. if (!cmd_err) {
  951. cmd_delay |= (1 << i);
  952. } else {
  953. cmd_delay &= ~(1 << i);
  954. break;
  955. }
  956. }
  957. }
  958. final_cmd_delay = get_best_delay(dev, host, cmd_delay);
  959. clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
  960. final_cmd_delay.final_phase <<
  961. PAD_CMD_TUNE_RX_DLY3_S);
  962. final_delay = final_cmd_delay.final_phase;
  963. dev_info(dev, "Final cmd pad delay: %x\n", final_delay);
  964. return final_delay == 0xff ? -EIO : 0;
  965. }
  966. static int msdc_tune_response(struct udevice *dev, u32 opcode)
  967. {
  968. struct msdc_plat *plat = dev_get_plat(dev);
  969. struct msdc_host *host = dev_get_priv(dev);
  970. struct mmc *mmc = &plat->mmc;
  971. u32 rise_delay = 0, fall_delay = 0;
  972. struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
  973. struct msdc_delay_phase internal_delay_phase;
  974. u8 final_delay, final_maxlen;
  975. u32 internal_delay = 0;
  976. void __iomem *tune_reg = &host->base->pad_tune;
  977. int cmd_err;
  978. int i, j;
  979. if (host->dev_comp->pad_tune0)
  980. tune_reg = &host->base->pad_tune0;
  981. if (mmc->selected_mode == MMC_HS_200 ||
  982. mmc->selected_mode == UHS_SDR104)
  983. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
  984. host->hs200_cmd_int_delay <<
  985. MSDC_PAD_TUNE_CMDRRDLY_S);
  986. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
  987. for (i = 0; i < PAD_DELAY_MAX; i++) {
  988. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
  989. i << MSDC_PAD_TUNE_CMDRDLY_S);
  990. for (j = 0; j < 3; j++) {
  991. mmc_send_tuning(mmc, opcode, &cmd_err);
  992. if (!cmd_err) {
  993. rise_delay |= (1 << i);
  994. } else {
  995. rise_delay &= ~(1 << i);
  996. break;
  997. }
  998. }
  999. }
  1000. final_rise_delay = get_best_delay(dev, host, rise_delay);
  1001. /* if rising edge has enough margin, do not scan falling edge */
  1002. if (final_rise_delay.maxlen >= 12 ||
  1003. (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
  1004. goto skip_fall;
  1005. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
  1006. for (i = 0; i < PAD_DELAY_MAX; i++) {
  1007. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
  1008. i << MSDC_PAD_TUNE_CMDRDLY_S);
  1009. for (j = 0; j < 3; j++) {
  1010. mmc_send_tuning(mmc, opcode, &cmd_err);
  1011. if (!cmd_err) {
  1012. fall_delay |= (1 << i);
  1013. } else {
  1014. fall_delay &= ~(1 << i);
  1015. break;
  1016. }
  1017. }
  1018. }
  1019. final_fall_delay = get_best_delay(dev, host, fall_delay);
  1020. skip_fall:
  1021. final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
  1022. if (final_maxlen == final_rise_delay.maxlen) {
  1023. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
  1024. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
  1025. final_rise_delay.final_phase <<
  1026. MSDC_PAD_TUNE_CMDRDLY_S);
  1027. final_delay = final_rise_delay.final_phase;
  1028. } else {
  1029. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
  1030. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
  1031. final_fall_delay.final_phase <<
  1032. MSDC_PAD_TUNE_CMDRDLY_S);
  1033. final_delay = final_fall_delay.final_phase;
  1034. }
  1035. if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
  1036. goto skip_internal;
  1037. for (i = 0; i < PAD_DELAY_MAX; i++) {
  1038. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
  1039. i << MSDC_PAD_TUNE_CMDRRDLY_S);
  1040. mmc_send_tuning(mmc, opcode, &cmd_err);
  1041. if (!cmd_err)
  1042. internal_delay |= (1 << i);
  1043. }
  1044. dev_dbg(dev, "Final internal delay: 0x%x\n", internal_delay);
  1045. internal_delay_phase = get_best_delay(dev, host, internal_delay);
  1046. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
  1047. internal_delay_phase.final_phase <<
  1048. MSDC_PAD_TUNE_CMDRRDLY_S);
  1049. skip_internal:
  1050. dev_dbg(dev, "Final cmd pad delay: %x\n", final_delay);
  1051. return final_delay == 0xff ? -EIO : 0;
  1052. }
  1053. static int msdc_tune_data(struct udevice *dev, u32 opcode)
  1054. {
  1055. struct msdc_plat *plat = dev_get_plat(dev);
  1056. struct msdc_host *host = dev_get_priv(dev);
  1057. struct mmc *mmc = &plat->mmc;
  1058. u32 rise_delay = 0, fall_delay = 0;
  1059. struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
  1060. u8 final_delay, final_maxlen;
  1061. void __iomem *tune_reg = &host->base->pad_tune;
  1062. int cmd_err;
  1063. int i, ret;
  1064. if (host->dev_comp->pad_tune0)
  1065. tune_reg = &host->base->pad_tune0;
  1066. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
  1067. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
  1068. for (i = 0; i < PAD_DELAY_MAX; i++) {
  1069. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
  1070. i << MSDC_PAD_TUNE_DATRRDLY_S);
  1071. ret = mmc_send_tuning(mmc, opcode, &cmd_err);
  1072. if (!ret) {
  1073. rise_delay |= (1 << i);
  1074. } else if (cmd_err) {
  1075. /* in this case, retune response is needed */
  1076. ret = msdc_tune_response(dev, opcode);
  1077. if (ret)
  1078. break;
  1079. }
  1080. }
  1081. final_rise_delay = get_best_delay(dev, host, rise_delay);
  1082. if (final_rise_delay.maxlen >= 12 ||
  1083. (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
  1084. goto skip_fall;
  1085. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
  1086. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
  1087. for (i = 0; i < PAD_DELAY_MAX; i++) {
  1088. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
  1089. i << MSDC_PAD_TUNE_DATRRDLY_S);
  1090. ret = mmc_send_tuning(mmc, opcode, &cmd_err);
  1091. if (!ret) {
  1092. fall_delay |= (1 << i);
  1093. } else if (cmd_err) {
  1094. /* in this case, retune response is needed */
  1095. ret = msdc_tune_response(dev, opcode);
  1096. if (ret)
  1097. break;
  1098. }
  1099. }
  1100. final_fall_delay = get_best_delay(dev, host, fall_delay);
  1101. skip_fall:
  1102. final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
  1103. if (final_maxlen == final_rise_delay.maxlen) {
  1104. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
  1105. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
  1106. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
  1107. final_rise_delay.final_phase <<
  1108. MSDC_PAD_TUNE_DATRRDLY_S);
  1109. final_delay = final_rise_delay.final_phase;
  1110. } else {
  1111. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
  1112. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
  1113. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
  1114. final_fall_delay.final_phase <<
  1115. MSDC_PAD_TUNE_DATRRDLY_S);
  1116. final_delay = final_fall_delay.final_phase;
  1117. }
  1118. if (mmc->selected_mode == MMC_HS_200 ||
  1119. mmc->selected_mode == UHS_SDR104)
  1120. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY_M,
  1121. host->hs200_write_int_delay <<
  1122. MSDC_PAD_TUNE_DATWRDLY_S);
  1123. dev_dbg(dev, "Final data pad delay: %x\n", final_delay);
  1124. return final_delay == 0xff ? -EIO : 0;
  1125. }
  1126. /*
  1127. * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
  1128. * together, which can save the tuning time.
  1129. */
  1130. static int msdc_tune_together(struct udevice *dev, u32 opcode)
  1131. {
  1132. struct msdc_plat *plat = dev_get_plat(dev);
  1133. struct msdc_host *host = dev_get_priv(dev);
  1134. struct mmc *mmc = &plat->mmc;
  1135. u32 rise_delay = 0, fall_delay = 0;
  1136. struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
  1137. u8 final_delay, final_maxlen;
  1138. int i, ret;
  1139. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
  1140. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
  1141. for (i = 0; i < PAD_DELAY_MAX; i++) {
  1142. msdc_set_cmd_delay(host, i);
  1143. msdc_set_data_delay(host, i);
  1144. ret = mmc_send_tuning(mmc, opcode, NULL);
  1145. if (!ret)
  1146. rise_delay |= (1 << i);
  1147. }
  1148. final_rise_delay = get_best_delay(dev, host, rise_delay);
  1149. if (final_rise_delay.maxlen >= 12 ||
  1150. (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
  1151. goto skip_fall;
  1152. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
  1153. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
  1154. for (i = 0; i < PAD_DELAY_MAX; i++) {
  1155. msdc_set_cmd_delay(host, i);
  1156. msdc_set_data_delay(host, i);
  1157. ret = mmc_send_tuning(mmc, opcode, NULL);
  1158. if (!ret)
  1159. fall_delay |= (1 << i);
  1160. }
  1161. final_fall_delay = get_best_delay(dev, host, fall_delay);
  1162. skip_fall:
  1163. final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
  1164. if (final_maxlen == final_rise_delay.maxlen) {
  1165. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
  1166. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
  1167. final_delay = final_rise_delay.final_phase;
  1168. } else {
  1169. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
  1170. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
  1171. final_delay = final_fall_delay.final_phase;
  1172. }
  1173. msdc_set_cmd_delay(host, final_delay);
  1174. msdc_set_data_delay(host, final_delay);
  1175. dev_info(dev, "Final pad delay: %x\n", final_delay);
  1176. return final_delay == 0xff ? -EIO : 0;
  1177. }
  1178. static int msdc_execute_tuning(struct udevice *dev, uint opcode)
  1179. {
  1180. struct msdc_plat *plat = dev_get_plat(dev);
  1181. struct msdc_host *host = dev_get_priv(dev);
  1182. struct mmc *mmc = &plat->mmc;
  1183. int ret = 0;
  1184. if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
  1185. ret = msdc_tune_together(dev, opcode);
  1186. if (ret == -EIO) {
  1187. dev_err(dev, "Tune fail!\n");
  1188. return ret;
  1189. }
  1190. if (mmc->selected_mode == MMC_HS_400) {
  1191. clrbits_le32(&host->base->msdc_iocon,
  1192. MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
  1193. clrsetbits_le32(&host->base->pad_tune,
  1194. MSDC_PAD_TUNE_DATRRDLY_M, 0);
  1195. writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
  1196. /* for hs400 mode it must be set to 0 */
  1197. clrbits_le32(&host->base->patch_bit2,
  1198. MSDC_PB2_CFGCRCSTS);
  1199. host->hs400_mode = true;
  1200. }
  1201. goto tune_done;
  1202. }
  1203. if (mmc->selected_mode == MMC_HS_400)
  1204. ret = hs400_tune_response(dev, opcode);
  1205. else
  1206. ret = msdc_tune_response(dev, opcode);
  1207. if (ret == -EIO) {
  1208. dev_err(dev, "Tune response fail!\n");
  1209. return ret;
  1210. }
  1211. if (mmc->selected_mode != MMC_HS_400) {
  1212. ret = msdc_tune_data(dev, opcode);
  1213. if (ret == -EIO) {
  1214. dev_err(dev, "Tune data fail!\n");
  1215. return ret;
  1216. }
  1217. }
  1218. tune_done:
  1219. host->saved_tune_para.iocon = readl(&host->base->msdc_iocon);
  1220. host->saved_tune_para.pad_tune = readl(&host->base->pad_tune);
  1221. host->saved_tune_para.pad_cmd_tune = readl(&host->base->pad_cmd_tune);
  1222. return ret;
  1223. }
  1224. #endif
  1225. static void msdc_init_hw(struct msdc_host *host)
  1226. {
  1227. u32 val;
  1228. void __iomem *tune_reg = &host->base->pad_tune;
  1229. void __iomem *rd_dly0_reg = &host->base->pad_tune0;
  1230. void __iomem *rd_dly1_reg = &host->base->pad_tune1;
  1231. if (host->dev_comp->pad_tune0) {
  1232. tune_reg = &host->base->pad_tune0;
  1233. rd_dly0_reg = &host->base->dat_rd_dly[0];
  1234. rd_dly1_reg = &host->base->dat_rd_dly[1];
  1235. }
  1236. /* Configure to MMC/SD mode, clock free running */
  1237. setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE);
  1238. /* Use PIO mode */
  1239. setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO);
  1240. /* Reset */
  1241. msdc_reset_hw(host);
  1242. /* Enable/disable hw card detection according to fdt option */
  1243. if (host->builtin_cd)
  1244. clrsetbits_le32(&host->base->msdc_ps,
  1245. MSDC_PS_CDDBCE_M,
  1246. (DEFAULT_CD_DEBOUNCE << MSDC_PS_CDDBCE_S) |
  1247. MSDC_PS_CDEN);
  1248. else
  1249. clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN);
  1250. /* Clear all interrupts */
  1251. val = readl(&host->base->msdc_int);
  1252. writel(val, &host->base->msdc_int);
  1253. /* Enable data & cmd interrupts */
  1254. writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten);
  1255. writel(0, tune_reg);
  1256. writel(0, &host->base->msdc_iocon);
  1257. if (host->r_smpl)
  1258. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
  1259. else
  1260. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
  1261. writel(0x403c0046, &host->base->patch_bit0);
  1262. writel(0xffff4089, &host->base->patch_bit1);
  1263. if (host->dev_comp->stop_clk_fix)
  1264. clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M,
  1265. 3 << MSDC_PB1_STOP_DLY_S);
  1266. if (host->dev_comp->busy_check)
  1267. clrbits_le32(&host->base->patch_bit1, (1 << 7));
  1268. setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL);
  1269. if (host->dev_comp->async_fifo) {
  1270. clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M,
  1271. 3 << MSDC_PB2_RESPWAIT_S);
  1272. if (host->dev_comp->enhance_rx) {
  1273. if (host->top_base)
  1274. setbits_le32(&host->top_base->emmc_top_control,
  1275. SDC_RX_ENH_EN);
  1276. else
  1277. setbits_le32(&host->base->sdc_adv_cfg0,
  1278. SDC_RX_ENHANCE_EN);
  1279. } else {
  1280. clrsetbits_le32(&host->base->patch_bit2,
  1281. MSDC_PB2_RESPSTSENSEL_M,
  1282. 2 << MSDC_PB2_RESPSTSENSEL_S);
  1283. clrsetbits_le32(&host->base->patch_bit2,
  1284. MSDC_PB2_CRCSTSENSEL_M,
  1285. 2 << MSDC_PB2_CRCSTSENSEL_S);
  1286. }
  1287. /* use async fifo to avoid tune internal delay */
  1288. clrbits_le32(&host->base->patch_bit2,
  1289. MSDC_PB2_CFGRESP);
  1290. clrbits_le32(&host->base->patch_bit2,
  1291. MSDC_PB2_CFGCRCSTS);
  1292. }
  1293. if (host->dev_comp->data_tune) {
  1294. setbits_le32(tune_reg,
  1295. MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
  1296. clrsetbits_le32(&host->base->patch_bit0,
  1297. MSDC_INT_DAT_LATCH_CK_SEL_M,
  1298. host->latch_ck <<
  1299. MSDC_INT_DAT_LATCH_CK_SEL_S);
  1300. } else {
  1301. /* choose clock tune */
  1302. setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
  1303. }
  1304. if (host->dev_comp->builtin_pad_ctrl) {
  1305. /* Set pins driving strength */
  1306. writel(MSDC_PAD_CTRL0_CLKPD | MSDC_PAD_CTRL0_CLKSMT |
  1307. MSDC_PAD_CTRL0_CLKIES | (4 << MSDC_PAD_CTRL0_CLKDRVN_S) |
  1308. (4 << MSDC_PAD_CTRL0_CLKDRVP_S), &host->base->pad_ctrl0);
  1309. writel(MSDC_PAD_CTRL1_CMDPU | MSDC_PAD_CTRL1_CMDSMT |
  1310. MSDC_PAD_CTRL1_CMDIES | (4 << MSDC_PAD_CTRL1_CMDDRVN_S) |
  1311. (4 << MSDC_PAD_CTRL1_CMDDRVP_S), &host->base->pad_ctrl1);
  1312. writel(MSDC_PAD_CTRL2_DATPU | MSDC_PAD_CTRL2_DATSMT |
  1313. MSDC_PAD_CTRL2_DATIES | (4 << MSDC_PAD_CTRL2_DATDRVN_S) |
  1314. (4 << MSDC_PAD_CTRL2_DATDRVP_S), &host->base->pad_ctrl2);
  1315. }
  1316. if (host->dev_comp->default_pad_dly) {
  1317. /* Default pad delay may be needed if tuning not enabled */
  1318. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CLKTDLY_M |
  1319. MSDC_PAD_TUNE_CMDRRDLY_M |
  1320. MSDC_PAD_TUNE_CMDRDLY_M |
  1321. MSDC_PAD_TUNE_DATRRDLY_M |
  1322. MSDC_PAD_TUNE_DATWRDLY_M,
  1323. (0x10 << MSDC_PAD_TUNE_CLKTDLY_S) |
  1324. (0x10 << MSDC_PAD_TUNE_CMDRRDLY_S) |
  1325. (0x10 << MSDC_PAD_TUNE_CMDRDLY_S) |
  1326. (0x10 << MSDC_PAD_TUNE_DATRRDLY_S) |
  1327. (0x10 << MSDC_PAD_TUNE_DATWRDLY_S));
  1328. writel((0x10 << MSDC_PAD_TUNE0_DAT0RDDLY_S) |
  1329. (0x10 << MSDC_PAD_TUNE0_DAT1RDDLY_S) |
  1330. (0x10 << MSDC_PAD_TUNE0_DAT2RDDLY_S) |
  1331. (0x10 << MSDC_PAD_TUNE0_DAT3RDDLY_S),
  1332. rd_dly0_reg);
  1333. writel((0x10 << MSDC_PAD_TUNE1_DAT4RDDLY_S) |
  1334. (0x10 << MSDC_PAD_TUNE1_DAT5RDDLY_S) |
  1335. (0x10 << MSDC_PAD_TUNE1_DAT6RDDLY_S) |
  1336. (0x10 << MSDC_PAD_TUNE1_DAT7RDDLY_S),
  1337. rd_dly1_reg);
  1338. }
  1339. /* Configure to enable SDIO mode otherwise sdio cmd5 won't work */
  1340. setbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIO);
  1341. /* disable detecting SDIO device interrupt function */
  1342. clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE);
  1343. /* Configure to default data timeout */
  1344. clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
  1345. 3 << SDC_CFG_DTOC_S);
  1346. if (host->dev_comp->stop_clk_fix) {
  1347. clrbits_le32(&host->base->sdc_fifo_cfg,
  1348. SDC_FIFO_CFG_WRVALIDSEL);
  1349. clrbits_le32(&host->base->sdc_fifo_cfg,
  1350. SDC_FIFO_CFG_RDVALIDSEL);
  1351. }
  1352. host->def_tune_para.iocon = readl(&host->base->msdc_iocon);
  1353. host->def_tune_para.pad_tune = readl(&host->base->pad_tune);
  1354. }
  1355. static void msdc_ungate_clock(struct msdc_host *host)
  1356. {
  1357. clk_enable(&host->src_clk);
  1358. clk_enable(&host->h_clk);
  1359. if (host->src_clk_cg.dev)
  1360. clk_enable(&host->src_clk_cg);
  1361. }
  1362. static int msdc_drv_probe(struct udevice *dev)
  1363. {
  1364. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  1365. struct msdc_plat *plat = dev_get_plat(dev);
  1366. struct msdc_host *host = dev_get_priv(dev);
  1367. struct mmc_config *cfg = &plat->cfg;
  1368. cfg->name = dev->name;
  1369. host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev);
  1370. host->src_clk_freq = clk_get_rate(&host->src_clk);
  1371. if (host->dev_comp->clk_div_bits == 8)
  1372. cfg->f_min = host->src_clk_freq / (4 * 255);
  1373. else
  1374. cfg->f_min = host->src_clk_freq / (4 * 4095);
  1375. if (cfg->f_min < MIN_BUS_CLK)
  1376. cfg->f_min = MIN_BUS_CLK;
  1377. if (cfg->f_max < cfg->f_min || cfg->f_max > host->src_clk_freq)
  1378. cfg->f_max = host->src_clk_freq;
  1379. cfg->b_max = 1024;
  1380. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  1381. host->mmc = &plat->mmc;
  1382. host->timeout_ns = 100000000;
  1383. host->timeout_clks = 3 * (1 << SCLK_CYCLES_SHIFT);
  1384. #ifdef CONFIG_PINCTRL
  1385. pinctrl_select_state(dev, "default");
  1386. #endif
  1387. msdc_ungate_clock(host);
  1388. msdc_init_hw(host);
  1389. upriv->mmc = &plat->mmc;
  1390. return 0;
  1391. }
  1392. static int msdc_of_to_plat(struct udevice *dev)
  1393. {
  1394. struct msdc_plat *plat = dev_get_plat(dev);
  1395. struct msdc_host *host = dev_get_priv(dev);
  1396. struct mmc_config *cfg = &plat->cfg;
  1397. fdt_addr_t base, top_base;
  1398. int ret;
  1399. base = dev_read_addr(dev);
  1400. if (base == FDT_ADDR_T_NONE)
  1401. return -EINVAL;
  1402. host->base = map_sysmem(base, 0);
  1403. top_base = dev_read_addr_index(dev, 1);
  1404. if (top_base == FDT_ADDR_T_NONE)
  1405. host->top_base = NULL;
  1406. else
  1407. host->top_base = map_sysmem(top_base, 0);
  1408. ret = mmc_of_parse(dev, cfg);
  1409. if (ret)
  1410. return ret;
  1411. ret = clk_get_by_name(dev, "source", &host->src_clk);
  1412. if (ret < 0)
  1413. return ret;
  1414. ret = clk_get_by_name(dev, "hclk", &host->h_clk);
  1415. if (ret < 0)
  1416. return ret;
  1417. clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
  1418. #if CONFIG_IS_ENABLED(DM_GPIO)
  1419. gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
  1420. gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
  1421. #endif
  1422. host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0);
  1423. host->hs200_cmd_int_delay =
  1424. dev_read_u32_default(dev, "cmd_int_delay", 0);
  1425. host->hs200_write_int_delay =
  1426. dev_read_u32_default(dev, "write_int_delay", 0);
  1427. host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0);
  1428. host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0);
  1429. host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0);
  1430. host->cd_active_high = dev_read_bool(dev, "cd-active-high");
  1431. return 0;
  1432. }
  1433. static int msdc_drv_bind(struct udevice *dev)
  1434. {
  1435. struct msdc_plat *plat = dev_get_plat(dev);
  1436. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  1437. }
  1438. static const struct dm_mmc_ops msdc_ops = {
  1439. .send_cmd = msdc_ops_send_cmd,
  1440. .set_ios = msdc_ops_set_ios,
  1441. .get_cd = msdc_ops_get_cd,
  1442. .get_wp = msdc_ops_get_wp,
  1443. #ifdef MMC_SUPPORTS_TUNING
  1444. .execute_tuning = msdc_execute_tuning,
  1445. #endif
  1446. };
  1447. static const struct msdc_compatible mt7620_compat = {
  1448. .clk_div_bits = 8,
  1449. .pad_tune0 = false,
  1450. .async_fifo = false,
  1451. .data_tune = false,
  1452. .busy_check = false,
  1453. .stop_clk_fix = false,
  1454. .enhance_rx = false,
  1455. .builtin_pad_ctrl = true,
  1456. .default_pad_dly = true,
  1457. };
  1458. static const struct msdc_compatible mt7622_compat = {
  1459. .clk_div_bits = 12,
  1460. .pad_tune0 = true,
  1461. .async_fifo = true,
  1462. .data_tune = true,
  1463. .busy_check = true,
  1464. .stop_clk_fix = true,
  1465. };
  1466. static const struct msdc_compatible mt7623_compat = {
  1467. .clk_div_bits = 12,
  1468. .pad_tune0 = true,
  1469. .async_fifo = true,
  1470. .data_tune = true,
  1471. .busy_check = false,
  1472. .stop_clk_fix = false,
  1473. .enhance_rx = false
  1474. };
  1475. static const struct msdc_compatible mt8512_compat = {
  1476. .clk_div_bits = 12,
  1477. .pad_tune0 = true,
  1478. .async_fifo = true,
  1479. .data_tune = true,
  1480. .busy_check = true,
  1481. .stop_clk_fix = true,
  1482. };
  1483. static const struct msdc_compatible mt8516_compat = {
  1484. .clk_div_bits = 12,
  1485. .pad_tune0 = true,
  1486. .async_fifo = true,
  1487. .data_tune = true,
  1488. .busy_check = true,
  1489. .stop_clk_fix = true,
  1490. };
  1491. static const struct msdc_compatible mt8183_compat = {
  1492. .clk_div_bits = 12,
  1493. .pad_tune0 = true,
  1494. .async_fifo = true,
  1495. .data_tune = true,
  1496. .busy_check = true,
  1497. .stop_clk_fix = true,
  1498. };
  1499. static const struct udevice_id msdc_ids[] = {
  1500. { .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat },
  1501. { .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat },
  1502. { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
  1503. { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat },
  1504. { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
  1505. { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },
  1506. {}
  1507. };
  1508. U_BOOT_DRIVER(mtk_sd_drv) = {
  1509. .name = "mtk_sd",
  1510. .id = UCLASS_MMC,
  1511. .of_match = msdc_ids,
  1512. .of_to_plat = msdc_of_to_plat,
  1513. .bind = msdc_drv_bind,
  1514. .probe = msdc_drv_probe,
  1515. .ops = &msdc_ops,
  1516. .plat_auto = sizeof(struct msdc_plat),
  1517. .priv_auto = sizeof(struct msdc_host),
  1518. };