msm_sdhci.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Qualcomm SDHCI driver - SD/eMMC controller
  4. *
  5. * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
  6. *
  7. * Based on Linux driver
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <malloc.h>
  13. #include <sdhci.h>
  14. #include <wait_bit.h>
  15. #include <asm/global_data.h>
  16. #include <asm/io.h>
  17. #include <linux/bitops.h>
  18. /* Non-standard registers needed for SDHCI startup */
  19. #define SDCC_MCI_POWER 0x0
  20. #define SDCC_MCI_POWER_SW_RST BIT(7)
  21. /* This is undocumented register */
  22. #define SDCC_MCI_VERSION 0x50
  23. #define SDCC_MCI_VERSION_MAJOR_SHIFT 28
  24. #define SDCC_MCI_VERSION_MAJOR_MASK (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT)
  25. #define SDCC_MCI_VERSION_MINOR_MASK 0xff
  26. #define SDCC_MCI_STATUS2 0x6C
  27. #define SDCC_MCI_STATUS2_MCI_ACT 0x1
  28. #define SDCC_MCI_HC_MODE 0x78
  29. /* Offset to SDHCI registers */
  30. #define SDCC_SDHCI_OFFSET 0x900
  31. /* Non standard (?) SDHCI register */
  32. #define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c
  33. struct msm_sdhc_plat {
  34. struct mmc_config cfg;
  35. struct mmc mmc;
  36. };
  37. struct msm_sdhc {
  38. struct sdhci_host host;
  39. void *base;
  40. };
  41. DECLARE_GLOBAL_DATA_PTR;
  42. static int msm_sdc_clk_init(struct udevice *dev)
  43. {
  44. int node = dev_of_offset(dev);
  45. uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency",
  46. 400000);
  47. uint clkd[2]; /* clk_id and clk_no */
  48. int clk_offset;
  49. struct udevice *clk_dev;
  50. struct clk clk;
  51. int ret;
  52. ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2);
  53. if (ret)
  54. return ret;
  55. clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
  56. if (clk_offset < 0)
  57. return clk_offset;
  58. ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
  59. if (ret)
  60. return ret;
  61. clk.id = clkd[1];
  62. ret = clk_request(clk_dev, &clk);
  63. if (ret < 0)
  64. return ret;
  65. ret = clk_set_rate(&clk, clk_rate);
  66. clk_free(&clk);
  67. if (ret < 0)
  68. return ret;
  69. return 0;
  70. }
  71. static int msm_sdc_probe(struct udevice *dev)
  72. {
  73. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  74. struct msm_sdhc_plat *plat = dev_get_plat(dev);
  75. struct msm_sdhc *prv = dev_get_priv(dev);
  76. struct sdhci_host *host = &prv->host;
  77. u32 core_version, core_minor, core_major;
  78. u32 caps;
  79. int ret;
  80. host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
  81. host->max_clk = 0;
  82. /* Init clocks */
  83. ret = msm_sdc_clk_init(dev);
  84. if (ret)
  85. return ret;
  86. /* Reset the core and Enable SDHC mode */
  87. writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST,
  88. prv->base + SDCC_MCI_POWER);
  89. /* Wait for reset to be written to register */
  90. if (wait_for_bit_le32(prv->base + SDCC_MCI_STATUS2,
  91. SDCC_MCI_STATUS2_MCI_ACT, false, 10, false)) {
  92. printf("msm_sdhci: reset request failed\n");
  93. return -EIO;
  94. }
  95. /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
  96. if (wait_for_bit_le32(prv->base + SDCC_MCI_POWER,
  97. SDCC_MCI_POWER_SW_RST, false, 2, false)) {
  98. printf("msm_sdhci: stuck in reset\n");
  99. return -ETIMEDOUT;
  100. }
  101. /* Enable host-controller mode */
  102. writel(1, prv->base + SDCC_MCI_HC_MODE);
  103. core_version = readl(prv->base + SDCC_MCI_VERSION);
  104. core_major = (core_version & SDCC_MCI_VERSION_MAJOR_MASK);
  105. core_major >>= SDCC_MCI_VERSION_MAJOR_SHIFT;
  106. core_minor = core_version & SDCC_MCI_VERSION_MINOR_MASK;
  107. /*
  108. * Support for some capabilities is not advertised by newer
  109. * controller versions and must be explicitly enabled.
  110. */
  111. if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
  112. caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  113. caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
  114. writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0);
  115. }
  116. ret = mmc_of_parse(dev, &plat->cfg);
  117. if (ret)
  118. return ret;
  119. host->mmc = &plat->mmc;
  120. host->mmc->dev = dev;
  121. ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
  122. if (ret)
  123. return ret;
  124. host->mmc->priv = &prv->host;
  125. upriv->mmc = host->mmc;
  126. return sdhci_probe(dev);
  127. }
  128. static int msm_sdc_remove(struct udevice *dev)
  129. {
  130. struct msm_sdhc *priv = dev_get_priv(dev);
  131. /* Disable host-controller mode */
  132. writel(0, priv->base + SDCC_MCI_HC_MODE);
  133. return 0;
  134. }
  135. static int msm_of_to_plat(struct udevice *dev)
  136. {
  137. struct udevice *parent = dev->parent;
  138. struct msm_sdhc *priv = dev_get_priv(dev);
  139. struct sdhci_host *host = &priv->host;
  140. int node = dev_of_offset(dev);
  141. host->name = strdup(dev->name);
  142. host->ioaddr = dev_read_addr_ptr(dev);
  143. host->bus_width = fdtdec_get_int(gd->fdt_blob, node, "bus-width", 4);
  144. host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0);
  145. priv->base = (void *)fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
  146. dev_of_offset(parent), node, "reg", 1, NULL, false);
  147. if (priv->base == (void *)FDT_ADDR_T_NONE ||
  148. host->ioaddr == (void *)FDT_ADDR_T_NONE)
  149. return -EINVAL;
  150. return 0;
  151. }
  152. static int msm_sdc_bind(struct udevice *dev)
  153. {
  154. struct msm_sdhc_plat *plat = dev_get_plat(dev);
  155. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  156. }
  157. static const struct udevice_id msm_mmc_ids[] = {
  158. { .compatible = "qcom,sdhci-msm-v4" },
  159. { }
  160. };
  161. U_BOOT_DRIVER(msm_sdc_drv) = {
  162. .name = "msm_sdc",
  163. .id = UCLASS_MMC,
  164. .of_match = msm_mmc_ids,
  165. .of_to_plat = msm_of_to_plat,
  166. .ops = &sdhci_ops,
  167. .bind = msm_sdc_bind,
  168. .probe = msm_sdc_probe,
  169. .remove = msm_sdc_remove,
  170. .priv_auto = sizeof(struct msm_sdhc),
  171. .plat_auto = sizeof(struct msm_sdhc_plat),
  172. };