mmc.c 70 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008, Freescale Semiconductor, Inc
  4. * Copyright 2020 NXP
  5. * Andy Fleming
  6. *
  7. * Based vaguely on the Linux code
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <blk.h>
  12. #include <command.h>
  13. #include <dm.h>
  14. #include <log.h>
  15. #include <dm/device-internal.h>
  16. #include <errno.h>
  17. #include <mmc.h>
  18. #include <part.h>
  19. #include <linux/bitops.h>
  20. #include <linux/delay.h>
  21. #include <power/regulator.h>
  22. #include <malloc.h>
  23. #include <memalign.h>
  24. #include <linux/list.h>
  25. #include <div64.h>
  26. #include "mmc_private.h"
  27. #define DEFAULT_CMD6_TIMEOUT_MS 500
  28. static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
  29. #if !CONFIG_IS_ENABLED(DM_MMC)
  30. static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
  31. {
  32. return -ENOSYS;
  33. }
  34. __weak int board_mmc_getwp(struct mmc *mmc)
  35. {
  36. return -1;
  37. }
  38. int mmc_getwp(struct mmc *mmc)
  39. {
  40. int wp;
  41. wp = board_mmc_getwp(mmc);
  42. if (wp < 0) {
  43. if (mmc->cfg->ops->getwp)
  44. wp = mmc->cfg->ops->getwp(mmc);
  45. else
  46. wp = 0;
  47. }
  48. return wp;
  49. }
  50. __weak int board_mmc_getcd(struct mmc *mmc)
  51. {
  52. return -1;
  53. }
  54. #endif
  55. #ifdef CONFIG_MMC_TRACE
  56. void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
  57. {
  58. printf("CMD_SEND:%d\n", cmd->cmdidx);
  59. printf("\t\tARG\t\t\t 0x%08x\n", cmd->cmdarg);
  60. }
  61. void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
  62. {
  63. int i;
  64. u8 *ptr;
  65. if (ret) {
  66. printf("\t\tRET\t\t\t %d\n", ret);
  67. } else {
  68. switch (cmd->resp_type) {
  69. case MMC_RSP_NONE:
  70. printf("\t\tMMC_RSP_NONE\n");
  71. break;
  72. case MMC_RSP_R1:
  73. printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n",
  74. cmd->response[0]);
  75. break;
  76. case MMC_RSP_R1b:
  77. printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n",
  78. cmd->response[0]);
  79. break;
  80. case MMC_RSP_R2:
  81. printf("\t\tMMC_RSP_R2\t\t 0x%08x \n",
  82. cmd->response[0]);
  83. printf("\t\t \t\t 0x%08x \n",
  84. cmd->response[1]);
  85. printf("\t\t \t\t 0x%08x \n",
  86. cmd->response[2]);
  87. printf("\t\t \t\t 0x%08x \n",
  88. cmd->response[3]);
  89. printf("\n");
  90. printf("\t\t\t\t\tDUMPING DATA\n");
  91. for (i = 0; i < 4; i++) {
  92. int j;
  93. printf("\t\t\t\t\t%03d - ", i*4);
  94. ptr = (u8 *)&cmd->response[i];
  95. ptr += 3;
  96. for (j = 0; j < 4; j++)
  97. printf("%02x ", *ptr--);
  98. printf("\n");
  99. }
  100. break;
  101. case MMC_RSP_R3:
  102. printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n",
  103. cmd->response[0]);
  104. break;
  105. default:
  106. printf("\t\tERROR MMC rsp not supported\n");
  107. break;
  108. }
  109. }
  110. }
  111. void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
  112. {
  113. int status;
  114. status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
  115. printf("CURR STATE:%d\n", status);
  116. }
  117. #endif
  118. #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
  119. const char *mmc_mode_name(enum bus_mode mode)
  120. {
  121. static const char *const names[] = {
  122. [MMC_LEGACY] = "MMC legacy",
  123. [MMC_HS] = "MMC High Speed (26MHz)",
  124. [SD_HS] = "SD High Speed (50MHz)",
  125. [UHS_SDR12] = "UHS SDR12 (25MHz)",
  126. [UHS_SDR25] = "UHS SDR25 (50MHz)",
  127. [UHS_SDR50] = "UHS SDR50 (100MHz)",
  128. [UHS_SDR104] = "UHS SDR104 (208MHz)",
  129. [UHS_DDR50] = "UHS DDR50 (50MHz)",
  130. [MMC_HS_52] = "MMC High Speed (52MHz)",
  131. [MMC_DDR_52] = "MMC DDR52 (52MHz)",
  132. [MMC_HS_200] = "HS200 (200MHz)",
  133. [MMC_HS_400] = "HS400 (200MHz)",
  134. [MMC_HS_400_ES] = "HS400ES (200MHz)",
  135. };
  136. if (mode >= MMC_MODES_END)
  137. return "Unknown mode";
  138. else
  139. return names[mode];
  140. }
  141. #endif
  142. static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
  143. {
  144. static const int freqs[] = {
  145. [MMC_LEGACY] = 25000000,
  146. [MMC_HS] = 26000000,
  147. [SD_HS] = 50000000,
  148. [MMC_HS_52] = 52000000,
  149. [MMC_DDR_52] = 52000000,
  150. [UHS_SDR12] = 25000000,
  151. [UHS_SDR25] = 50000000,
  152. [UHS_SDR50] = 100000000,
  153. [UHS_DDR50] = 50000000,
  154. [UHS_SDR104] = 208000000,
  155. [MMC_HS_200] = 200000000,
  156. [MMC_HS_400] = 200000000,
  157. [MMC_HS_400_ES] = 200000000,
  158. };
  159. if (mode == MMC_LEGACY)
  160. return mmc->legacy_speed;
  161. else if (mode >= MMC_MODES_END)
  162. return 0;
  163. else
  164. return freqs[mode];
  165. }
  166. static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
  167. {
  168. mmc->selected_mode = mode;
  169. mmc->tran_speed = mmc_mode2freq(mmc, mode);
  170. mmc->ddr_mode = mmc_is_mode_ddr(mode);
  171. pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
  172. mmc->tran_speed / 1000000);
  173. return 0;
  174. }
  175. #if !CONFIG_IS_ENABLED(DM_MMC)
  176. int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
  177. {
  178. int ret;
  179. mmmc_trace_before_send(mmc, cmd);
  180. ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
  181. mmmc_trace_after_send(mmc, cmd, ret);
  182. return ret;
  183. }
  184. #endif
  185. /**
  186. * mmc_send_cmd_retry() - send a command to the mmc device, retrying on error
  187. *
  188. * @dev: device to receive the command
  189. * @cmd: command to send
  190. * @data: additional data to send/receive
  191. * @retries: how many times to retry; mmc_send_cmd is always called at least
  192. * once
  193. * @return 0 if ok, -ve on error
  194. */
  195. static int mmc_send_cmd_retry(struct mmc *mmc, struct mmc_cmd *cmd,
  196. struct mmc_data *data, uint retries)
  197. {
  198. int ret;
  199. do {
  200. ret = mmc_send_cmd(mmc, cmd, data);
  201. } while (ret && retries--);
  202. return ret;
  203. }
  204. /**
  205. * mmc_send_cmd_quirks() - send a command to the mmc device, retrying if a
  206. * specific quirk is enabled
  207. *
  208. * @dev: device to receive the command
  209. * @cmd: command to send
  210. * @data: additional data to send/receive
  211. * @quirk: retry only if this quirk is enabled
  212. * @retries: how many times to retry; mmc_send_cmd is always called at least
  213. * once
  214. * @return 0 if ok, -ve on error
  215. */
  216. static int mmc_send_cmd_quirks(struct mmc *mmc, struct mmc_cmd *cmd,
  217. struct mmc_data *data, u32 quirk, uint retries)
  218. {
  219. if (CONFIG_IS_ENABLED(MMC_QUIRKS) && mmc->quirks & quirk)
  220. return mmc_send_cmd_retry(mmc, cmd, data, retries);
  221. else
  222. return mmc_send_cmd(mmc, cmd, data);
  223. }
  224. int mmc_send_status(struct mmc *mmc, unsigned int *status)
  225. {
  226. struct mmc_cmd cmd;
  227. int ret;
  228. cmd.cmdidx = MMC_CMD_SEND_STATUS;
  229. cmd.resp_type = MMC_RSP_R1;
  230. if (!mmc_host_is_spi(mmc))
  231. cmd.cmdarg = mmc->rca << 16;
  232. ret = mmc_send_cmd_retry(mmc, &cmd, NULL, 4);
  233. mmc_trace_state(mmc, &cmd);
  234. if (!ret)
  235. *status = cmd.response[0];
  236. return ret;
  237. }
  238. int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
  239. {
  240. unsigned int status;
  241. int err;
  242. err = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
  243. if (err != -ENOSYS)
  244. return err;
  245. while (1) {
  246. err = mmc_send_status(mmc, &status);
  247. if (err)
  248. return err;
  249. if ((status & MMC_STATUS_RDY_FOR_DATA) &&
  250. (status & MMC_STATUS_CURR_STATE) !=
  251. MMC_STATE_PRG)
  252. break;
  253. if (status & MMC_STATUS_MASK) {
  254. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  255. pr_err("Status Error: 0x%08x\n", status);
  256. #endif
  257. return -ECOMM;
  258. }
  259. if (timeout_ms-- <= 0)
  260. break;
  261. udelay(1000);
  262. }
  263. if (timeout_ms <= 0) {
  264. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  265. pr_err("Timeout waiting card ready\n");
  266. #endif
  267. return -ETIMEDOUT;
  268. }
  269. return 0;
  270. }
  271. int mmc_set_blocklen(struct mmc *mmc, int len)
  272. {
  273. struct mmc_cmd cmd;
  274. if (mmc->ddr_mode)
  275. return 0;
  276. cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
  277. cmd.resp_type = MMC_RSP_R1;
  278. cmd.cmdarg = len;
  279. return mmc_send_cmd_quirks(mmc, &cmd, NULL,
  280. MMC_QUIRK_RETRY_SET_BLOCKLEN, 4);
  281. }
  282. #ifdef MMC_SUPPORTS_TUNING
  283. static const u8 tuning_blk_pattern_4bit[] = {
  284. 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
  285. 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
  286. 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
  287. 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
  288. 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
  289. 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
  290. 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
  291. 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
  292. };
  293. static const u8 tuning_blk_pattern_8bit[] = {
  294. 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
  295. 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
  296. 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
  297. 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
  298. 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
  299. 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
  300. 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
  301. 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
  302. 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
  303. 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
  304. 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
  305. 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
  306. 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
  307. 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
  308. 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
  309. 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
  310. };
  311. int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
  312. {
  313. struct mmc_cmd cmd;
  314. struct mmc_data data;
  315. const u8 *tuning_block_pattern;
  316. int size, err;
  317. if (mmc->bus_width == 8) {
  318. tuning_block_pattern = tuning_blk_pattern_8bit;
  319. size = sizeof(tuning_blk_pattern_8bit);
  320. } else if (mmc->bus_width == 4) {
  321. tuning_block_pattern = tuning_blk_pattern_4bit;
  322. size = sizeof(tuning_blk_pattern_4bit);
  323. } else {
  324. return -EINVAL;
  325. }
  326. ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
  327. cmd.cmdidx = opcode;
  328. cmd.cmdarg = 0;
  329. cmd.resp_type = MMC_RSP_R1;
  330. data.dest = (void *)data_buf;
  331. data.blocks = 1;
  332. data.blocksize = size;
  333. data.flags = MMC_DATA_READ;
  334. err = mmc_send_cmd(mmc, &cmd, &data);
  335. if (err)
  336. return err;
  337. if (memcmp(data_buf, tuning_block_pattern, size))
  338. return -EIO;
  339. return 0;
  340. }
  341. #endif
  342. static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
  343. lbaint_t blkcnt)
  344. {
  345. struct mmc_cmd cmd;
  346. struct mmc_data data;
  347. if (blkcnt > 1)
  348. cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
  349. else
  350. cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
  351. if (mmc->high_capacity)
  352. cmd.cmdarg = start;
  353. else
  354. cmd.cmdarg = start * mmc->read_bl_len;
  355. cmd.resp_type = MMC_RSP_R1;
  356. data.dest = dst;
  357. data.blocks = blkcnt;
  358. data.blocksize = mmc->read_bl_len;
  359. data.flags = MMC_DATA_READ;
  360. if (mmc_send_cmd(mmc, &cmd, &data))
  361. return 0;
  362. if (blkcnt > 1) {
  363. cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
  364. cmd.cmdarg = 0;
  365. cmd.resp_type = MMC_RSP_R1b;
  366. if (mmc_send_cmd(mmc, &cmd, NULL)) {
  367. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  368. pr_err("mmc fail to send stop cmd\n");
  369. #endif
  370. return 0;
  371. }
  372. }
  373. return blkcnt;
  374. }
  375. #if !CONFIG_IS_ENABLED(DM_MMC)
  376. static int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt)
  377. {
  378. if (mmc->cfg->ops->get_b_max)
  379. return mmc->cfg->ops->get_b_max(mmc, dst, blkcnt);
  380. else
  381. return mmc->cfg->b_max;
  382. }
  383. #endif
  384. #if CONFIG_IS_ENABLED(BLK)
  385. ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
  386. #else
  387. ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
  388. void *dst)
  389. #endif
  390. {
  391. #if CONFIG_IS_ENABLED(BLK)
  392. struct blk_desc *block_dev = dev_get_uclass_plat(dev);
  393. #endif
  394. int dev_num = block_dev->devnum;
  395. int err;
  396. lbaint_t cur, blocks_todo = blkcnt;
  397. uint b_max;
  398. if (blkcnt == 0)
  399. return 0;
  400. struct mmc *mmc = find_mmc_device(dev_num);
  401. if (!mmc)
  402. return 0;
  403. if (CONFIG_IS_ENABLED(MMC_TINY))
  404. err = mmc_switch_part(mmc, block_dev->hwpart);
  405. else
  406. err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
  407. if (err < 0)
  408. return 0;
  409. if ((start + blkcnt) > block_dev->lba) {
  410. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  411. pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
  412. start + blkcnt, block_dev->lba);
  413. #endif
  414. return 0;
  415. }
  416. if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
  417. pr_debug("%s: Failed to set blocklen\n", __func__);
  418. return 0;
  419. }
  420. b_max = mmc_get_b_max(mmc, dst, blkcnt);
  421. do {
  422. cur = (blocks_todo > b_max) ? b_max : blocks_todo;
  423. if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
  424. pr_debug("%s: Failed to read blocks\n", __func__);
  425. return 0;
  426. }
  427. blocks_todo -= cur;
  428. start += cur;
  429. dst += cur * mmc->read_bl_len;
  430. } while (blocks_todo > 0);
  431. return blkcnt;
  432. }
  433. static int mmc_go_idle(struct mmc *mmc)
  434. {
  435. struct mmc_cmd cmd;
  436. int err;
  437. udelay(1000);
  438. cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
  439. cmd.cmdarg = 0;
  440. cmd.resp_type = MMC_RSP_NONE;
  441. err = mmc_send_cmd(mmc, &cmd, NULL);
  442. if (err)
  443. return err;
  444. udelay(2000);
  445. return 0;
  446. }
  447. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  448. static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
  449. {
  450. struct mmc_cmd cmd;
  451. int err = 0;
  452. /*
  453. * Send CMD11 only if the request is to switch the card to
  454. * 1.8V signalling.
  455. */
  456. if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
  457. return mmc_set_signal_voltage(mmc, signal_voltage);
  458. cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
  459. cmd.cmdarg = 0;
  460. cmd.resp_type = MMC_RSP_R1;
  461. err = mmc_send_cmd(mmc, &cmd, NULL);
  462. if (err)
  463. return err;
  464. if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
  465. return -EIO;
  466. /*
  467. * The card should drive cmd and dat[0:3] low immediately
  468. * after the response of cmd11, but wait 100 us to be sure
  469. */
  470. err = mmc_wait_dat0(mmc, 0, 100);
  471. if (err == -ENOSYS)
  472. udelay(100);
  473. else if (err)
  474. return -ETIMEDOUT;
  475. /*
  476. * During a signal voltage level switch, the clock must be gated
  477. * for 5 ms according to the SD spec
  478. */
  479. mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
  480. err = mmc_set_signal_voltage(mmc, signal_voltage);
  481. if (err)
  482. return err;
  483. /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
  484. mdelay(10);
  485. mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
  486. /*
  487. * Failure to switch is indicated by the card holding
  488. * dat[0:3] low. Wait for at least 1 ms according to spec
  489. */
  490. err = mmc_wait_dat0(mmc, 1, 1000);
  491. if (err == -ENOSYS)
  492. udelay(1000);
  493. else if (err)
  494. return -ETIMEDOUT;
  495. return 0;
  496. }
  497. #endif
  498. static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
  499. {
  500. int timeout = 1000;
  501. int err;
  502. struct mmc_cmd cmd;
  503. while (1) {
  504. cmd.cmdidx = MMC_CMD_APP_CMD;
  505. cmd.resp_type = MMC_RSP_R1;
  506. cmd.cmdarg = 0;
  507. err = mmc_send_cmd(mmc, &cmd, NULL);
  508. if (err)
  509. return err;
  510. cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
  511. cmd.resp_type = MMC_RSP_R3;
  512. /*
  513. * Most cards do not answer if some reserved bits
  514. * in the ocr are set. However, Some controller
  515. * can set bit 7 (reserved for low voltages), but
  516. * how to manage low voltages SD card is not yet
  517. * specified.
  518. */
  519. cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
  520. (mmc->cfg->voltages & 0xff8000);
  521. if (mmc->version == SD_VERSION_2)
  522. cmd.cmdarg |= OCR_HCS;
  523. if (uhs_en)
  524. cmd.cmdarg |= OCR_S18R;
  525. err = mmc_send_cmd(mmc, &cmd, NULL);
  526. if (err)
  527. return err;
  528. if (cmd.response[0] & OCR_BUSY)
  529. break;
  530. if (timeout-- <= 0)
  531. return -EOPNOTSUPP;
  532. udelay(1000);
  533. }
  534. if (mmc->version != SD_VERSION_2)
  535. mmc->version = SD_VERSION_1_0;
  536. if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
  537. cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
  538. cmd.resp_type = MMC_RSP_R3;
  539. cmd.cmdarg = 0;
  540. err = mmc_send_cmd(mmc, &cmd, NULL);
  541. if (err)
  542. return err;
  543. }
  544. mmc->ocr = cmd.response[0];
  545. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  546. if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
  547. == 0x41000000) {
  548. err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
  549. if (err)
  550. return err;
  551. }
  552. #endif
  553. mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
  554. mmc->rca = 0;
  555. return 0;
  556. }
  557. static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
  558. {
  559. struct mmc_cmd cmd;
  560. int err;
  561. cmd.cmdidx = MMC_CMD_SEND_OP_COND;
  562. cmd.resp_type = MMC_RSP_R3;
  563. cmd.cmdarg = 0;
  564. if (use_arg && !mmc_host_is_spi(mmc))
  565. cmd.cmdarg = OCR_HCS |
  566. (mmc->cfg->voltages &
  567. (mmc->ocr & OCR_VOLTAGE_MASK)) |
  568. (mmc->ocr & OCR_ACCESS_MODE);
  569. err = mmc_send_cmd(mmc, &cmd, NULL);
  570. if (err)
  571. return err;
  572. mmc->ocr = cmd.response[0];
  573. return 0;
  574. }
  575. static int mmc_send_op_cond(struct mmc *mmc)
  576. {
  577. int err, i;
  578. int timeout = 1000;
  579. uint start;
  580. /* Some cards seem to need this */
  581. mmc_go_idle(mmc);
  582. start = get_timer(0);
  583. /* Asking to the card its capabilities */
  584. for (i = 0; ; i++) {
  585. err = mmc_send_op_cond_iter(mmc, i != 0);
  586. if (err)
  587. return err;
  588. /* exit if not busy (flag seems to be inverted) */
  589. if (mmc->ocr & OCR_BUSY)
  590. break;
  591. if (get_timer(start) > timeout)
  592. return -ETIMEDOUT;
  593. udelay(100);
  594. }
  595. mmc->op_cond_pending = 1;
  596. return 0;
  597. }
  598. static int mmc_complete_op_cond(struct mmc *mmc)
  599. {
  600. struct mmc_cmd cmd;
  601. int timeout = 1000;
  602. ulong start;
  603. int err;
  604. mmc->op_cond_pending = 0;
  605. if (!(mmc->ocr & OCR_BUSY)) {
  606. /* Some cards seem to need this */
  607. mmc_go_idle(mmc);
  608. start = get_timer(0);
  609. while (1) {
  610. err = mmc_send_op_cond_iter(mmc, 1);
  611. if (err)
  612. return err;
  613. if (mmc->ocr & OCR_BUSY)
  614. break;
  615. if (get_timer(start) > timeout)
  616. return -EOPNOTSUPP;
  617. udelay(100);
  618. }
  619. }
  620. if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
  621. cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
  622. cmd.resp_type = MMC_RSP_R3;
  623. cmd.cmdarg = 0;
  624. err = mmc_send_cmd(mmc, &cmd, NULL);
  625. if (err)
  626. return err;
  627. mmc->ocr = cmd.response[0];
  628. }
  629. mmc->version = MMC_VERSION_UNKNOWN;
  630. mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
  631. mmc->rca = 1;
  632. return 0;
  633. }
  634. int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
  635. {
  636. struct mmc_cmd cmd;
  637. struct mmc_data data;
  638. int err;
  639. /* Get the Card Status Register */
  640. cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
  641. cmd.resp_type = MMC_RSP_R1;
  642. cmd.cmdarg = 0;
  643. data.dest = (char *)ext_csd;
  644. data.blocks = 1;
  645. data.blocksize = MMC_MAX_BLOCK_LEN;
  646. data.flags = MMC_DATA_READ;
  647. err = mmc_send_cmd(mmc, &cmd, &data);
  648. return err;
  649. }
  650. static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
  651. bool send_status)
  652. {
  653. unsigned int status, start;
  654. struct mmc_cmd cmd;
  655. int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS;
  656. bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&
  657. (index == EXT_CSD_PART_CONF);
  658. int ret;
  659. if (mmc->gen_cmd6_time)
  660. timeout_ms = mmc->gen_cmd6_time * 10;
  661. if (is_part_switch && mmc->part_switch_time)
  662. timeout_ms = mmc->part_switch_time * 10;
  663. cmd.cmdidx = MMC_CMD_SWITCH;
  664. cmd.resp_type = MMC_RSP_R1b;
  665. cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
  666. (index << 16) |
  667. (value << 8);
  668. ret = mmc_send_cmd_retry(mmc, &cmd, NULL, 3);
  669. if (ret)
  670. return ret;
  671. start = get_timer(0);
  672. /* poll dat0 for rdy/buys status */
  673. ret = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
  674. if (ret && ret != -ENOSYS)
  675. return ret;
  676. /*
  677. * In cases when not allowed to poll by using CMD13 or because we aren't
  678. * capable of polling by using mmc_wait_dat0, then rely on waiting the
  679. * stated timeout to be sufficient.
  680. */
  681. if (ret == -ENOSYS || !send_status) {
  682. mdelay(timeout_ms);
  683. return 0;
  684. }
  685. /* Finally wait until the card is ready or indicates a failure
  686. * to switch. It doesn't hurt to use CMD13 here even if send_status
  687. * is false, because by now (after 'timeout_ms' ms) the bus should be
  688. * reliable.
  689. */
  690. do {
  691. ret = mmc_send_status(mmc, &status);
  692. if (!ret && (status & MMC_STATUS_SWITCH_ERROR)) {
  693. pr_debug("switch failed %d/%d/0x%x !\n", set, index,
  694. value);
  695. return -EIO;
  696. }
  697. if (!ret && (status & MMC_STATUS_RDY_FOR_DATA) &&
  698. (status & MMC_STATUS_CURR_STATE) == MMC_STATE_TRANS)
  699. return 0;
  700. udelay(100);
  701. } while (get_timer(start) < timeout_ms);
  702. return -ETIMEDOUT;
  703. }
  704. int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
  705. {
  706. return __mmc_switch(mmc, set, index, value, true);
  707. }
  708. int mmc_boot_wp(struct mmc *mmc)
  709. {
  710. return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP, 1);
  711. }
  712. #if !CONFIG_IS_ENABLED(MMC_TINY)
  713. static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
  714. bool hsdowngrade)
  715. {
  716. int err;
  717. int speed_bits;
  718. ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
  719. switch (mode) {
  720. case MMC_HS:
  721. case MMC_HS_52:
  722. case MMC_DDR_52:
  723. speed_bits = EXT_CSD_TIMING_HS;
  724. break;
  725. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  726. case MMC_HS_200:
  727. speed_bits = EXT_CSD_TIMING_HS200;
  728. break;
  729. #endif
  730. #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  731. case MMC_HS_400:
  732. speed_bits = EXT_CSD_TIMING_HS400;
  733. break;
  734. #endif
  735. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  736. case MMC_HS_400_ES:
  737. speed_bits = EXT_CSD_TIMING_HS400;
  738. break;
  739. #endif
  740. case MMC_LEGACY:
  741. speed_bits = EXT_CSD_TIMING_LEGACY;
  742. break;
  743. default:
  744. return -EINVAL;
  745. }
  746. err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
  747. speed_bits, !hsdowngrade);
  748. if (err)
  749. return err;
  750. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  751. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  752. /*
  753. * In case the eMMC is in HS200/HS400 mode and we are downgrading
  754. * to HS mode, the card clock are still running much faster than
  755. * the supported HS mode clock, so we can not reliably read out
  756. * Extended CSD. Reconfigure the controller to run at HS mode.
  757. */
  758. if (hsdowngrade) {
  759. mmc_select_mode(mmc, MMC_HS);
  760. mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
  761. }
  762. #endif
  763. if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
  764. /* Now check to see that it worked */
  765. err = mmc_send_ext_csd(mmc, test_csd);
  766. if (err)
  767. return err;
  768. /* No high-speed support */
  769. if (!test_csd[EXT_CSD_HS_TIMING])
  770. return -ENOTSUPP;
  771. }
  772. return 0;
  773. }
  774. static int mmc_get_capabilities(struct mmc *mmc)
  775. {
  776. u8 *ext_csd = mmc->ext_csd;
  777. char cardtype;
  778. mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
  779. if (mmc_host_is_spi(mmc))
  780. return 0;
  781. /* Only version 4 supports high-speed */
  782. if (mmc->version < MMC_VERSION_4)
  783. return 0;
  784. if (!ext_csd) {
  785. pr_err("No ext_csd found!\n"); /* this should enver happen */
  786. return -ENOTSUPP;
  787. }
  788. mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
  789. cardtype = ext_csd[EXT_CSD_CARD_TYPE];
  790. mmc->cardtype = cardtype;
  791. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  792. if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
  793. EXT_CSD_CARD_TYPE_HS200_1_8V)) {
  794. mmc->card_caps |= MMC_MODE_HS200;
  795. }
  796. #endif
  797. #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
  798. CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  799. if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
  800. EXT_CSD_CARD_TYPE_HS400_1_8V)) {
  801. mmc->card_caps |= MMC_MODE_HS400;
  802. }
  803. #endif
  804. if (cardtype & EXT_CSD_CARD_TYPE_52) {
  805. if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
  806. mmc->card_caps |= MMC_MODE_DDR_52MHz;
  807. mmc->card_caps |= MMC_MODE_HS_52MHz;
  808. }
  809. if (cardtype & EXT_CSD_CARD_TYPE_26)
  810. mmc->card_caps |= MMC_MODE_HS;
  811. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  812. if (ext_csd[EXT_CSD_STROBE_SUPPORT] &&
  813. (mmc->card_caps & MMC_MODE_HS400)) {
  814. mmc->card_caps |= MMC_MODE_HS400_ES;
  815. }
  816. #endif
  817. return 0;
  818. }
  819. #endif
  820. static int mmc_set_capacity(struct mmc *mmc, int part_num)
  821. {
  822. switch (part_num) {
  823. case 0:
  824. mmc->capacity = mmc->capacity_user;
  825. break;
  826. case 1:
  827. case 2:
  828. mmc->capacity = mmc->capacity_boot;
  829. break;
  830. case 3:
  831. mmc->capacity = mmc->capacity_rpmb;
  832. break;
  833. case 4:
  834. case 5:
  835. case 6:
  836. case 7:
  837. mmc->capacity = mmc->capacity_gp[part_num - 4];
  838. break;
  839. default:
  840. return -1;
  841. }
  842. mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
  843. return 0;
  844. }
  845. int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
  846. {
  847. int ret;
  848. int retry = 3;
  849. do {
  850. ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  851. EXT_CSD_PART_CONF,
  852. (mmc->part_config & ~PART_ACCESS_MASK)
  853. | (part_num & PART_ACCESS_MASK));
  854. } while (ret && retry--);
  855. /*
  856. * Set the capacity if the switch succeeded or was intended
  857. * to return to representing the raw device.
  858. */
  859. if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
  860. ret = mmc_set_capacity(mmc, part_num);
  861. mmc_get_blk_desc(mmc)->hwpart = part_num;
  862. }
  863. return ret;
  864. }
  865. #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
  866. int mmc_hwpart_config(struct mmc *mmc,
  867. const struct mmc_hwpart_conf *conf,
  868. enum mmc_hwpart_conf_mode mode)
  869. {
  870. u8 part_attrs = 0;
  871. u32 enh_size_mult;
  872. u32 enh_start_addr;
  873. u32 gp_size_mult[4];
  874. u32 max_enh_size_mult;
  875. u32 tot_enh_size_mult = 0;
  876. u8 wr_rel_set;
  877. int i, pidx, err;
  878. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  879. if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
  880. return -EINVAL;
  881. if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
  882. pr_err("eMMC >= 4.4 required for enhanced user data area\n");
  883. return -EMEDIUMTYPE;
  884. }
  885. if (!(mmc->part_support & PART_SUPPORT)) {
  886. pr_err("Card does not support partitioning\n");
  887. return -EMEDIUMTYPE;
  888. }
  889. if (!mmc->hc_wp_grp_size) {
  890. pr_err("Card does not define HC WP group size\n");
  891. return -EMEDIUMTYPE;
  892. }
  893. /* check partition alignment and total enhanced size */
  894. if (conf->user.enh_size) {
  895. if (conf->user.enh_size % mmc->hc_wp_grp_size ||
  896. conf->user.enh_start % mmc->hc_wp_grp_size) {
  897. pr_err("User data enhanced area not HC WP group "
  898. "size aligned\n");
  899. return -EINVAL;
  900. }
  901. part_attrs |= EXT_CSD_ENH_USR;
  902. enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
  903. if (mmc->high_capacity) {
  904. enh_start_addr = conf->user.enh_start;
  905. } else {
  906. enh_start_addr = (conf->user.enh_start << 9);
  907. }
  908. } else {
  909. enh_size_mult = 0;
  910. enh_start_addr = 0;
  911. }
  912. tot_enh_size_mult += enh_size_mult;
  913. for (pidx = 0; pidx < 4; pidx++) {
  914. if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
  915. pr_err("GP%i partition not HC WP group size "
  916. "aligned\n", pidx+1);
  917. return -EINVAL;
  918. }
  919. gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
  920. if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
  921. part_attrs |= EXT_CSD_ENH_GP(pidx);
  922. tot_enh_size_mult += gp_size_mult[pidx];
  923. }
  924. }
  925. if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
  926. pr_err("Card does not support enhanced attribute\n");
  927. return -EMEDIUMTYPE;
  928. }
  929. err = mmc_send_ext_csd(mmc, ext_csd);
  930. if (err)
  931. return err;
  932. max_enh_size_mult =
  933. (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
  934. (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
  935. ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
  936. if (tot_enh_size_mult > max_enh_size_mult) {
  937. pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
  938. tot_enh_size_mult, max_enh_size_mult);
  939. return -EMEDIUMTYPE;
  940. }
  941. /* The default value of EXT_CSD_WR_REL_SET is device
  942. * dependent, the values can only be changed if the
  943. * EXT_CSD_HS_CTRL_REL bit is set. The values can be
  944. * changed only once and before partitioning is completed. */
  945. wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
  946. if (conf->user.wr_rel_change) {
  947. if (conf->user.wr_rel_set)
  948. wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
  949. else
  950. wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
  951. }
  952. for (pidx = 0; pidx < 4; pidx++) {
  953. if (conf->gp_part[pidx].wr_rel_change) {
  954. if (conf->gp_part[pidx].wr_rel_set)
  955. wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
  956. else
  957. wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
  958. }
  959. }
  960. if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
  961. !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
  962. puts("Card does not support host controlled partition write "
  963. "reliability settings\n");
  964. return -EMEDIUMTYPE;
  965. }
  966. if (ext_csd[EXT_CSD_PARTITION_SETTING] &
  967. EXT_CSD_PARTITION_SETTING_COMPLETED) {
  968. pr_err("Card already partitioned\n");
  969. return -EPERM;
  970. }
  971. if (mode == MMC_HWPART_CONF_CHECK)
  972. return 0;
  973. /* Partitioning requires high-capacity size definitions */
  974. if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
  975. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  976. EXT_CSD_ERASE_GROUP_DEF, 1);
  977. if (err)
  978. return err;
  979. ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
  980. #if CONFIG_IS_ENABLED(MMC_WRITE)
  981. /* update erase group size to be high-capacity */
  982. mmc->erase_grp_size =
  983. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
  984. #endif
  985. }
  986. /* all OK, write the configuration */
  987. for (i = 0; i < 4; i++) {
  988. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  989. EXT_CSD_ENH_START_ADDR+i,
  990. (enh_start_addr >> (i*8)) & 0xFF);
  991. if (err)
  992. return err;
  993. }
  994. for (i = 0; i < 3; i++) {
  995. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  996. EXT_CSD_ENH_SIZE_MULT+i,
  997. (enh_size_mult >> (i*8)) & 0xFF);
  998. if (err)
  999. return err;
  1000. }
  1001. for (pidx = 0; pidx < 4; pidx++) {
  1002. for (i = 0; i < 3; i++) {
  1003. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1004. EXT_CSD_GP_SIZE_MULT+pidx*3+i,
  1005. (gp_size_mult[pidx] >> (i*8)) & 0xFF);
  1006. if (err)
  1007. return err;
  1008. }
  1009. }
  1010. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1011. EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
  1012. if (err)
  1013. return err;
  1014. if (mode == MMC_HWPART_CONF_SET)
  1015. return 0;
  1016. /* The WR_REL_SET is a write-once register but shall be
  1017. * written before setting PART_SETTING_COMPLETED. As it is
  1018. * write-once we can only write it when completing the
  1019. * partitioning. */
  1020. if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
  1021. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1022. EXT_CSD_WR_REL_SET, wr_rel_set);
  1023. if (err)
  1024. return err;
  1025. }
  1026. /* Setting PART_SETTING_COMPLETED confirms the partition
  1027. * configuration but it only becomes effective after power
  1028. * cycle, so we do not adjust the partition related settings
  1029. * in the mmc struct. */
  1030. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1031. EXT_CSD_PARTITION_SETTING,
  1032. EXT_CSD_PARTITION_SETTING_COMPLETED);
  1033. if (err)
  1034. return err;
  1035. return 0;
  1036. }
  1037. #endif
  1038. #if !CONFIG_IS_ENABLED(DM_MMC)
  1039. int mmc_getcd(struct mmc *mmc)
  1040. {
  1041. int cd;
  1042. cd = board_mmc_getcd(mmc);
  1043. if (cd < 0) {
  1044. if (mmc->cfg->ops->getcd)
  1045. cd = mmc->cfg->ops->getcd(mmc);
  1046. else
  1047. cd = 1;
  1048. }
  1049. return cd;
  1050. }
  1051. #endif
  1052. #if !CONFIG_IS_ENABLED(MMC_TINY)
  1053. static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
  1054. {
  1055. struct mmc_cmd cmd;
  1056. struct mmc_data data;
  1057. /* Switch the frequency */
  1058. cmd.cmdidx = SD_CMD_SWITCH_FUNC;
  1059. cmd.resp_type = MMC_RSP_R1;
  1060. cmd.cmdarg = (mode << 31) | 0xffffff;
  1061. cmd.cmdarg &= ~(0xf << (group * 4));
  1062. cmd.cmdarg |= value << (group * 4);
  1063. data.dest = (char *)resp;
  1064. data.blocksize = 64;
  1065. data.blocks = 1;
  1066. data.flags = MMC_DATA_READ;
  1067. return mmc_send_cmd(mmc, &cmd, &data);
  1068. }
  1069. static int sd_get_capabilities(struct mmc *mmc)
  1070. {
  1071. int err;
  1072. struct mmc_cmd cmd;
  1073. ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
  1074. ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
  1075. struct mmc_data data;
  1076. int timeout;
  1077. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1078. u32 sd3_bus_mode;
  1079. #endif
  1080. mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
  1081. if (mmc_host_is_spi(mmc))
  1082. return 0;
  1083. /* Read the SCR to find out if this card supports higher speeds */
  1084. cmd.cmdidx = MMC_CMD_APP_CMD;
  1085. cmd.resp_type = MMC_RSP_R1;
  1086. cmd.cmdarg = mmc->rca << 16;
  1087. err = mmc_send_cmd(mmc, &cmd, NULL);
  1088. if (err)
  1089. return err;
  1090. cmd.cmdidx = SD_CMD_APP_SEND_SCR;
  1091. cmd.resp_type = MMC_RSP_R1;
  1092. cmd.cmdarg = 0;
  1093. data.dest = (char *)scr;
  1094. data.blocksize = 8;
  1095. data.blocks = 1;
  1096. data.flags = MMC_DATA_READ;
  1097. err = mmc_send_cmd_retry(mmc, &cmd, &data, 3);
  1098. if (err)
  1099. return err;
  1100. mmc->scr[0] = __be32_to_cpu(scr[0]);
  1101. mmc->scr[1] = __be32_to_cpu(scr[1]);
  1102. switch ((mmc->scr[0] >> 24) & 0xf) {
  1103. case 0:
  1104. mmc->version = SD_VERSION_1_0;
  1105. break;
  1106. case 1:
  1107. mmc->version = SD_VERSION_1_10;
  1108. break;
  1109. case 2:
  1110. mmc->version = SD_VERSION_2;
  1111. if ((mmc->scr[0] >> 15) & 0x1)
  1112. mmc->version = SD_VERSION_3;
  1113. break;
  1114. default:
  1115. mmc->version = SD_VERSION_1_0;
  1116. break;
  1117. }
  1118. if (mmc->scr[0] & SD_DATA_4BIT)
  1119. mmc->card_caps |= MMC_MODE_4BIT;
  1120. /* Version 1.0 doesn't support switching */
  1121. if (mmc->version == SD_VERSION_1_0)
  1122. return 0;
  1123. timeout = 4;
  1124. while (timeout--) {
  1125. err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
  1126. (u8 *)switch_status);
  1127. if (err)
  1128. return err;
  1129. /* The high-speed function is busy. Try again */
  1130. if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
  1131. break;
  1132. }
  1133. /* If high-speed isn't supported, we return */
  1134. if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
  1135. mmc->card_caps |= MMC_CAP(SD_HS);
  1136. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1137. /* Version before 3.0 don't support UHS modes */
  1138. if (mmc->version < SD_VERSION_3)
  1139. return 0;
  1140. sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
  1141. if (sd3_bus_mode & SD_MODE_UHS_SDR104)
  1142. mmc->card_caps |= MMC_CAP(UHS_SDR104);
  1143. if (sd3_bus_mode & SD_MODE_UHS_SDR50)
  1144. mmc->card_caps |= MMC_CAP(UHS_SDR50);
  1145. if (sd3_bus_mode & SD_MODE_UHS_SDR25)
  1146. mmc->card_caps |= MMC_CAP(UHS_SDR25);
  1147. if (sd3_bus_mode & SD_MODE_UHS_SDR12)
  1148. mmc->card_caps |= MMC_CAP(UHS_SDR12);
  1149. if (sd3_bus_mode & SD_MODE_UHS_DDR50)
  1150. mmc->card_caps |= MMC_CAP(UHS_DDR50);
  1151. #endif
  1152. return 0;
  1153. }
  1154. static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
  1155. {
  1156. int err;
  1157. ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
  1158. int speed;
  1159. /* SD version 1.00 and 1.01 does not support CMD 6 */
  1160. if (mmc->version == SD_VERSION_1_0)
  1161. return 0;
  1162. switch (mode) {
  1163. case MMC_LEGACY:
  1164. speed = UHS_SDR12_BUS_SPEED;
  1165. break;
  1166. case SD_HS:
  1167. speed = HIGH_SPEED_BUS_SPEED;
  1168. break;
  1169. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1170. case UHS_SDR12:
  1171. speed = UHS_SDR12_BUS_SPEED;
  1172. break;
  1173. case UHS_SDR25:
  1174. speed = UHS_SDR25_BUS_SPEED;
  1175. break;
  1176. case UHS_SDR50:
  1177. speed = UHS_SDR50_BUS_SPEED;
  1178. break;
  1179. case UHS_DDR50:
  1180. speed = UHS_DDR50_BUS_SPEED;
  1181. break;
  1182. case UHS_SDR104:
  1183. speed = UHS_SDR104_BUS_SPEED;
  1184. break;
  1185. #endif
  1186. default:
  1187. return -EINVAL;
  1188. }
  1189. err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
  1190. if (err)
  1191. return err;
  1192. if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
  1193. return -ENOTSUPP;
  1194. return 0;
  1195. }
  1196. static int sd_select_bus_width(struct mmc *mmc, int w)
  1197. {
  1198. int err;
  1199. struct mmc_cmd cmd;
  1200. if ((w != 4) && (w != 1))
  1201. return -EINVAL;
  1202. cmd.cmdidx = MMC_CMD_APP_CMD;
  1203. cmd.resp_type = MMC_RSP_R1;
  1204. cmd.cmdarg = mmc->rca << 16;
  1205. err = mmc_send_cmd(mmc, &cmd, NULL);
  1206. if (err)
  1207. return err;
  1208. cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
  1209. cmd.resp_type = MMC_RSP_R1;
  1210. if (w == 4)
  1211. cmd.cmdarg = 2;
  1212. else if (w == 1)
  1213. cmd.cmdarg = 0;
  1214. err = mmc_send_cmd(mmc, &cmd, NULL);
  1215. if (err)
  1216. return err;
  1217. return 0;
  1218. }
  1219. #endif
  1220. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1221. static int sd_read_ssr(struct mmc *mmc)
  1222. {
  1223. static const unsigned int sd_au_size[] = {
  1224. 0, SZ_16K / 512, SZ_32K / 512,
  1225. SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
  1226. SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
  1227. SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
  1228. SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
  1229. SZ_64M / 512,
  1230. };
  1231. int err, i;
  1232. struct mmc_cmd cmd;
  1233. ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
  1234. struct mmc_data data;
  1235. unsigned int au, eo, et, es;
  1236. cmd.cmdidx = MMC_CMD_APP_CMD;
  1237. cmd.resp_type = MMC_RSP_R1;
  1238. cmd.cmdarg = mmc->rca << 16;
  1239. err = mmc_send_cmd_quirks(mmc, &cmd, NULL, MMC_QUIRK_RETRY_APP_CMD, 4);
  1240. if (err)
  1241. return err;
  1242. cmd.cmdidx = SD_CMD_APP_SD_STATUS;
  1243. cmd.resp_type = MMC_RSP_R1;
  1244. cmd.cmdarg = 0;
  1245. data.dest = (char *)ssr;
  1246. data.blocksize = 64;
  1247. data.blocks = 1;
  1248. data.flags = MMC_DATA_READ;
  1249. err = mmc_send_cmd_retry(mmc, &cmd, &data, 3);
  1250. if (err)
  1251. return err;
  1252. for (i = 0; i < 16; i++)
  1253. ssr[i] = be32_to_cpu(ssr[i]);
  1254. au = (ssr[2] >> 12) & 0xF;
  1255. if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
  1256. mmc->ssr.au = sd_au_size[au];
  1257. es = (ssr[3] >> 24) & 0xFF;
  1258. es |= (ssr[2] & 0xFF) << 8;
  1259. et = (ssr[3] >> 18) & 0x3F;
  1260. if (es && et) {
  1261. eo = (ssr[3] >> 16) & 0x3;
  1262. mmc->ssr.erase_timeout = (et * 1000) / es;
  1263. mmc->ssr.erase_offset = eo * 1000;
  1264. }
  1265. } else {
  1266. pr_debug("Invalid Allocation Unit Size.\n");
  1267. }
  1268. return 0;
  1269. }
  1270. #endif
  1271. /* frequency bases */
  1272. /* divided by 10 to be nice to platforms without floating point */
  1273. static const int fbase[] = {
  1274. 10000,
  1275. 100000,
  1276. 1000000,
  1277. 10000000,
  1278. };
  1279. /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
  1280. * to platforms without floating point.
  1281. */
  1282. static const u8 multipliers[] = {
  1283. 0, /* reserved */
  1284. 10,
  1285. 12,
  1286. 13,
  1287. 15,
  1288. 20,
  1289. 25,
  1290. 30,
  1291. 35,
  1292. 40,
  1293. 45,
  1294. 50,
  1295. 55,
  1296. 60,
  1297. 70,
  1298. 80,
  1299. };
  1300. static inline int bus_width(uint cap)
  1301. {
  1302. if (cap == MMC_MODE_8BIT)
  1303. return 8;
  1304. if (cap == MMC_MODE_4BIT)
  1305. return 4;
  1306. if (cap == MMC_MODE_1BIT)
  1307. return 1;
  1308. pr_warn("invalid bus witdh capability 0x%x\n", cap);
  1309. return 0;
  1310. }
  1311. #if !CONFIG_IS_ENABLED(DM_MMC)
  1312. #ifdef MMC_SUPPORTS_TUNING
  1313. static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
  1314. {
  1315. return -ENOTSUPP;
  1316. }
  1317. #endif
  1318. static int mmc_set_ios(struct mmc *mmc)
  1319. {
  1320. int ret = 0;
  1321. if (mmc->cfg->ops->set_ios)
  1322. ret = mmc->cfg->ops->set_ios(mmc);
  1323. return ret;
  1324. }
  1325. static int mmc_host_power_cycle(struct mmc *mmc)
  1326. {
  1327. int ret = 0;
  1328. if (mmc->cfg->ops->host_power_cycle)
  1329. ret = mmc->cfg->ops->host_power_cycle(mmc);
  1330. return ret;
  1331. }
  1332. #endif
  1333. int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
  1334. {
  1335. if (!disable) {
  1336. if (clock > mmc->cfg->f_max)
  1337. clock = mmc->cfg->f_max;
  1338. if (clock < mmc->cfg->f_min)
  1339. clock = mmc->cfg->f_min;
  1340. }
  1341. mmc->clock = clock;
  1342. mmc->clk_disable = disable;
  1343. debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
  1344. return mmc_set_ios(mmc);
  1345. }
  1346. static int mmc_set_bus_width(struct mmc *mmc, uint width)
  1347. {
  1348. mmc->bus_width = width;
  1349. return mmc_set_ios(mmc);
  1350. }
  1351. #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
  1352. /*
  1353. * helper function to display the capabilities in a human
  1354. * friendly manner. The capabilities include bus width and
  1355. * supported modes.
  1356. */
  1357. void mmc_dump_capabilities(const char *text, uint caps)
  1358. {
  1359. enum bus_mode mode;
  1360. pr_debug("%s: widths [", text);
  1361. if (caps & MMC_MODE_8BIT)
  1362. pr_debug("8, ");
  1363. if (caps & MMC_MODE_4BIT)
  1364. pr_debug("4, ");
  1365. if (caps & MMC_MODE_1BIT)
  1366. pr_debug("1, ");
  1367. pr_debug("\b\b] modes [");
  1368. for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
  1369. if (MMC_CAP(mode) & caps)
  1370. pr_debug("%s, ", mmc_mode_name(mode));
  1371. pr_debug("\b\b]\n");
  1372. }
  1373. #endif
  1374. struct mode_width_tuning {
  1375. enum bus_mode mode;
  1376. uint widths;
  1377. #ifdef MMC_SUPPORTS_TUNING
  1378. uint tuning;
  1379. #endif
  1380. };
  1381. #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
  1382. int mmc_voltage_to_mv(enum mmc_voltage voltage)
  1383. {
  1384. switch (voltage) {
  1385. case MMC_SIGNAL_VOLTAGE_000: return 0;
  1386. case MMC_SIGNAL_VOLTAGE_330: return 3300;
  1387. case MMC_SIGNAL_VOLTAGE_180: return 1800;
  1388. case MMC_SIGNAL_VOLTAGE_120: return 1200;
  1389. }
  1390. return -EINVAL;
  1391. }
  1392. static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
  1393. {
  1394. int err;
  1395. if (mmc->signal_voltage == signal_voltage)
  1396. return 0;
  1397. mmc->signal_voltage = signal_voltage;
  1398. err = mmc_set_ios(mmc);
  1399. if (err)
  1400. pr_debug("unable to set voltage (err %d)\n", err);
  1401. return err;
  1402. }
  1403. #else
  1404. static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
  1405. {
  1406. return 0;
  1407. }
  1408. #endif
  1409. #if !CONFIG_IS_ENABLED(MMC_TINY)
  1410. static const struct mode_width_tuning sd_modes_by_pref[] = {
  1411. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1412. #ifdef MMC_SUPPORTS_TUNING
  1413. {
  1414. .mode = UHS_SDR104,
  1415. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1416. .tuning = MMC_CMD_SEND_TUNING_BLOCK
  1417. },
  1418. #endif
  1419. {
  1420. .mode = UHS_SDR50,
  1421. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1422. },
  1423. {
  1424. .mode = UHS_DDR50,
  1425. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1426. },
  1427. {
  1428. .mode = UHS_SDR25,
  1429. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1430. },
  1431. #endif
  1432. {
  1433. .mode = SD_HS,
  1434. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1435. },
  1436. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1437. {
  1438. .mode = UHS_SDR12,
  1439. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1440. },
  1441. #endif
  1442. {
  1443. .mode = MMC_LEGACY,
  1444. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1445. }
  1446. };
  1447. #define for_each_sd_mode_by_pref(caps, mwt) \
  1448. for (mwt = sd_modes_by_pref;\
  1449. mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
  1450. mwt++) \
  1451. if (caps & MMC_CAP(mwt->mode))
  1452. static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
  1453. {
  1454. int err;
  1455. uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
  1456. const struct mode_width_tuning *mwt;
  1457. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1458. bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
  1459. #else
  1460. bool uhs_en = false;
  1461. #endif
  1462. uint caps;
  1463. #ifdef DEBUG
  1464. mmc_dump_capabilities("sd card", card_caps);
  1465. mmc_dump_capabilities("host", mmc->host_caps);
  1466. #endif
  1467. if (mmc_host_is_spi(mmc)) {
  1468. mmc_set_bus_width(mmc, 1);
  1469. mmc_select_mode(mmc, MMC_LEGACY);
  1470. mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
  1471. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1472. err = sd_read_ssr(mmc);
  1473. if (err)
  1474. pr_warn("unable to read ssr\n");
  1475. #endif
  1476. return 0;
  1477. }
  1478. /* Restrict card's capabilities by what the host can do */
  1479. caps = card_caps & mmc->host_caps;
  1480. if (!uhs_en)
  1481. caps &= ~UHS_CAPS;
  1482. for_each_sd_mode_by_pref(caps, mwt) {
  1483. uint *w;
  1484. for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
  1485. if (*w & caps & mwt->widths) {
  1486. pr_debug("trying mode %s width %d (at %d MHz)\n",
  1487. mmc_mode_name(mwt->mode),
  1488. bus_width(*w),
  1489. mmc_mode2freq(mmc, mwt->mode) / 1000000);
  1490. /* configure the bus width (card + host) */
  1491. err = sd_select_bus_width(mmc, bus_width(*w));
  1492. if (err)
  1493. goto error;
  1494. mmc_set_bus_width(mmc, bus_width(*w));
  1495. /* configure the bus mode (card) */
  1496. err = sd_set_card_speed(mmc, mwt->mode);
  1497. if (err)
  1498. goto error;
  1499. /* configure the bus mode (host) */
  1500. mmc_select_mode(mmc, mwt->mode);
  1501. mmc_set_clock(mmc, mmc->tran_speed,
  1502. MMC_CLK_ENABLE);
  1503. #ifdef MMC_SUPPORTS_TUNING
  1504. /* execute tuning if needed */
  1505. if (mwt->tuning && !mmc_host_is_spi(mmc)) {
  1506. err = mmc_execute_tuning(mmc,
  1507. mwt->tuning);
  1508. if (err) {
  1509. pr_debug("tuning failed\n");
  1510. goto error;
  1511. }
  1512. }
  1513. #endif
  1514. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1515. err = sd_read_ssr(mmc);
  1516. if (err)
  1517. pr_warn("unable to read ssr\n");
  1518. #endif
  1519. if (!err)
  1520. return 0;
  1521. error:
  1522. /* revert to a safer bus speed */
  1523. mmc_select_mode(mmc, MMC_LEGACY);
  1524. mmc_set_clock(mmc, mmc->tran_speed,
  1525. MMC_CLK_ENABLE);
  1526. }
  1527. }
  1528. }
  1529. pr_err("unable to select a mode\n");
  1530. return -ENOTSUPP;
  1531. }
  1532. /*
  1533. * read the compare the part of ext csd that is constant.
  1534. * This can be used to check that the transfer is working
  1535. * as expected.
  1536. */
  1537. static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
  1538. {
  1539. int err;
  1540. const u8 *ext_csd = mmc->ext_csd;
  1541. ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
  1542. if (mmc->version < MMC_VERSION_4)
  1543. return 0;
  1544. err = mmc_send_ext_csd(mmc, test_csd);
  1545. if (err)
  1546. return err;
  1547. /* Only compare read only fields */
  1548. if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
  1549. == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
  1550. ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
  1551. == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
  1552. ext_csd[EXT_CSD_REV]
  1553. == test_csd[EXT_CSD_REV] &&
  1554. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
  1555. == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
  1556. memcmp(&ext_csd[EXT_CSD_SEC_CNT],
  1557. &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
  1558. return 0;
  1559. return -EBADMSG;
  1560. }
  1561. #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
  1562. static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
  1563. uint32_t allowed_mask)
  1564. {
  1565. u32 card_mask = 0;
  1566. switch (mode) {
  1567. case MMC_HS_400_ES:
  1568. case MMC_HS_400:
  1569. case MMC_HS_200:
  1570. if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
  1571. EXT_CSD_CARD_TYPE_HS400_1_8V))
  1572. card_mask |= MMC_SIGNAL_VOLTAGE_180;
  1573. if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
  1574. EXT_CSD_CARD_TYPE_HS400_1_2V))
  1575. card_mask |= MMC_SIGNAL_VOLTAGE_120;
  1576. break;
  1577. case MMC_DDR_52:
  1578. if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
  1579. card_mask |= MMC_SIGNAL_VOLTAGE_330 |
  1580. MMC_SIGNAL_VOLTAGE_180;
  1581. if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
  1582. card_mask |= MMC_SIGNAL_VOLTAGE_120;
  1583. break;
  1584. default:
  1585. card_mask |= MMC_SIGNAL_VOLTAGE_330;
  1586. break;
  1587. }
  1588. while (card_mask & allowed_mask) {
  1589. enum mmc_voltage best_match;
  1590. best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
  1591. if (!mmc_set_signal_voltage(mmc, best_match))
  1592. return 0;
  1593. allowed_mask &= ~best_match;
  1594. }
  1595. return -ENOTSUPP;
  1596. }
  1597. #else
  1598. static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
  1599. uint32_t allowed_mask)
  1600. {
  1601. return 0;
  1602. }
  1603. #endif
  1604. static const struct mode_width_tuning mmc_modes_by_pref[] = {
  1605. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1606. {
  1607. .mode = MMC_HS_400_ES,
  1608. .widths = MMC_MODE_8BIT,
  1609. },
  1610. #endif
  1611. #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  1612. {
  1613. .mode = MMC_HS_400,
  1614. .widths = MMC_MODE_8BIT,
  1615. .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
  1616. },
  1617. #endif
  1618. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  1619. {
  1620. .mode = MMC_HS_200,
  1621. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
  1622. .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
  1623. },
  1624. #endif
  1625. {
  1626. .mode = MMC_DDR_52,
  1627. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
  1628. },
  1629. {
  1630. .mode = MMC_HS_52,
  1631. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
  1632. },
  1633. {
  1634. .mode = MMC_HS,
  1635. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
  1636. },
  1637. {
  1638. .mode = MMC_LEGACY,
  1639. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
  1640. }
  1641. };
  1642. #define for_each_mmc_mode_by_pref(caps, mwt) \
  1643. for (mwt = mmc_modes_by_pref;\
  1644. mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
  1645. mwt++) \
  1646. if (caps & MMC_CAP(mwt->mode))
  1647. static const struct ext_csd_bus_width {
  1648. uint cap;
  1649. bool is_ddr;
  1650. uint ext_csd_bits;
  1651. } ext_csd_bus_width[] = {
  1652. {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
  1653. {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
  1654. {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
  1655. {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
  1656. {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
  1657. };
  1658. #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  1659. static int mmc_select_hs400(struct mmc *mmc)
  1660. {
  1661. int err;
  1662. /* Set timing to HS200 for tuning */
  1663. err = mmc_set_card_speed(mmc, MMC_HS_200, false);
  1664. if (err)
  1665. return err;
  1666. /* configure the bus mode (host) */
  1667. mmc_select_mode(mmc, MMC_HS_200);
  1668. mmc_set_clock(mmc, mmc->tran_speed, false);
  1669. /* execute tuning if needed */
  1670. mmc->hs400_tuning = 1;
  1671. err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
  1672. mmc->hs400_tuning = 0;
  1673. if (err) {
  1674. debug("tuning failed\n");
  1675. return err;
  1676. }
  1677. /* Set back to HS */
  1678. mmc_set_card_speed(mmc, MMC_HS, true);
  1679. err = mmc_hs400_prepare_ddr(mmc);
  1680. if (err)
  1681. return err;
  1682. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
  1683. EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
  1684. if (err)
  1685. return err;
  1686. err = mmc_set_card_speed(mmc, MMC_HS_400, false);
  1687. if (err)
  1688. return err;
  1689. mmc_select_mode(mmc, MMC_HS_400);
  1690. err = mmc_set_clock(mmc, mmc->tran_speed, false);
  1691. if (err)
  1692. return err;
  1693. return 0;
  1694. }
  1695. #else
  1696. static int mmc_select_hs400(struct mmc *mmc)
  1697. {
  1698. return -ENOTSUPP;
  1699. }
  1700. #endif
  1701. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1702. #if !CONFIG_IS_ENABLED(DM_MMC)
  1703. static int mmc_set_enhanced_strobe(struct mmc *mmc)
  1704. {
  1705. return -ENOTSUPP;
  1706. }
  1707. #endif
  1708. static int mmc_select_hs400es(struct mmc *mmc)
  1709. {
  1710. int err;
  1711. err = mmc_set_card_speed(mmc, MMC_HS, true);
  1712. if (err)
  1713. return err;
  1714. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
  1715. EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG |
  1716. EXT_CSD_BUS_WIDTH_STROBE);
  1717. if (err) {
  1718. printf("switch to bus width for hs400 failed\n");
  1719. return err;
  1720. }
  1721. /* TODO: driver strength */
  1722. err = mmc_set_card_speed(mmc, MMC_HS_400_ES, false);
  1723. if (err)
  1724. return err;
  1725. mmc_select_mode(mmc, MMC_HS_400_ES);
  1726. err = mmc_set_clock(mmc, mmc->tran_speed, false);
  1727. if (err)
  1728. return err;
  1729. return mmc_set_enhanced_strobe(mmc);
  1730. }
  1731. #else
  1732. static int mmc_select_hs400es(struct mmc *mmc)
  1733. {
  1734. return -ENOTSUPP;
  1735. }
  1736. #endif
  1737. #define for_each_supported_width(caps, ddr, ecbv) \
  1738. for (ecbv = ext_csd_bus_width;\
  1739. ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
  1740. ecbv++) \
  1741. if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
  1742. static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
  1743. {
  1744. int err = 0;
  1745. const struct mode_width_tuning *mwt;
  1746. const struct ext_csd_bus_width *ecbw;
  1747. #ifdef DEBUG
  1748. mmc_dump_capabilities("mmc", card_caps);
  1749. mmc_dump_capabilities("host", mmc->host_caps);
  1750. #endif
  1751. if (mmc_host_is_spi(mmc)) {
  1752. mmc_set_bus_width(mmc, 1);
  1753. mmc_select_mode(mmc, MMC_LEGACY);
  1754. mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
  1755. return 0;
  1756. }
  1757. /* Restrict card's capabilities by what the host can do */
  1758. card_caps &= mmc->host_caps;
  1759. /* Only version 4 of MMC supports wider bus widths */
  1760. if (mmc->version < MMC_VERSION_4)
  1761. return 0;
  1762. if (!mmc->ext_csd) {
  1763. pr_debug("No ext_csd found!\n"); /* this should enver happen */
  1764. return -ENOTSUPP;
  1765. }
  1766. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  1767. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
  1768. CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1769. /*
  1770. * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
  1771. * before doing anything else, since a transition from either of
  1772. * the HS200/HS400 mode directly to legacy mode is not supported.
  1773. */
  1774. if (mmc->selected_mode == MMC_HS_200 ||
  1775. mmc->selected_mode == MMC_HS_400 ||
  1776. mmc->selected_mode == MMC_HS_400_ES)
  1777. mmc_set_card_speed(mmc, MMC_HS, true);
  1778. else
  1779. #endif
  1780. mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
  1781. for_each_mmc_mode_by_pref(card_caps, mwt) {
  1782. for_each_supported_width(card_caps & mwt->widths,
  1783. mmc_is_mode_ddr(mwt->mode), ecbw) {
  1784. enum mmc_voltage old_voltage;
  1785. pr_debug("trying mode %s width %d (at %d MHz)\n",
  1786. mmc_mode_name(mwt->mode),
  1787. bus_width(ecbw->cap),
  1788. mmc_mode2freq(mmc, mwt->mode) / 1000000);
  1789. old_voltage = mmc->signal_voltage;
  1790. err = mmc_set_lowest_voltage(mmc, mwt->mode,
  1791. MMC_ALL_SIGNAL_VOLTAGE);
  1792. if (err)
  1793. continue;
  1794. /* configure the bus width (card + host) */
  1795. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1796. EXT_CSD_BUS_WIDTH,
  1797. ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
  1798. if (err)
  1799. goto error;
  1800. mmc_set_bus_width(mmc, bus_width(ecbw->cap));
  1801. if (mwt->mode == MMC_HS_400) {
  1802. err = mmc_select_hs400(mmc);
  1803. if (err) {
  1804. printf("Select HS400 failed %d\n", err);
  1805. goto error;
  1806. }
  1807. } else if (mwt->mode == MMC_HS_400_ES) {
  1808. err = mmc_select_hs400es(mmc);
  1809. if (err) {
  1810. printf("Select HS400ES failed %d\n",
  1811. err);
  1812. goto error;
  1813. }
  1814. } else {
  1815. /* configure the bus speed (card) */
  1816. err = mmc_set_card_speed(mmc, mwt->mode, false);
  1817. if (err)
  1818. goto error;
  1819. /*
  1820. * configure the bus width AND the ddr mode
  1821. * (card). The host side will be taken care
  1822. * of in the next step
  1823. */
  1824. if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
  1825. err = mmc_switch(mmc,
  1826. EXT_CSD_CMD_SET_NORMAL,
  1827. EXT_CSD_BUS_WIDTH,
  1828. ecbw->ext_csd_bits);
  1829. if (err)
  1830. goto error;
  1831. }
  1832. /* configure the bus mode (host) */
  1833. mmc_select_mode(mmc, mwt->mode);
  1834. mmc_set_clock(mmc, mmc->tran_speed,
  1835. MMC_CLK_ENABLE);
  1836. #ifdef MMC_SUPPORTS_TUNING
  1837. /* execute tuning if needed */
  1838. if (mwt->tuning) {
  1839. err = mmc_execute_tuning(mmc,
  1840. mwt->tuning);
  1841. if (err) {
  1842. pr_debug("tuning failed : %d\n", err);
  1843. goto error;
  1844. }
  1845. }
  1846. #endif
  1847. }
  1848. /* do a transfer to check the configuration */
  1849. err = mmc_read_and_compare_ext_csd(mmc);
  1850. if (!err)
  1851. return 0;
  1852. error:
  1853. mmc_set_signal_voltage(mmc, old_voltage);
  1854. /* if an error occurred, revert to a safer bus mode */
  1855. mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1856. EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
  1857. mmc_select_mode(mmc, MMC_LEGACY);
  1858. mmc_set_bus_width(mmc, 1);
  1859. }
  1860. }
  1861. pr_err("unable to select a mode : %d\n", err);
  1862. return -ENOTSUPP;
  1863. }
  1864. #endif
  1865. #if CONFIG_IS_ENABLED(MMC_TINY)
  1866. DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
  1867. #endif
  1868. static int mmc_startup_v4(struct mmc *mmc)
  1869. {
  1870. int err, i;
  1871. u64 capacity;
  1872. bool has_parts = false;
  1873. bool part_completed;
  1874. static const u32 mmc_versions[] = {
  1875. MMC_VERSION_4,
  1876. MMC_VERSION_4_1,
  1877. MMC_VERSION_4_2,
  1878. MMC_VERSION_4_3,
  1879. MMC_VERSION_4_4,
  1880. MMC_VERSION_4_41,
  1881. MMC_VERSION_4_5,
  1882. MMC_VERSION_5_0,
  1883. MMC_VERSION_5_1
  1884. };
  1885. #if CONFIG_IS_ENABLED(MMC_TINY)
  1886. u8 *ext_csd = ext_csd_bkup;
  1887. if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
  1888. return 0;
  1889. if (!mmc->ext_csd)
  1890. memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
  1891. err = mmc_send_ext_csd(mmc, ext_csd);
  1892. if (err)
  1893. goto error;
  1894. /* store the ext csd for future reference */
  1895. if (!mmc->ext_csd)
  1896. mmc->ext_csd = ext_csd;
  1897. #else
  1898. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  1899. if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
  1900. return 0;
  1901. /* check ext_csd version and capacity */
  1902. err = mmc_send_ext_csd(mmc, ext_csd);
  1903. if (err)
  1904. goto error;
  1905. /* store the ext csd for future reference */
  1906. if (!mmc->ext_csd)
  1907. mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
  1908. if (!mmc->ext_csd)
  1909. return -ENOMEM;
  1910. memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
  1911. #endif
  1912. if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
  1913. return -EINVAL;
  1914. mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
  1915. if (mmc->version >= MMC_VERSION_4_2) {
  1916. /*
  1917. * According to the JEDEC Standard, the value of
  1918. * ext_csd's capacity is valid if the value is more
  1919. * than 2GB
  1920. */
  1921. capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
  1922. | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
  1923. | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
  1924. | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
  1925. capacity *= MMC_MAX_BLOCK_LEN;
  1926. if ((capacity >> 20) > 2 * 1024)
  1927. mmc->capacity_user = capacity;
  1928. }
  1929. if (mmc->version >= MMC_VERSION_4_5)
  1930. mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME];
  1931. /* The partition data may be non-zero but it is only
  1932. * effective if PARTITION_SETTING_COMPLETED is set in
  1933. * EXT_CSD, so ignore any data if this bit is not set,
  1934. * except for enabling the high-capacity group size
  1935. * definition (see below).
  1936. */
  1937. part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
  1938. EXT_CSD_PARTITION_SETTING_COMPLETED);
  1939. mmc->part_switch_time = ext_csd[EXT_CSD_PART_SWITCH_TIME];
  1940. /* Some eMMC set the value too low so set a minimum */
  1941. if (mmc->part_switch_time < MMC_MIN_PART_SWITCH_TIME && mmc->part_switch_time)
  1942. mmc->part_switch_time = MMC_MIN_PART_SWITCH_TIME;
  1943. /* store the partition info of emmc */
  1944. mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
  1945. if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
  1946. ext_csd[EXT_CSD_BOOT_MULT])
  1947. mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
  1948. if (part_completed &&
  1949. (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
  1950. mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
  1951. mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
  1952. mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
  1953. for (i = 0; i < 4; i++) {
  1954. int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
  1955. uint mult = (ext_csd[idx + 2] << 16) +
  1956. (ext_csd[idx + 1] << 8) + ext_csd[idx];
  1957. if (mult)
  1958. has_parts = true;
  1959. if (!part_completed)
  1960. continue;
  1961. mmc->capacity_gp[i] = mult;
  1962. mmc->capacity_gp[i] *=
  1963. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
  1964. mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1965. mmc->capacity_gp[i] <<= 19;
  1966. }
  1967. #ifndef CONFIG_SPL_BUILD
  1968. if (part_completed) {
  1969. mmc->enh_user_size =
  1970. (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
  1971. (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
  1972. ext_csd[EXT_CSD_ENH_SIZE_MULT];
  1973. mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
  1974. mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1975. mmc->enh_user_size <<= 19;
  1976. mmc->enh_user_start =
  1977. (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
  1978. (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
  1979. (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
  1980. ext_csd[EXT_CSD_ENH_START_ADDR];
  1981. if (mmc->high_capacity)
  1982. mmc->enh_user_start <<= 9;
  1983. }
  1984. #endif
  1985. /*
  1986. * Host needs to enable ERASE_GRP_DEF bit if device is
  1987. * partitioned. This bit will be lost every time after a reset
  1988. * or power off. This will affect erase size.
  1989. */
  1990. if (part_completed)
  1991. has_parts = true;
  1992. if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
  1993. (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
  1994. has_parts = true;
  1995. if (has_parts) {
  1996. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1997. EXT_CSD_ERASE_GROUP_DEF, 1);
  1998. if (err)
  1999. goto error;
  2000. ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
  2001. }
  2002. if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
  2003. #if CONFIG_IS_ENABLED(MMC_WRITE)
  2004. /* Read out group size from ext_csd */
  2005. mmc->erase_grp_size =
  2006. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
  2007. #endif
  2008. /*
  2009. * if high capacity and partition setting completed
  2010. * SEC_COUNT is valid even if it is smaller than 2 GiB
  2011. * JEDEC Standard JESD84-B45, 6.2.4
  2012. */
  2013. if (mmc->high_capacity && part_completed) {
  2014. capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
  2015. (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
  2016. (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
  2017. (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
  2018. capacity *= MMC_MAX_BLOCK_LEN;
  2019. mmc->capacity_user = capacity;
  2020. }
  2021. }
  2022. #if CONFIG_IS_ENABLED(MMC_WRITE)
  2023. else {
  2024. /* Calculate the group size from the csd value. */
  2025. int erase_gsz, erase_gmul;
  2026. erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
  2027. erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
  2028. mmc->erase_grp_size = (erase_gsz + 1)
  2029. * (erase_gmul + 1);
  2030. }
  2031. #endif
  2032. #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
  2033. mmc->hc_wp_grp_size = 1024
  2034. * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
  2035. * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  2036. #endif
  2037. mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
  2038. return 0;
  2039. error:
  2040. if (mmc->ext_csd) {
  2041. #if !CONFIG_IS_ENABLED(MMC_TINY)
  2042. free(mmc->ext_csd);
  2043. #endif
  2044. mmc->ext_csd = NULL;
  2045. }
  2046. return err;
  2047. }
  2048. static int mmc_startup(struct mmc *mmc)
  2049. {
  2050. int err, i;
  2051. uint mult, freq;
  2052. u64 cmult, csize;
  2053. struct mmc_cmd cmd;
  2054. struct blk_desc *bdesc;
  2055. #ifdef CONFIG_MMC_SPI_CRC_ON
  2056. if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
  2057. cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
  2058. cmd.resp_type = MMC_RSP_R1;
  2059. cmd.cmdarg = 1;
  2060. err = mmc_send_cmd(mmc, &cmd, NULL);
  2061. if (err)
  2062. return err;
  2063. }
  2064. #endif
  2065. /* Put the Card in Identify Mode */
  2066. cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
  2067. MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
  2068. cmd.resp_type = MMC_RSP_R2;
  2069. cmd.cmdarg = 0;
  2070. err = mmc_send_cmd_quirks(mmc, &cmd, NULL, MMC_QUIRK_RETRY_SEND_CID, 4);
  2071. if (err)
  2072. return err;
  2073. memcpy(mmc->cid, cmd.response, 16);
  2074. /*
  2075. * For MMC cards, set the Relative Address.
  2076. * For SD cards, get the Relatvie Address.
  2077. * This also puts the cards into Standby State
  2078. */
  2079. if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
  2080. cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
  2081. cmd.cmdarg = mmc->rca << 16;
  2082. cmd.resp_type = MMC_RSP_R6;
  2083. err = mmc_send_cmd(mmc, &cmd, NULL);
  2084. if (err)
  2085. return err;
  2086. if (IS_SD(mmc))
  2087. mmc->rca = (cmd.response[0] >> 16) & 0xffff;
  2088. }
  2089. /* Get the Card-Specific Data */
  2090. cmd.cmdidx = MMC_CMD_SEND_CSD;
  2091. cmd.resp_type = MMC_RSP_R2;
  2092. cmd.cmdarg = mmc->rca << 16;
  2093. err = mmc_send_cmd(mmc, &cmd, NULL);
  2094. if (err)
  2095. return err;
  2096. mmc->csd[0] = cmd.response[0];
  2097. mmc->csd[1] = cmd.response[1];
  2098. mmc->csd[2] = cmd.response[2];
  2099. mmc->csd[3] = cmd.response[3];
  2100. if (mmc->version == MMC_VERSION_UNKNOWN) {
  2101. int version = (cmd.response[0] >> 26) & 0xf;
  2102. switch (version) {
  2103. case 0:
  2104. mmc->version = MMC_VERSION_1_2;
  2105. break;
  2106. case 1:
  2107. mmc->version = MMC_VERSION_1_4;
  2108. break;
  2109. case 2:
  2110. mmc->version = MMC_VERSION_2_2;
  2111. break;
  2112. case 3:
  2113. mmc->version = MMC_VERSION_3;
  2114. break;
  2115. case 4:
  2116. mmc->version = MMC_VERSION_4;
  2117. break;
  2118. default:
  2119. mmc->version = MMC_VERSION_1_2;
  2120. break;
  2121. }
  2122. }
  2123. /* divide frequency by 10, since the mults are 10x bigger */
  2124. freq = fbase[(cmd.response[0] & 0x7)];
  2125. mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
  2126. mmc->legacy_speed = freq * mult;
  2127. mmc_select_mode(mmc, MMC_LEGACY);
  2128. mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
  2129. mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
  2130. #if CONFIG_IS_ENABLED(MMC_WRITE)
  2131. if (IS_SD(mmc))
  2132. mmc->write_bl_len = mmc->read_bl_len;
  2133. else
  2134. mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
  2135. #endif
  2136. if (mmc->high_capacity) {
  2137. csize = (mmc->csd[1] & 0x3f) << 16
  2138. | (mmc->csd[2] & 0xffff0000) >> 16;
  2139. cmult = 8;
  2140. } else {
  2141. csize = (mmc->csd[1] & 0x3ff) << 2
  2142. | (mmc->csd[2] & 0xc0000000) >> 30;
  2143. cmult = (mmc->csd[2] & 0x00038000) >> 15;
  2144. }
  2145. mmc->capacity_user = (csize + 1) << (cmult + 2);
  2146. mmc->capacity_user *= mmc->read_bl_len;
  2147. mmc->capacity_boot = 0;
  2148. mmc->capacity_rpmb = 0;
  2149. for (i = 0; i < 4; i++)
  2150. mmc->capacity_gp[i] = 0;
  2151. if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
  2152. mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
  2153. #if CONFIG_IS_ENABLED(MMC_WRITE)
  2154. if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
  2155. mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
  2156. #endif
  2157. if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
  2158. cmd.cmdidx = MMC_CMD_SET_DSR;
  2159. cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
  2160. cmd.resp_type = MMC_RSP_NONE;
  2161. if (mmc_send_cmd(mmc, &cmd, NULL))
  2162. pr_warn("MMC: SET_DSR failed\n");
  2163. }
  2164. /* Select the card, and put it into Transfer Mode */
  2165. if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
  2166. cmd.cmdidx = MMC_CMD_SELECT_CARD;
  2167. cmd.resp_type = MMC_RSP_R1;
  2168. cmd.cmdarg = mmc->rca << 16;
  2169. err = mmc_send_cmd(mmc, &cmd, NULL);
  2170. if (err)
  2171. return err;
  2172. }
  2173. /*
  2174. * For SD, its erase group is always one sector
  2175. */
  2176. #if CONFIG_IS_ENABLED(MMC_WRITE)
  2177. mmc->erase_grp_size = 1;
  2178. #endif
  2179. mmc->part_config = MMCPART_NOAVAILABLE;
  2180. err = mmc_startup_v4(mmc);
  2181. if (err)
  2182. return err;
  2183. err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
  2184. if (err)
  2185. return err;
  2186. #if CONFIG_IS_ENABLED(MMC_TINY)
  2187. mmc_set_clock(mmc, mmc->legacy_speed, false);
  2188. mmc_select_mode(mmc, MMC_LEGACY);
  2189. mmc_set_bus_width(mmc, 1);
  2190. #else
  2191. if (IS_SD(mmc)) {
  2192. err = sd_get_capabilities(mmc);
  2193. if (err)
  2194. return err;
  2195. err = sd_select_mode_and_width(mmc, mmc->card_caps);
  2196. } else {
  2197. err = mmc_get_capabilities(mmc);
  2198. if (err)
  2199. return err;
  2200. err = mmc_select_mode_and_width(mmc, mmc->card_caps);
  2201. }
  2202. #endif
  2203. if (err)
  2204. return err;
  2205. mmc->best_mode = mmc->selected_mode;
  2206. /* Fix the block length for DDR mode */
  2207. if (mmc->ddr_mode) {
  2208. mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
  2209. #if CONFIG_IS_ENABLED(MMC_WRITE)
  2210. mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
  2211. #endif
  2212. }
  2213. /* fill in device description */
  2214. bdesc = mmc_get_blk_desc(mmc);
  2215. bdesc->lun = 0;
  2216. bdesc->hwpart = 0;
  2217. bdesc->type = 0;
  2218. bdesc->blksz = mmc->read_bl_len;
  2219. bdesc->log2blksz = LOG2(bdesc->blksz);
  2220. bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
  2221. #if !defined(CONFIG_SPL_BUILD) || \
  2222. (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
  2223. !CONFIG_IS_ENABLED(USE_TINY_PRINTF))
  2224. sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
  2225. mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
  2226. (mmc->cid[3] >> 16) & 0xffff);
  2227. sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
  2228. (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
  2229. (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
  2230. (mmc->cid[2] >> 24) & 0xff);
  2231. sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
  2232. (mmc->cid[2] >> 16) & 0xf);
  2233. #else
  2234. bdesc->vendor[0] = 0;
  2235. bdesc->product[0] = 0;
  2236. bdesc->revision[0] = 0;
  2237. #endif
  2238. #if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
  2239. part_init(bdesc);
  2240. #endif
  2241. return 0;
  2242. }
  2243. static int mmc_send_if_cond(struct mmc *mmc)
  2244. {
  2245. struct mmc_cmd cmd;
  2246. int err;
  2247. cmd.cmdidx = SD_CMD_SEND_IF_COND;
  2248. /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
  2249. cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
  2250. cmd.resp_type = MMC_RSP_R7;
  2251. err = mmc_send_cmd(mmc, &cmd, NULL);
  2252. if (err)
  2253. return err;
  2254. if ((cmd.response[0] & 0xff) != 0xaa)
  2255. return -EOPNOTSUPP;
  2256. else
  2257. mmc->version = SD_VERSION_2;
  2258. return 0;
  2259. }
  2260. #if !CONFIG_IS_ENABLED(DM_MMC)
  2261. /* board-specific MMC power initializations. */
  2262. __weak void board_mmc_power_init(void)
  2263. {
  2264. }
  2265. #endif
  2266. static int mmc_power_init(struct mmc *mmc)
  2267. {
  2268. #if CONFIG_IS_ENABLED(DM_MMC)
  2269. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  2270. int ret;
  2271. ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
  2272. &mmc->vmmc_supply);
  2273. if (ret)
  2274. pr_debug("%s: No vmmc supply\n", mmc->dev->name);
  2275. ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
  2276. &mmc->vqmmc_supply);
  2277. if (ret)
  2278. pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
  2279. #endif
  2280. #else /* !CONFIG_DM_MMC */
  2281. /*
  2282. * Driver model should use a regulator, as above, rather than calling
  2283. * out to board code.
  2284. */
  2285. board_mmc_power_init();
  2286. #endif
  2287. return 0;
  2288. }
  2289. /*
  2290. * put the host in the initial state:
  2291. * - turn on Vdd (card power supply)
  2292. * - configure the bus width and clock to minimal values
  2293. */
  2294. static void mmc_set_initial_state(struct mmc *mmc)
  2295. {
  2296. int err;
  2297. /* First try to set 3.3V. If it fails set to 1.8V */
  2298. err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
  2299. if (err != 0)
  2300. err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
  2301. if (err != 0)
  2302. pr_warn("mmc: failed to set signal voltage\n");
  2303. mmc_select_mode(mmc, MMC_LEGACY);
  2304. mmc_set_bus_width(mmc, 1);
  2305. mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
  2306. }
  2307. static int mmc_power_on(struct mmc *mmc)
  2308. {
  2309. #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
  2310. if (mmc->vmmc_supply) {
  2311. int ret = regulator_set_enable(mmc->vmmc_supply, true);
  2312. if (ret && ret != -EACCES) {
  2313. printf("Error enabling VMMC supply : %d\n", ret);
  2314. return ret;
  2315. }
  2316. }
  2317. #endif
  2318. return 0;
  2319. }
  2320. static int mmc_power_off(struct mmc *mmc)
  2321. {
  2322. mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
  2323. #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
  2324. if (mmc->vmmc_supply) {
  2325. int ret = regulator_set_enable(mmc->vmmc_supply, false);
  2326. if (ret && ret != -EACCES) {
  2327. pr_debug("Error disabling VMMC supply : %d\n", ret);
  2328. return ret;
  2329. }
  2330. }
  2331. #endif
  2332. return 0;
  2333. }
  2334. static int mmc_power_cycle(struct mmc *mmc)
  2335. {
  2336. int ret;
  2337. ret = mmc_power_off(mmc);
  2338. if (ret)
  2339. return ret;
  2340. ret = mmc_host_power_cycle(mmc);
  2341. if (ret)
  2342. return ret;
  2343. /*
  2344. * SD spec recommends at least 1ms of delay. Let's wait for 2ms
  2345. * to be on the safer side.
  2346. */
  2347. udelay(2000);
  2348. return mmc_power_on(mmc);
  2349. }
  2350. int mmc_get_op_cond(struct mmc *mmc, bool quiet)
  2351. {
  2352. bool uhs_en = supports_uhs(mmc->cfg->host_caps);
  2353. int err;
  2354. if (mmc->has_init)
  2355. return 0;
  2356. err = mmc_power_init(mmc);
  2357. if (err)
  2358. return err;
  2359. #ifdef CONFIG_MMC_QUIRKS
  2360. mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
  2361. MMC_QUIRK_RETRY_SEND_CID |
  2362. MMC_QUIRK_RETRY_APP_CMD;
  2363. #endif
  2364. err = mmc_power_cycle(mmc);
  2365. if (err) {
  2366. /*
  2367. * if power cycling is not supported, we should not try
  2368. * to use the UHS modes, because we wouldn't be able to
  2369. * recover from an error during the UHS initialization.
  2370. */
  2371. pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
  2372. uhs_en = false;
  2373. mmc->host_caps &= ~UHS_CAPS;
  2374. err = mmc_power_on(mmc);
  2375. }
  2376. if (err)
  2377. return err;
  2378. #if CONFIG_IS_ENABLED(DM_MMC)
  2379. /*
  2380. * Re-initialization is needed to clear old configuration for
  2381. * mmc rescan.
  2382. */
  2383. err = mmc_reinit(mmc);
  2384. #else
  2385. /* made sure it's not NULL earlier */
  2386. err = mmc->cfg->ops->init(mmc);
  2387. #endif
  2388. if (err)
  2389. return err;
  2390. mmc->ddr_mode = 0;
  2391. retry:
  2392. mmc_set_initial_state(mmc);
  2393. /* Reset the Card */
  2394. err = mmc_go_idle(mmc);
  2395. if (err)
  2396. return err;
  2397. /* The internal partition reset to user partition(0) at every CMD0 */
  2398. mmc_get_blk_desc(mmc)->hwpart = 0;
  2399. /* Test for SD version 2 */
  2400. err = mmc_send_if_cond(mmc);
  2401. /* Now try to get the SD card's operating condition */
  2402. err = sd_send_op_cond(mmc, uhs_en);
  2403. if (err && uhs_en) {
  2404. uhs_en = false;
  2405. mmc_power_cycle(mmc);
  2406. goto retry;
  2407. }
  2408. /* If the command timed out, we check for an MMC card */
  2409. if (err == -ETIMEDOUT) {
  2410. err = mmc_send_op_cond(mmc);
  2411. if (err) {
  2412. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  2413. if (!quiet)
  2414. pr_err("Card did not respond to voltage select! : %d\n", err);
  2415. #endif
  2416. return -EOPNOTSUPP;
  2417. }
  2418. }
  2419. return err;
  2420. }
  2421. int mmc_start_init(struct mmc *mmc)
  2422. {
  2423. bool no_card;
  2424. int err = 0;
  2425. /*
  2426. * all hosts are capable of 1 bit bus-width and able to use the legacy
  2427. * timings.
  2428. */
  2429. mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(MMC_LEGACY) |
  2430. MMC_MODE_1BIT;
  2431. if (IS_ENABLED(CONFIG_MMC_SPEED_MODE_SET)) {
  2432. if (mmc->user_speed_mode != MMC_MODES_END) {
  2433. int i;
  2434. /* set host caps */
  2435. if (mmc->host_caps & MMC_CAP(mmc->user_speed_mode)) {
  2436. /* Remove all existing speed capabilities */
  2437. for (i = MMC_LEGACY; i < MMC_MODES_END; i++)
  2438. mmc->host_caps &= ~MMC_CAP(i);
  2439. mmc->host_caps |= (MMC_CAP(mmc->user_speed_mode)
  2440. | MMC_CAP(MMC_LEGACY) |
  2441. MMC_MODE_1BIT);
  2442. } else {
  2443. pr_err("bus_mode requested is not supported\n");
  2444. return -EINVAL;
  2445. }
  2446. }
  2447. }
  2448. #if CONFIG_IS_ENABLED(DM_MMC)
  2449. mmc_deferred_probe(mmc);
  2450. #endif
  2451. #if !defined(CONFIG_MMC_BROKEN_CD)
  2452. no_card = mmc_getcd(mmc) == 0;
  2453. #else
  2454. no_card = 0;
  2455. #endif
  2456. #if !CONFIG_IS_ENABLED(DM_MMC)
  2457. /* we pretend there's no card when init is NULL */
  2458. no_card = no_card || (mmc->cfg->ops->init == NULL);
  2459. #endif
  2460. if (no_card) {
  2461. mmc->has_init = 0;
  2462. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  2463. pr_err("MMC: no card present\n");
  2464. #endif
  2465. return -ENOMEDIUM;
  2466. }
  2467. err = mmc_get_op_cond(mmc, false);
  2468. if (!err)
  2469. mmc->init_in_progress = 1;
  2470. return err;
  2471. }
  2472. static int mmc_complete_init(struct mmc *mmc)
  2473. {
  2474. int err = 0;
  2475. mmc->init_in_progress = 0;
  2476. if (mmc->op_cond_pending)
  2477. err = mmc_complete_op_cond(mmc);
  2478. if (!err)
  2479. err = mmc_startup(mmc);
  2480. if (err)
  2481. mmc->has_init = 0;
  2482. else
  2483. mmc->has_init = 1;
  2484. return err;
  2485. }
  2486. int mmc_init(struct mmc *mmc)
  2487. {
  2488. int err = 0;
  2489. __maybe_unused ulong start;
  2490. #if CONFIG_IS_ENABLED(DM_MMC)
  2491. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
  2492. upriv->mmc = mmc;
  2493. #endif
  2494. if (mmc->has_init)
  2495. return 0;
  2496. start = get_timer(0);
  2497. if (!mmc->init_in_progress)
  2498. err = mmc_start_init(mmc);
  2499. if (!err)
  2500. err = mmc_complete_init(mmc);
  2501. if (err)
  2502. pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
  2503. return err;
  2504. }
  2505. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  2506. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  2507. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  2508. int mmc_deinit(struct mmc *mmc)
  2509. {
  2510. u32 caps_filtered;
  2511. if (!mmc->has_init)
  2512. return 0;
  2513. if (IS_SD(mmc)) {
  2514. caps_filtered = mmc->card_caps &
  2515. ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
  2516. MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
  2517. MMC_CAP(UHS_SDR104));
  2518. return sd_select_mode_and_width(mmc, caps_filtered);
  2519. } else {
  2520. caps_filtered = mmc->card_caps &
  2521. ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400) | MMC_CAP(MMC_HS_400_ES));
  2522. return mmc_select_mode_and_width(mmc, caps_filtered);
  2523. }
  2524. }
  2525. #endif
  2526. int mmc_set_dsr(struct mmc *mmc, u16 val)
  2527. {
  2528. mmc->dsr = val;
  2529. return 0;
  2530. }
  2531. /* CPU-specific MMC initializations */
  2532. __weak int cpu_mmc_init(struct bd_info *bis)
  2533. {
  2534. return -1;
  2535. }
  2536. /* board-specific MMC initializations. */
  2537. __weak int board_mmc_init(struct bd_info *bis)
  2538. {
  2539. return -1;
  2540. }
  2541. void mmc_set_preinit(struct mmc *mmc, int preinit)
  2542. {
  2543. mmc->preinit = preinit;
  2544. }
  2545. #if CONFIG_IS_ENABLED(DM_MMC)
  2546. static int mmc_probe(struct bd_info *bis)
  2547. {
  2548. int ret, i;
  2549. struct uclass *uc;
  2550. struct udevice *dev;
  2551. ret = uclass_get(UCLASS_MMC, &uc);
  2552. if (ret)
  2553. return ret;
  2554. /*
  2555. * Try to add them in sequence order. Really with driver model we
  2556. * should allow holes, but the current MMC list does not allow that.
  2557. * So if we request 0, 1, 3 we will get 0, 1, 2.
  2558. */
  2559. for (i = 0; ; i++) {
  2560. ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
  2561. if (ret == -ENODEV)
  2562. break;
  2563. }
  2564. uclass_foreach_dev(dev, uc) {
  2565. ret = device_probe(dev);
  2566. if (ret)
  2567. pr_err("%s - probe failed: %d\n", dev->name, ret);
  2568. }
  2569. return 0;
  2570. }
  2571. #else
  2572. static int mmc_probe(struct bd_info *bis)
  2573. {
  2574. if (board_mmc_init(bis) < 0)
  2575. cpu_mmc_init(bis);
  2576. return 0;
  2577. }
  2578. #endif
  2579. int mmc_initialize(struct bd_info *bis)
  2580. {
  2581. static int initialized = 0;
  2582. int ret;
  2583. if (initialized) /* Avoid initializing mmc multiple times */
  2584. return 0;
  2585. initialized = 1;
  2586. #if !CONFIG_IS_ENABLED(BLK)
  2587. #if !CONFIG_IS_ENABLED(MMC_TINY)
  2588. mmc_list_init();
  2589. #endif
  2590. #endif
  2591. ret = mmc_probe(bis);
  2592. if (ret)
  2593. return ret;
  2594. #ifndef CONFIG_SPL_BUILD
  2595. print_mmc_devices(',');
  2596. #endif
  2597. mmc_do_preinit();
  2598. return 0;
  2599. }
  2600. #if CONFIG_IS_ENABLED(DM_MMC)
  2601. int mmc_init_device(int num)
  2602. {
  2603. struct udevice *dev;
  2604. struct mmc *m;
  2605. int ret;
  2606. if (uclass_get_device_by_seq(UCLASS_MMC, num, &dev)) {
  2607. ret = uclass_get_device(UCLASS_MMC, num, &dev);
  2608. if (ret)
  2609. return ret;
  2610. }
  2611. m = mmc_get_mmc_dev(dev);
  2612. m->user_speed_mode = MMC_MODES_END; /* Initialising user set speed mode */
  2613. if (!m)
  2614. return 0;
  2615. if (m->preinit)
  2616. mmc_start_init(m);
  2617. return 0;
  2618. }
  2619. #endif
  2620. #ifdef CONFIG_CMD_BKOPS_ENABLE
  2621. int mmc_set_bkops_enable(struct mmc *mmc)
  2622. {
  2623. int err;
  2624. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  2625. err = mmc_send_ext_csd(mmc, ext_csd);
  2626. if (err) {
  2627. puts("Could not get ext_csd register values\n");
  2628. return err;
  2629. }
  2630. if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
  2631. puts("Background operations not supported on device\n");
  2632. return -EMEDIUMTYPE;
  2633. }
  2634. if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
  2635. puts("Background operations already enabled\n");
  2636. return 0;
  2637. }
  2638. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
  2639. if (err) {
  2640. puts("Failed to enable manual background operations\n");
  2641. return err;
  2642. }
  2643. puts("Enabled manual background operations\n");
  2644. return 0;
  2645. }
  2646. #endif
  2647. __weak int mmc_get_env_dev(void)
  2648. {
  2649. #ifdef CONFIG_SYS_MMC_ENV_DEV
  2650. return CONFIG_SYS_MMC_ENV_DEV;
  2651. #else
  2652. return 0;
  2653. #endif
  2654. }