jz_mmc.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Ingenic JZ MMC driver
  4. *
  5. * Copyright (c) 2013 Imagination Technologies
  6. * Author: Paul Burton <paul.burton@imgtec.com>
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <mmc.h>
  11. #include <asm/global_data.h>
  12. #include <asm/io.h>
  13. #include <asm/unaligned.h>
  14. #include <errno.h>
  15. #include <dm/device_compat.h>
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. #include <mach/jz4780.h>
  19. #include <wait_bit.h>
  20. /* Registers */
  21. #define MSC_STRPCL 0x000
  22. #define MSC_STAT 0x004
  23. #define MSC_CLKRT 0x008
  24. #define MSC_CMDAT 0x00c
  25. #define MSC_RESTO 0x010
  26. #define MSC_RDTO 0x014
  27. #define MSC_BLKLEN 0x018
  28. #define MSC_NOB 0x01c
  29. #define MSC_SNOB 0x020
  30. #define MSC_IMASK 0x024
  31. #define MSC_IREG 0x028
  32. #define MSC_CMD 0x02c
  33. #define MSC_ARG 0x030
  34. #define MSC_RES 0x034
  35. #define MSC_RXFIFO 0x038
  36. #define MSC_TXFIFO 0x03c
  37. #define MSC_LPM 0x040
  38. #define MSC_DMAC 0x044
  39. #define MSC_DMANDA 0x048
  40. #define MSC_DMADA 0x04c
  41. #define MSC_DMALEN 0x050
  42. #define MSC_DMACMD 0x054
  43. #define MSC_CTRL2 0x058
  44. #define MSC_RTCNT 0x05c
  45. #define MSC_DBG 0x0fc
  46. /* MSC Clock and Control Register (MSC_STRPCL) */
  47. #define MSC_STRPCL_EXIT_MULTIPLE BIT(7)
  48. #define MSC_STRPCL_EXIT_TRANSFER BIT(6)
  49. #define MSC_STRPCL_START_READWAIT BIT(5)
  50. #define MSC_STRPCL_STOP_READWAIT BIT(4)
  51. #define MSC_STRPCL_RESET BIT(3)
  52. #define MSC_STRPCL_START_OP BIT(2)
  53. #define MSC_STRPCL_CLOCK_CONTROL_STOP BIT(0)
  54. #define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
  55. /* MSC Status Register (MSC_STAT) */
  56. #define MSC_STAT_AUTO_CMD_DONE BIT(31)
  57. #define MSC_STAT_IS_RESETTING BIT(15)
  58. #define MSC_STAT_SDIO_INT_ACTIVE BIT(14)
  59. #define MSC_STAT_PRG_DONE BIT(13)
  60. #define MSC_STAT_DATA_TRAN_DONE BIT(12)
  61. #define MSC_STAT_END_CMD_RES BIT(11)
  62. #define MSC_STAT_DATA_FIFO_AFULL BIT(10)
  63. #define MSC_STAT_IS_READWAIT BIT(9)
  64. #define MSC_STAT_CLK_EN BIT(8)
  65. #define MSC_STAT_DATA_FIFO_FULL BIT(7)
  66. #define MSC_STAT_DATA_FIFO_EMPTY BIT(6)
  67. #define MSC_STAT_CRC_RES_ERR BIT(5)
  68. #define MSC_STAT_CRC_READ_ERROR BIT(4)
  69. #define MSC_STAT_CRC_WRITE_ERROR BIT(2)
  70. #define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
  71. #define MSC_STAT_TIME_OUT_RES BIT(1)
  72. #define MSC_STAT_TIME_OUT_READ BIT(0)
  73. /* MSC Bus Clock Control Register (MSC_CLKRT) */
  74. #define MSC_CLKRT_CLK_RATE_MASK 0x7
  75. /* MSC Command Sequence Control Register (MSC_CMDAT) */
  76. #define MSC_CMDAT_IO_ABORT BIT(11)
  77. #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << 9)
  78. #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << 9)
  79. #define MSC_CMDAT_DMA_EN BIT(8)
  80. #define MSC_CMDAT_INIT BIT(7)
  81. #define MSC_CMDAT_BUSY BIT(6)
  82. #define MSC_CMDAT_STREAM_BLOCK BIT(5)
  83. #define MSC_CMDAT_WRITE BIT(4)
  84. #define MSC_CMDAT_DATA_EN BIT(3)
  85. #define MSC_CMDAT_RESPONSE_MASK (0x7 << 0)
  86. #define MSC_CMDAT_RESPONSE_NONE (0x0 << 0) /* No response */
  87. #define MSC_CMDAT_RESPONSE_R1 (0x1 << 0) /* Format R1 and R1b */
  88. #define MSC_CMDAT_RESPONSE_R2 (0x2 << 0) /* Format R2 */
  89. #define MSC_CMDAT_RESPONSE_R3 (0x3 << 0) /* Format R3 */
  90. #define MSC_CMDAT_RESPONSE_R4 (0x4 << 0) /* Format R4 */
  91. #define MSC_CMDAT_RESPONSE_R5 (0x5 << 0) /* Format R5 */
  92. #define MSC_CMDAT_RESPONSE_R6 (0x6 << 0) /* Format R6 */
  93. /* MSC Interrupts Mask Register (MSC_IMASK) */
  94. #define MSC_IMASK_TIME_OUT_RES BIT(9)
  95. #define MSC_IMASK_TIME_OUT_READ BIT(8)
  96. #define MSC_IMASK_SDIO BIT(7)
  97. #define MSC_IMASK_TXFIFO_WR_REQ BIT(6)
  98. #define MSC_IMASK_RXFIFO_RD_REQ BIT(5)
  99. #define MSC_IMASK_END_CMD_RES BIT(2)
  100. #define MSC_IMASK_PRG_DONE BIT(1)
  101. #define MSC_IMASK_DATA_TRAN_DONE BIT(0)
  102. /* MSC Interrupts Status Register (MSC_IREG) */
  103. #define MSC_IREG_TIME_OUT_RES BIT(9)
  104. #define MSC_IREG_TIME_OUT_READ BIT(8)
  105. #define MSC_IREG_SDIO BIT(7)
  106. #define MSC_IREG_TXFIFO_WR_REQ BIT(6)
  107. #define MSC_IREG_RXFIFO_RD_REQ BIT(5)
  108. #define MSC_IREG_END_CMD_RES BIT(2)
  109. #define MSC_IREG_PRG_DONE BIT(1)
  110. #define MSC_IREG_DATA_TRAN_DONE BIT(0)
  111. struct jz_mmc_plat {
  112. struct mmc_config cfg;
  113. struct mmc mmc;
  114. };
  115. struct jz_mmc_priv {
  116. void __iomem *regs;
  117. u32 flags;
  118. /* priv flags */
  119. #define JZ_MMC_BUS_WIDTH_MASK 0x3
  120. #define JZ_MMC_BUS_WIDTH_1 0x0
  121. #define JZ_MMC_BUS_WIDTH_4 0x2
  122. #define JZ_MMC_BUS_WIDTH_8 0x3
  123. #define JZ_MMC_SENT_INIT BIT(2)
  124. };
  125. static int jz_mmc_clock_rate(void)
  126. {
  127. return 24000000;
  128. }
  129. #if CONFIG_IS_ENABLED(MMC_WRITE)
  130. static inline void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
  131. {
  132. int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
  133. const void *buf = data->src;
  134. while (sz--) {
  135. u32 val = get_unaligned_le32(buf);
  136. wait_for_bit_le32(priv->regs + MSC_IREG,
  137. MSC_IREG_TXFIFO_WR_REQ,
  138. true, 10000, false);
  139. writel(val, priv->regs + MSC_TXFIFO);
  140. buf += 4;
  141. }
  142. }
  143. #else
  144. static void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
  145. {}
  146. #endif
  147. static inline int jz_mmc_read_data(struct jz_mmc_priv *priv, struct mmc_data *data)
  148. {
  149. int sz = data->blocks * data->blocksize;
  150. void *buf = data->dest;
  151. u32 stat, val;
  152. do {
  153. stat = readl(priv->regs + MSC_STAT);
  154. if (stat & MSC_STAT_TIME_OUT_READ)
  155. return -ETIMEDOUT;
  156. if (stat & MSC_STAT_CRC_READ_ERROR)
  157. return -EINVAL;
  158. if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
  159. udelay(10);
  160. continue;
  161. }
  162. do {
  163. val = readl(priv->regs + MSC_RXFIFO);
  164. if (sz == 1)
  165. *(u8 *)buf = (u8)val;
  166. else if (sz == 2)
  167. put_unaligned_le16(val, buf);
  168. else if (sz >= 4)
  169. put_unaligned_le32(val, buf);
  170. buf += 4;
  171. sz -= 4;
  172. stat = readl(priv->regs + MSC_STAT);
  173. } while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
  174. } while (!(stat & MSC_STAT_DATA_TRAN_DONE));
  175. return 0;
  176. }
  177. static int jz_mmc_send_cmd(struct mmc *mmc, struct jz_mmc_priv *priv,
  178. struct mmc_cmd *cmd, struct mmc_data *data)
  179. {
  180. u32 stat, mask, cmdat = 0;
  181. int i, ret;
  182. /* stop the clock */
  183. writel(MSC_STRPCL_CLOCK_CONTROL_STOP, priv->regs + MSC_STRPCL);
  184. ret = wait_for_bit_le32(priv->regs + MSC_STAT,
  185. MSC_STAT_CLK_EN, false, 10000, false);
  186. if (ret)
  187. return ret;
  188. writel(0, priv->regs + MSC_DMAC);
  189. /* setup command */
  190. writel(cmd->cmdidx, priv->regs + MSC_CMD);
  191. writel(cmd->cmdarg, priv->regs + MSC_ARG);
  192. if (data) {
  193. /* setup data */
  194. cmdat |= MSC_CMDAT_DATA_EN;
  195. if (data->flags & MMC_DATA_WRITE)
  196. cmdat |= MSC_CMDAT_WRITE;
  197. writel(data->blocks, priv->regs + MSC_NOB);
  198. writel(data->blocksize, priv->regs + MSC_BLKLEN);
  199. } else {
  200. writel(0, priv->regs + MSC_NOB);
  201. writel(0, priv->regs + MSC_BLKLEN);
  202. }
  203. /* setup response */
  204. switch (cmd->resp_type) {
  205. case MMC_RSP_NONE:
  206. break;
  207. case MMC_RSP_R1:
  208. case MMC_RSP_R1b:
  209. cmdat |= MSC_CMDAT_RESPONSE_R1;
  210. break;
  211. case MMC_RSP_R2:
  212. cmdat |= MSC_CMDAT_RESPONSE_R2;
  213. break;
  214. case MMC_RSP_R3:
  215. cmdat |= MSC_CMDAT_RESPONSE_R3;
  216. break;
  217. default:
  218. break;
  219. }
  220. if (cmd->resp_type & MMC_RSP_BUSY)
  221. cmdat |= MSC_CMDAT_BUSY;
  222. /* set init for the first command only */
  223. if (!(priv->flags & JZ_MMC_SENT_INIT)) {
  224. cmdat |= MSC_CMDAT_INIT;
  225. priv->flags |= JZ_MMC_SENT_INIT;
  226. }
  227. cmdat |= (priv->flags & JZ_MMC_BUS_WIDTH_MASK) << 9;
  228. /* write the data setup */
  229. writel(cmdat, priv->regs + MSC_CMDAT);
  230. /* unmask interrupts */
  231. mask = 0xffffffff & ~(MSC_IMASK_END_CMD_RES | MSC_IMASK_TIME_OUT_RES);
  232. if (data) {
  233. mask &= ~MSC_IMASK_DATA_TRAN_DONE;
  234. if (data->flags & MMC_DATA_WRITE) {
  235. mask &= ~MSC_IMASK_TXFIFO_WR_REQ;
  236. } else {
  237. mask &= ~(MSC_IMASK_RXFIFO_RD_REQ |
  238. MSC_IMASK_TIME_OUT_READ);
  239. }
  240. }
  241. writel(mask, priv->regs + MSC_IMASK);
  242. /* clear interrupts */
  243. writel(0xffffffff, priv->regs + MSC_IREG);
  244. /* start the command (& the clock) */
  245. writel(MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START,
  246. priv->regs + MSC_STRPCL);
  247. /* wait for completion */
  248. for (i = 0; i < 100; i++) {
  249. stat = readl(priv->regs + MSC_IREG);
  250. stat &= MSC_IREG_END_CMD_RES | MSC_IREG_TIME_OUT_RES;
  251. if (stat)
  252. break;
  253. mdelay(1);
  254. }
  255. writel(stat, priv->regs + MSC_IREG);
  256. if (stat & MSC_IREG_TIME_OUT_RES)
  257. return -ETIMEDOUT;
  258. if (cmd->resp_type & MMC_RSP_PRESENT) {
  259. /* read the response */
  260. if (cmd->resp_type & MMC_RSP_136) {
  261. u16 a, b, c, i;
  262. a = readw(priv->regs + MSC_RES);
  263. for (i = 0; i < 4; i++) {
  264. b = readw(priv->regs + MSC_RES);
  265. c = readw(priv->regs + MSC_RES);
  266. cmd->response[i] =
  267. (a << 24) | (b << 8) | (c >> 8);
  268. a = c;
  269. }
  270. } else {
  271. cmd->response[0] = readw(priv->regs + MSC_RES) << 24;
  272. cmd->response[0] |= readw(priv->regs + MSC_RES) << 8;
  273. cmd->response[0] |= readw(priv->regs + MSC_RES) & 0xff;
  274. }
  275. }
  276. if (data) {
  277. if (data->flags & MMC_DATA_WRITE)
  278. jz_mmc_write_data(priv, data);
  279. else if (data->flags & MMC_DATA_READ) {
  280. ret = jz_mmc_read_data(priv, data);
  281. if (ret)
  282. return ret;
  283. }
  284. }
  285. return 0;
  286. }
  287. static int jz_mmc_set_ios(struct mmc *mmc, struct jz_mmc_priv *priv)
  288. {
  289. u32 real_rate = jz_mmc_clock_rate();
  290. u8 clk_div = 0;
  291. /* calculate clock divide */
  292. while ((real_rate > mmc->clock) && (clk_div < 7)) {
  293. real_rate >>= 1;
  294. clk_div++;
  295. }
  296. writel(clk_div & MSC_CLKRT_CLK_RATE_MASK, priv->regs + MSC_CLKRT);
  297. /* set the bus width for the next command */
  298. priv->flags &= ~JZ_MMC_BUS_WIDTH_MASK;
  299. if (mmc->bus_width == 8)
  300. priv->flags |= JZ_MMC_BUS_WIDTH_8;
  301. else if (mmc->bus_width == 4)
  302. priv->flags |= JZ_MMC_BUS_WIDTH_4;
  303. else
  304. priv->flags |= JZ_MMC_BUS_WIDTH_1;
  305. return 0;
  306. }
  307. static int jz_mmc_core_init(struct mmc *mmc)
  308. {
  309. struct jz_mmc_priv *priv = mmc->priv;
  310. int ret;
  311. /* Reset */
  312. writel(MSC_STRPCL_RESET, priv->regs + MSC_STRPCL);
  313. ret = wait_for_bit_le32(priv->regs + MSC_STAT,
  314. MSC_STAT_IS_RESETTING, false, 10000, false);
  315. if (ret)
  316. return ret;
  317. /* Maximum timeouts */
  318. writel(0xffff, priv->regs + MSC_RESTO);
  319. writel(0xffffffff, priv->regs + MSC_RDTO);
  320. /* Enable low power mode */
  321. writel(0x1, priv->regs + MSC_LPM);
  322. return 0;
  323. }
  324. #if !CONFIG_IS_ENABLED(DM_MMC)
  325. static int jz_mmc_legacy_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  326. struct mmc_data *data)
  327. {
  328. struct jz_mmc_priv *priv = mmc->priv;
  329. return jz_mmc_send_cmd(mmc, priv, cmd, data);
  330. }
  331. static int jz_mmc_legacy_set_ios(struct mmc *mmc)
  332. {
  333. struct jz_mmc_priv *priv = mmc->priv;
  334. return jz_mmc_set_ios(mmc, priv);
  335. };
  336. static const struct mmc_ops jz_msc_ops = {
  337. .send_cmd = jz_mmc_legacy_send_cmd,
  338. .set_ios = jz_mmc_legacy_set_ios,
  339. .init = jz_mmc_core_init,
  340. };
  341. static struct jz_mmc_priv jz_mmc_priv_static;
  342. static struct jz_mmc_plat jz_mmc_plat_static = {
  343. .cfg = {
  344. .name = "MSC",
  345. .ops = &jz_msc_ops,
  346. .voltages = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
  347. MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
  348. MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36,
  349. .host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS,
  350. .f_min = 375000,
  351. .f_max = 48000000,
  352. .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  353. },
  354. };
  355. int jz_mmc_init(void __iomem *base)
  356. {
  357. struct mmc *mmc;
  358. jz_mmc_priv_static.regs = base;
  359. mmc = mmc_create(&jz_mmc_plat_static.cfg, &jz_mmc_priv_static);
  360. return mmc ? 0 : -ENODEV;
  361. }
  362. #else /* CONFIG_DM_MMC */
  363. #include <dm.h>
  364. DECLARE_GLOBAL_DATA_PTR;
  365. static int jz_mmc_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  366. struct mmc_data *data)
  367. {
  368. struct jz_mmc_priv *priv = dev_get_priv(dev);
  369. struct mmc *mmc = mmc_get_mmc_dev(dev);
  370. return jz_mmc_send_cmd(mmc, priv, cmd, data);
  371. }
  372. static int jz_mmc_dm_set_ios(struct udevice *dev)
  373. {
  374. struct jz_mmc_priv *priv = dev_get_priv(dev);
  375. struct mmc *mmc = mmc_get_mmc_dev(dev);
  376. return jz_mmc_set_ios(mmc, priv);
  377. };
  378. static const struct dm_mmc_ops jz_msc_ops = {
  379. .send_cmd = jz_mmc_dm_send_cmd,
  380. .set_ios = jz_mmc_dm_set_ios,
  381. };
  382. static int jz_mmc_of_to_plat(struct udevice *dev)
  383. {
  384. struct jz_mmc_priv *priv = dev_get_priv(dev);
  385. struct jz_mmc_plat *plat = dev_get_plat(dev);
  386. struct mmc_config *cfg;
  387. int ret;
  388. priv->regs = map_physmem(dev_read_addr(dev), 0x100, MAP_NOCACHE);
  389. cfg = &plat->cfg;
  390. cfg->name = "MSC";
  391. cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
  392. ret = mmc_of_parse(dev, cfg);
  393. if (ret < 0) {
  394. dev_err(dev, "failed to parse host caps\n");
  395. return ret;
  396. }
  397. cfg->f_min = 400000;
  398. cfg->f_max = 52000000;
  399. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  400. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  401. return 0;
  402. }
  403. static int jz_mmc_bind(struct udevice *dev)
  404. {
  405. struct jz_mmc_plat *plat = dev_get_plat(dev);
  406. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  407. }
  408. static int jz_mmc_probe(struct udevice *dev)
  409. {
  410. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  411. struct jz_mmc_priv *priv = dev_get_priv(dev);
  412. struct jz_mmc_plat *plat = dev_get_plat(dev);
  413. plat->mmc.priv = priv;
  414. upriv->mmc = &plat->mmc;
  415. return jz_mmc_core_init(&plat->mmc);
  416. }
  417. static const struct udevice_id jz_mmc_ids[] = {
  418. { .compatible = "ingenic,jz4780-mmc" },
  419. { }
  420. };
  421. U_BOOT_DRIVER(jz_mmc_drv) = {
  422. .name = "jz_mmc",
  423. .id = UCLASS_MMC,
  424. .of_match = jz_mmc_ids,
  425. .of_to_plat = jz_mmc_of_to_plat,
  426. .bind = jz_mmc_bind,
  427. .probe = jz_mmc_probe,
  428. .priv_auto = sizeof(struct jz_mmc_priv),
  429. .plat_auto = sizeof(struct jz_mmc_plat),
  430. .ops = &jz_msc_ops,
  431. };
  432. #endif /* CONFIG_DM_MMC */