gen_atmel_mci.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010
  4. * Rob Emanuele <rob@emanuele.us>
  5. * Reinhard Meyer, EMK Elektronik <reinhard.meyer@emk-elektronik.de>
  6. *
  7. * Original Driver:
  8. * Copyright (C) 2004-2006 Atmel Corporation
  9. */
  10. #include <common.h>
  11. #include <clk.h>
  12. #include <dm.h>
  13. #include <log.h>
  14. #include <mmc.h>
  15. #include <part.h>
  16. #include <malloc.h>
  17. #include <asm/io.h>
  18. #include <linux/delay.h>
  19. #include <linux/errno.h>
  20. #include <asm/byteorder.h>
  21. #include <asm/arch/clk.h>
  22. #include <asm/arch/hardware.h>
  23. #include "atmel_mci.h"
  24. #ifndef CONFIG_SYS_MMC_CLK_OD
  25. # define CONFIG_SYS_MMC_CLK_OD 150000
  26. #endif
  27. #define MMC_DEFAULT_BLKLEN 512
  28. #if defined(CONFIG_ATMEL_MCI_PORTB)
  29. # define MCI_BUS 1
  30. #else
  31. # define MCI_BUS 0
  32. #endif
  33. #ifdef CONFIG_DM_MMC
  34. struct atmel_mci_plat {
  35. struct mmc mmc;
  36. struct mmc_config cfg;
  37. struct atmel_mci *mci;
  38. };
  39. #endif
  40. struct atmel_mci_priv {
  41. #ifndef CONFIG_DM_MMC
  42. struct mmc_config cfg;
  43. struct atmel_mci *mci;
  44. #endif
  45. unsigned int initialized:1;
  46. unsigned int curr_clk;
  47. #ifdef CONFIG_DM_MMC
  48. ulong bus_clk_rate;
  49. #endif
  50. };
  51. /* Read Atmel MCI IP version */
  52. static unsigned int atmel_mci_get_version(struct atmel_mci *mci)
  53. {
  54. return readl(&mci->version) & 0x00000fff;
  55. }
  56. /*
  57. * Print command and status:
  58. *
  59. * - always when DEBUG is defined
  60. * - on command errors
  61. */
  62. static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg)
  63. {
  64. debug("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n",
  65. cmdr, cmdr & 0x3F, arg, status, msg);
  66. }
  67. static inline void mci_set_blklen(atmel_mci_t *mci, int blklen)
  68. {
  69. unsigned int version = atmel_mci_get_version(mci);
  70. blklen &= 0xfffc;
  71. /* MCI IP version >= 0x200 has blkr */
  72. if (version >= 0x200)
  73. writel(MMCI_BFINS(BLKLEN, blklen, readl(&mci->blkr)),
  74. &mci->blkr);
  75. else
  76. writel(MMCI_BFINS(BLKLEN, blklen, readl(&mci->mr)), &mci->mr);
  77. }
  78. /* Setup for MCI Clock and Block Size */
  79. #ifdef CONFIG_DM_MMC
  80. static void mci_set_mode(struct udevice *dev, u32 hz, u32 blklen)
  81. {
  82. struct atmel_mci_plat *plat = dev_get_plat(dev);
  83. struct atmel_mci_priv *priv = dev_get_priv(dev);
  84. struct mmc *mmc = &plat->mmc;
  85. u32 bus_hz = priv->bus_clk_rate;
  86. atmel_mci_t *mci = plat->mci;
  87. #else
  88. static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
  89. {
  90. struct atmel_mci_priv *priv = mmc->priv;
  91. u32 bus_hz = get_mci_clk_rate();
  92. atmel_mci_t *mci = priv->mci;
  93. #endif
  94. u32 clkdiv = 255;
  95. unsigned int version = atmel_mci_get_version(mci);
  96. u32 clkodd = 0;
  97. u32 mr;
  98. debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n",
  99. bus_hz, hz, blklen);
  100. if (hz > 0) {
  101. if (version >= 0x500) {
  102. clkdiv = DIV_ROUND_UP(bus_hz, hz) - 2;
  103. if (clkdiv > 511)
  104. clkdiv = 511;
  105. clkodd = clkdiv & 1;
  106. clkdiv >>= 1;
  107. debug("mci: setting clock %u Hz, block size %u\n",
  108. bus_hz / (clkdiv * 2 + clkodd + 2), blklen);
  109. } else {
  110. /* find clkdiv yielding a rate <= than requested */
  111. for (clkdiv = 0; clkdiv < 255; clkdiv++) {
  112. if ((bus_hz / (clkdiv + 1) / 2) <= hz)
  113. break;
  114. }
  115. debug("mci: setting clock %u Hz, block size %u\n",
  116. (bus_hz / (clkdiv + 1)) / 2, blklen);
  117. }
  118. }
  119. if (version >= 0x500)
  120. priv->curr_clk = bus_hz / (clkdiv * 2 + clkodd + 2);
  121. else
  122. priv->curr_clk = (bus_hz / (clkdiv + 1)) / 2;
  123. mr = MMCI_BF(CLKDIV, clkdiv);
  124. /* MCI IP version >= 0x200 has R/WPROOF */
  125. if (version >= 0x200)
  126. mr |= MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF);
  127. /*
  128. * MCI IP version >= 0x500 use bit 16 as clkodd.
  129. * MCI IP version < 0x500 use upper 16 bits for blklen.
  130. */
  131. if (version >= 0x500)
  132. mr |= MMCI_BF(CLKODD, clkodd);
  133. writel(mr, &mci->mr);
  134. mci_set_blklen(mci, blklen);
  135. if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS)
  136. writel(MMCI_BIT(HSMODE), &mci->cfg);
  137. priv->initialized = 1;
  138. }
  139. /* Return the CMDR with flags for a given command and data packet */
  140. static u32 mci_encode_cmd(
  141. struct mmc_cmd *cmd, struct mmc_data *data, u32* error_flags)
  142. {
  143. u32 cmdr = 0;
  144. /* Default Flags for Errors */
  145. *error_flags |= (MMCI_BIT(DTOE) | MMCI_BIT(RDIRE) | MMCI_BIT(RENDE) |
  146. MMCI_BIT(RINDE) | MMCI_BIT(RTOE));
  147. /* Default Flags for the Command */
  148. cmdr |= MMCI_BIT(MAXLAT);
  149. if (data) {
  150. cmdr |= MMCI_BF(TRCMD, 1);
  151. if (data->blocks > 1)
  152. cmdr |= MMCI_BF(TRTYP, 1);
  153. if (data->flags & MMC_DATA_READ)
  154. cmdr |= MMCI_BIT(TRDIR);
  155. }
  156. if (cmd->resp_type & MMC_RSP_CRC)
  157. *error_flags |= MMCI_BIT(RCRCE);
  158. if (cmd->resp_type & MMC_RSP_136)
  159. cmdr |= MMCI_BF(RSPTYP, 2);
  160. else if (cmd->resp_type & MMC_RSP_BUSY)
  161. cmdr |= MMCI_BF(RSPTYP, 3);
  162. else if (cmd->resp_type & MMC_RSP_PRESENT)
  163. cmdr |= MMCI_BF(RSPTYP, 1);
  164. return cmdr | MMCI_BF(CMDNB, cmd->cmdidx);
  165. }
  166. /* Entered into function pointer in mci_send_cmd */
  167. static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags)
  168. {
  169. u32 status;
  170. do {
  171. status = readl(&mci->sr);
  172. if (status & (error_flags | MMCI_BIT(OVRE)))
  173. goto io_fail;
  174. } while (!(status & MMCI_BIT(RXRDY)));
  175. if (status & MMCI_BIT(RXRDY)) {
  176. *data = readl(&mci->rdr);
  177. status = 0;
  178. }
  179. io_fail:
  180. return status;
  181. }
  182. /* Entered into function pointer in mci_send_cmd */
  183. static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags)
  184. {
  185. u32 status;
  186. do {
  187. status = readl(&mci->sr);
  188. if (status & (error_flags | MMCI_BIT(UNRE)))
  189. goto io_fail;
  190. } while (!(status & MMCI_BIT(TXRDY)));
  191. if (status & MMCI_BIT(TXRDY)) {
  192. writel(*data, &mci->tdr);
  193. status = 0;
  194. }
  195. io_fail:
  196. return status;
  197. }
  198. /*
  199. * Entered into mmc structure during driver init
  200. *
  201. * Sends a command out on the bus and deals with the block data.
  202. * Takes the mmc pointer, a command pointer, and an optional data pointer.
  203. */
  204. #ifdef CONFIG_DM_MMC
  205. static int atmel_mci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  206. struct mmc_data *data)
  207. {
  208. struct atmel_mci_plat *plat = dev_get_plat(dev);
  209. struct atmel_mci_priv *priv = dev_get_priv(dev);
  210. atmel_mci_t *mci = plat->mci;
  211. #else
  212. static int
  213. mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
  214. {
  215. struct atmel_mci_priv *priv = mmc->priv;
  216. atmel_mci_t *mci = priv->mci;
  217. #endif
  218. u32 cmdr;
  219. u32 error_flags = 0;
  220. u32 status;
  221. if (!priv->initialized) {
  222. puts ("MCI not initialized!\n");
  223. return -ECOMM;
  224. }
  225. /* Figure out the transfer arguments */
  226. cmdr = mci_encode_cmd(cmd, data, &error_flags);
  227. mci_set_blklen(mci, data->blocksize);
  228. /* For multi blocks read/write, set the block register */
  229. if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
  230. || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
  231. writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize),
  232. &mci->blkr);
  233. /* Send the command */
  234. writel(cmd->cmdarg, &mci->argr);
  235. writel(cmdr, &mci->cmdr);
  236. #ifdef DEBUG
  237. dump_cmd(cmdr, cmd->cmdarg, 0, "DEBUG");
  238. #endif
  239. /* Wait for the command to complete */
  240. while (!((status = readl(&mci->sr)) & MMCI_BIT(CMDRDY)));
  241. if ((status & error_flags) & MMCI_BIT(RTOE)) {
  242. dump_cmd(cmdr, cmd->cmdarg, status, "Command Time Out");
  243. return -ETIMEDOUT;
  244. } else if (status & error_flags) {
  245. dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed");
  246. return -ECOMM;
  247. }
  248. /* Copy the response to the response buffer */
  249. if (cmd->resp_type & MMC_RSP_136) {
  250. cmd->response[0] = readl(&mci->rspr);
  251. cmd->response[1] = readl(&mci->rspr1);
  252. cmd->response[2] = readl(&mci->rspr2);
  253. cmd->response[3] = readl(&mci->rspr3);
  254. } else
  255. cmd->response[0] = readl(&mci->rspr);
  256. /* transfer all of the blocks */
  257. if (data) {
  258. u32 word_count, block_count;
  259. u32* ioptr;
  260. u32 i;
  261. u32 (*mci_data_op)
  262. (atmel_mci_t *mci, u32* data, u32 error_flags);
  263. if (data->flags & MMC_DATA_READ) {
  264. mci_data_op = mci_data_read;
  265. ioptr = (u32*)data->dest;
  266. } else {
  267. mci_data_op = mci_data_write;
  268. ioptr = (u32*)data->src;
  269. }
  270. status = 0;
  271. for (block_count = 0;
  272. block_count < data->blocks && !status;
  273. block_count++) {
  274. word_count = 0;
  275. do {
  276. status = mci_data_op(mci, ioptr, error_flags);
  277. word_count++;
  278. ioptr++;
  279. } while (!status && word_count < (data->blocksize/4));
  280. #ifdef DEBUG
  281. if (data->flags & MMC_DATA_READ)
  282. {
  283. u32 cnt = word_count * 4;
  284. printf("Read Data:\n");
  285. print_buffer(0, data->dest + cnt * block_count,
  286. 1, cnt, 0);
  287. }
  288. #endif
  289. if (status) {
  290. dump_cmd(cmdr, cmd->cmdarg, status,
  291. "Data Transfer Failed");
  292. return -ECOMM;
  293. }
  294. }
  295. /* Wait for Transfer End */
  296. i = 0;
  297. do {
  298. status = readl(&mci->sr);
  299. if (status & error_flags) {
  300. dump_cmd(cmdr, cmd->cmdarg, status,
  301. "DTIP Wait Failed");
  302. return -ECOMM;
  303. }
  304. i++;
  305. } while ((status & MMCI_BIT(DTIP)) && i < 10000);
  306. if (status & MMCI_BIT(DTIP)) {
  307. dump_cmd(cmdr, cmd->cmdarg, status,
  308. "XFER DTIP never unset, ignoring");
  309. }
  310. }
  311. /*
  312. * After the switch command, wait for 8 clocks before the next
  313. * command
  314. */
  315. if (cmd->cmdidx == MMC_CMD_SWITCH)
  316. udelay(8*1000000 / priv->curr_clk); /* 8 clk in us */
  317. return 0;
  318. }
  319. #ifdef CONFIG_DM_MMC
  320. static int atmel_mci_set_ios(struct udevice *dev)
  321. {
  322. struct atmel_mci_plat *plat = dev_get_plat(dev);
  323. struct mmc *mmc = mmc_get_mmc_dev(dev);
  324. atmel_mci_t *mci = plat->mci;
  325. #else
  326. /* Entered into mmc structure during driver init */
  327. static int mci_set_ios(struct mmc *mmc)
  328. {
  329. struct atmel_mci_priv *priv = mmc->priv;
  330. atmel_mci_t *mci = priv->mci;
  331. #endif
  332. int bus_width = mmc->bus_width;
  333. unsigned int version = atmel_mci_get_version(mci);
  334. int busw;
  335. /* Set the clock speed */
  336. #ifdef CONFIG_DM_MMC
  337. mci_set_mode(dev, mmc->clock, MMC_DEFAULT_BLKLEN);
  338. #else
  339. mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN);
  340. #endif
  341. /*
  342. * set the bus width and select slot for this interface
  343. * there is no capability for multiple slots on the same interface yet
  344. */
  345. if ((version & 0xf00) >= 0x300) {
  346. switch (bus_width) {
  347. case 8:
  348. busw = 3;
  349. break;
  350. case 4:
  351. busw = 2;
  352. break;
  353. default:
  354. busw = 0;
  355. break;
  356. }
  357. writel(busw << 6 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
  358. } else {
  359. busw = (bus_width == 4) ? 1 : 0;
  360. writel(busw << 7 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
  361. }
  362. return 0;
  363. }
  364. #ifdef CONFIG_DM_MMC
  365. static int atmel_mci_hw_init(struct udevice *dev)
  366. {
  367. struct atmel_mci_plat *plat = dev_get_plat(dev);
  368. atmel_mci_t *mci = plat->mci;
  369. #else
  370. /* Entered into mmc structure during driver init */
  371. static int mci_init(struct mmc *mmc)
  372. {
  373. struct atmel_mci_priv *priv = mmc->priv;
  374. atmel_mci_t *mci = priv->mci;
  375. #endif
  376. /* Initialize controller */
  377. writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */
  378. writel(MMCI_BIT(PWSDIS), &mci->cr); /* disable power save */
  379. writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */
  380. writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */
  381. /* This delay can be optimized, but stick with max value */
  382. writel(0x7f, &mci->dtor);
  383. /* Disable Interrupts */
  384. writel(~0UL, &mci->idr);
  385. /* Set default clocks and blocklen */
  386. #ifdef CONFIG_DM_MMC
  387. mci_set_mode(dev, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
  388. #else
  389. mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
  390. #endif
  391. return 0;
  392. }
  393. #ifndef CONFIG_DM_MMC
  394. static const struct mmc_ops atmel_mci_ops = {
  395. .send_cmd = mci_send_cmd,
  396. .set_ios = mci_set_ios,
  397. .init = mci_init,
  398. };
  399. /*
  400. * This is the only exported function
  401. *
  402. * Call it with the MCI register base address
  403. */
  404. int atmel_mci_init(void *regs)
  405. {
  406. struct mmc *mmc;
  407. struct mmc_config *cfg;
  408. struct atmel_mci_priv *priv;
  409. unsigned int version;
  410. priv = calloc(1, sizeof(*priv));
  411. if (!priv)
  412. return -ENOMEM;
  413. cfg = &priv->cfg;
  414. cfg->name = "mci";
  415. cfg->ops = &atmel_mci_ops;
  416. priv->mci = (struct atmel_mci *)regs;
  417. priv->initialized = 0;
  418. /* need to be able to pass these in on a board by board basis */
  419. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  420. version = atmel_mci_get_version(priv->mci);
  421. if ((version & 0xf00) >= 0x300) {
  422. cfg->host_caps = MMC_MODE_8BIT;
  423. cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
  424. }
  425. cfg->host_caps |= MMC_MODE_4BIT;
  426. /*
  427. * min and max frequencies determined by
  428. * max and min of clock divider
  429. */
  430. cfg->f_min = get_mci_clk_rate() / (2*256);
  431. cfg->f_max = get_mci_clk_rate() / (2*1);
  432. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  433. mmc = mmc_create(cfg, priv);
  434. if (mmc == NULL) {
  435. free(priv);
  436. return -ENODEV;
  437. }
  438. /* NOTE: possibly leaking the priv structure */
  439. return 0;
  440. }
  441. #endif
  442. #ifdef CONFIG_DM_MMC
  443. static const struct dm_mmc_ops atmel_mci_mmc_ops = {
  444. .send_cmd = atmel_mci_send_cmd,
  445. .set_ios = atmel_mci_set_ios,
  446. };
  447. static void atmel_mci_setup_cfg(struct udevice *dev)
  448. {
  449. struct atmel_mci_plat *plat = dev_get_plat(dev);
  450. struct atmel_mci_priv *priv = dev_get_priv(dev);
  451. struct mmc_config *cfg;
  452. u32 version;
  453. cfg = &plat->cfg;
  454. cfg->name = "Atmel mci";
  455. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  456. /*
  457. * If the version is above 3.0, the capabilities of the 8-bit
  458. * bus width and high speed are supported.
  459. */
  460. version = atmel_mci_get_version(plat->mci);
  461. if ((version & 0xf00) >= 0x300) {
  462. cfg->host_caps = MMC_MODE_8BIT |
  463. MMC_MODE_HS | MMC_MODE_HS_52MHz;
  464. }
  465. cfg->host_caps |= MMC_MODE_4BIT;
  466. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  467. cfg->f_min = priv->bus_clk_rate / (2 * 256);
  468. cfg->f_max = priv->bus_clk_rate / 2;
  469. }
  470. static int atmel_mci_enable_clk(struct udevice *dev)
  471. {
  472. struct atmel_mci_priv *priv = dev_get_priv(dev);
  473. struct clk clk;
  474. ulong clk_rate;
  475. int ret = 0;
  476. ret = clk_get_by_index(dev, 0, &clk);
  477. if (ret) {
  478. ret = -EINVAL;
  479. goto failed;
  480. }
  481. ret = clk_enable(&clk);
  482. if (ret)
  483. goto failed;
  484. clk_rate = clk_get_rate(&clk);
  485. if (!clk_rate) {
  486. ret = -EINVAL;
  487. goto failed;
  488. }
  489. priv->bus_clk_rate = clk_rate;
  490. failed:
  491. clk_free(&clk);
  492. return ret;
  493. }
  494. static int atmel_mci_probe(struct udevice *dev)
  495. {
  496. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  497. struct atmel_mci_plat *plat = dev_get_plat(dev);
  498. struct mmc *mmc;
  499. int ret;
  500. ret = atmel_mci_enable_clk(dev);
  501. if (ret)
  502. return ret;
  503. plat->mci = dev_read_addr_ptr(dev);
  504. atmel_mci_setup_cfg(dev);
  505. mmc = &plat->mmc;
  506. mmc->cfg = &plat->cfg;
  507. mmc->dev = dev;
  508. upriv->mmc = mmc;
  509. atmel_mci_hw_init(dev);
  510. return 0;
  511. }
  512. static int atmel_mci_bind(struct udevice *dev)
  513. {
  514. struct atmel_mci_plat *plat = dev_get_plat(dev);
  515. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  516. }
  517. static const struct udevice_id atmel_mci_ids[] = {
  518. { .compatible = "atmel,hsmci" },
  519. { }
  520. };
  521. U_BOOT_DRIVER(atmel_mci) = {
  522. .name = "atmel-mci",
  523. .id = UCLASS_MMC,
  524. .of_match = atmel_mci_ids,
  525. .bind = atmel_mci_bind,
  526. .probe = atmel_mci_probe,
  527. .plat_auto = sizeof(struct atmel_mci_plat),
  528. .priv_auto = sizeof(struct atmel_mci_priv),
  529. .ops = &atmel_mci_mmc_ops,
  530. };
  531. #endif