ftsdc010_mci.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Faraday MMC/SD Host Controller
  4. *
  5. * (C) Copyright 2010 Faraday Technology
  6. * Dante Su <dantesu@faraday-tech.com>
  7. *
  8. * Copyright 2018 Andes Technology, Inc.
  9. * Author: Rick Chen (rick@andestech.com)
  10. */
  11. #include <common.h>
  12. #include <clk.h>
  13. #include <log.h>
  14. #include <malloc.h>
  15. #include <part.h>
  16. #include <mmc.h>
  17. #include <asm/global_data.h>
  18. #include <linux/bitops.h>
  19. #include <linux/io.h>
  20. #include <linux/errno.h>
  21. #include <asm/byteorder.h>
  22. #include <faraday/ftsdc010.h>
  23. #include "ftsdc010_mci.h"
  24. #include <dm.h>
  25. #include <dt-structs.h>
  26. #include <errno.h>
  27. #include <mapmem.h>
  28. #include <pwrseq.h>
  29. #include <syscon.h>
  30. #include <linux/err.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
  33. #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
  34. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  35. struct ftsdc010 {
  36. fdt32_t bus_width;
  37. bool cap_mmc_highspeed;
  38. bool cap_sd_highspeed;
  39. fdt32_t clock_freq_min_max[2];
  40. struct phandle_2_cell clocks[4];
  41. fdt32_t fifo_depth;
  42. fdt32_t reg[2];
  43. };
  44. #endif
  45. struct ftsdc010_plat {
  46. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  47. struct ftsdc010 dtplat;
  48. #endif
  49. struct mmc_config cfg;
  50. struct mmc mmc;
  51. };
  52. struct ftsdc_priv {
  53. struct clk clk;
  54. struct ftsdc010_chip chip;
  55. int fifo_depth;
  56. bool fifo_mode;
  57. u32 minmax[2];
  58. };
  59. static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
  60. {
  61. struct ftsdc010_chip *chip = mmc->priv;
  62. struct ftsdc010_mmc __iomem *regs = chip->regs;
  63. int ret = -ETIMEDOUT;
  64. uint32_t ts, st;
  65. uint32_t cmd = FTSDC010_CMD_IDX(mmc_cmd->cmdidx);
  66. uint32_t arg = mmc_cmd->cmdarg;
  67. uint32_t flags = mmc_cmd->resp_type;
  68. cmd |= FTSDC010_CMD_CMD_EN;
  69. if (chip->acmd) {
  70. cmd |= FTSDC010_CMD_APP_CMD;
  71. chip->acmd = 0;
  72. }
  73. if (flags & MMC_RSP_PRESENT)
  74. cmd |= FTSDC010_CMD_NEED_RSP;
  75. if (flags & MMC_RSP_136)
  76. cmd |= FTSDC010_CMD_LONG_RSP;
  77. writel(FTSDC010_STATUS_RSP_MASK | FTSDC010_STATUS_CMD_SEND,
  78. &regs->clr);
  79. writel(arg, &regs->argu);
  80. writel(cmd, &regs->cmd);
  81. if (!(flags & (MMC_RSP_PRESENT | MMC_RSP_136))) {
  82. for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
  83. if (readl(&regs->status) & FTSDC010_STATUS_CMD_SEND) {
  84. writel(FTSDC010_STATUS_CMD_SEND, &regs->clr);
  85. ret = 0;
  86. break;
  87. }
  88. }
  89. } else {
  90. st = 0;
  91. for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
  92. st = readl(&regs->status);
  93. writel(st & FTSDC010_STATUS_RSP_MASK, &regs->clr);
  94. if (st & FTSDC010_STATUS_RSP_MASK)
  95. break;
  96. }
  97. if (st & FTSDC010_STATUS_RSP_CRC_OK) {
  98. if (flags & MMC_RSP_136) {
  99. mmc_cmd->response[0] = readl(&regs->rsp3);
  100. mmc_cmd->response[1] = readl(&regs->rsp2);
  101. mmc_cmd->response[2] = readl(&regs->rsp1);
  102. mmc_cmd->response[3] = readl(&regs->rsp0);
  103. } else {
  104. mmc_cmd->response[0] = readl(&regs->rsp0);
  105. }
  106. ret = 0;
  107. } else {
  108. debug("ftsdc010: rsp err (cmd=%d, st=0x%x)\n",
  109. mmc_cmd->cmdidx, st);
  110. }
  111. }
  112. if (ret) {
  113. debug("ftsdc010: cmd timeout (op code=%d)\n",
  114. mmc_cmd->cmdidx);
  115. } else if (mmc_cmd->cmdidx == MMC_CMD_APP_CMD) {
  116. chip->acmd = 1;
  117. }
  118. return ret;
  119. }
  120. static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate)
  121. {
  122. struct ftsdc010_chip *chip = mmc->priv;
  123. struct ftsdc010_mmc __iomem *regs = chip->regs;
  124. uint32_t div;
  125. for (div = 0; div < 0x7f; ++div) {
  126. if (rate >= chip->sclk / (2 * (div + 1)))
  127. break;
  128. }
  129. chip->rate = chip->sclk / (2 * (div + 1));
  130. writel(FTSDC010_CCR_CLK_DIV(div), &regs->ccr);
  131. if (IS_SD(mmc)) {
  132. setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_SD);
  133. if (chip->rate > 25000000)
  134. setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD);
  135. else
  136. clrbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD);
  137. }
  138. }
  139. static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
  140. {
  141. int ret = -ETIMEDOUT;
  142. uint32_t st, timeout = 10000000;
  143. while (timeout--) {
  144. st = readl(&regs->status);
  145. if (!(st & mask))
  146. continue;
  147. writel(st & mask, &regs->clr);
  148. ret = 0;
  149. break;
  150. }
  151. if (ret){
  152. debug("ftsdc010: wait st(0x%x) timeout\n", mask);
  153. }
  154. return ret;
  155. }
  156. /*
  157. * u-boot mmc api
  158. */
  159. static int ftsdc010_request(struct udevice *dev, struct mmc_cmd *cmd,
  160. struct mmc_data *data)
  161. {
  162. struct mmc *mmc = mmc_get_mmc_dev(dev);
  163. int ret = -EOPNOTSUPP;
  164. uint32_t len = 0;
  165. struct ftsdc010_chip *chip = mmc->priv;
  166. struct ftsdc010_mmc __iomem *regs = chip->regs;
  167. if (data && (data->flags & MMC_DATA_WRITE) && chip->wprot) {
  168. printf("ftsdc010: the card is write protected!\n");
  169. return ret;
  170. }
  171. if (data) {
  172. uint32_t dcr;
  173. len = data->blocksize * data->blocks;
  174. /* 1. data disable + fifo reset */
  175. dcr = 0;
  176. #ifdef CONFIG_FTSDC010_SDIO
  177. dcr |= FTSDC010_DCR_FIFO_RST;
  178. #endif
  179. writel(dcr, &regs->dcr);
  180. /* 2. clear status register */
  181. writel(FTSDC010_STATUS_DATA_MASK | FTSDC010_STATUS_FIFO_URUN
  182. | FTSDC010_STATUS_FIFO_ORUN, &regs->clr);
  183. /* 3. data timeout (1 sec) */
  184. writel(chip->rate, &regs->dtr);
  185. /* 4. data length (bytes) */
  186. writel(len, &regs->dlr);
  187. /* 5. data enable */
  188. dcr = (ffs(data->blocksize) - 1) | FTSDC010_DCR_DATA_EN;
  189. if (data->flags & MMC_DATA_WRITE)
  190. dcr |= FTSDC010_DCR_DATA_WRITE;
  191. writel(dcr, &regs->dcr);
  192. }
  193. ret = ftsdc010_send_cmd(mmc, cmd);
  194. if (ret) {
  195. printf("ftsdc010: CMD%d failed\n", cmd->cmdidx);
  196. return ret;
  197. }
  198. if (!data)
  199. return ret;
  200. if (data->flags & MMC_DATA_WRITE) {
  201. const uint8_t *buf = (const uint8_t *)data->src;
  202. while (len > 0) {
  203. int wlen;
  204. /* wait for tx ready */
  205. ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_URUN);
  206. if (ret)
  207. break;
  208. /* write bytes to ftsdc010 */
  209. for (wlen = 0; wlen < len && wlen < chip->fifo; ) {
  210. writel(*(uint32_t *)buf, &regs->dwr);
  211. buf += 4;
  212. wlen += 4;
  213. }
  214. len -= wlen;
  215. }
  216. } else {
  217. uint8_t *buf = (uint8_t *)data->dest;
  218. while (len > 0) {
  219. int rlen;
  220. /* wait for rx ready */
  221. ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_ORUN);
  222. if (ret)
  223. break;
  224. /* fetch bytes from ftsdc010 */
  225. for (rlen = 0; rlen < len && rlen < chip->fifo; ) {
  226. *(uint32_t *)buf = readl(&regs->dwr);
  227. buf += 4;
  228. rlen += 4;
  229. }
  230. len -= rlen;
  231. }
  232. }
  233. if (!ret) {
  234. ret = ftsdc010_wait(regs,
  235. FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_CRC_OK);
  236. }
  237. return ret;
  238. }
  239. static int ftsdc010_set_ios(struct udevice *dev)
  240. {
  241. struct mmc *mmc = mmc_get_mmc_dev(dev);
  242. struct ftsdc010_chip *chip = mmc->priv;
  243. struct ftsdc010_mmc __iomem *regs = chip->regs;
  244. ftsdc010_clkset(mmc, mmc->clock);
  245. clrbits_le32(&regs->bwr, FTSDC010_BWR_MODE_MASK);
  246. switch (mmc->bus_width) {
  247. case 4:
  248. setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_4BIT);
  249. break;
  250. case 8:
  251. setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_8BIT);
  252. break;
  253. default:
  254. setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_1BIT);
  255. break;
  256. }
  257. return 0;
  258. }
  259. static int ftsdc010_get_cd(struct udevice *dev)
  260. {
  261. struct mmc *mmc = mmc_get_mmc_dev(dev);
  262. struct ftsdc010_chip *chip = mmc->priv;
  263. struct ftsdc010_mmc __iomem *regs = chip->regs;
  264. return !(readl(&regs->status) & FTSDC010_STATUS_CARD_DETECT);
  265. }
  266. static int ftsdc010_get_wp(struct udevice *dev)
  267. {
  268. struct mmc *mmc = mmc_get_mmc_dev(dev);
  269. struct ftsdc010_chip *chip = mmc->priv;
  270. struct ftsdc010_mmc __iomem *regs = chip->regs;
  271. if (readl(&regs->status) & FTSDC010_STATUS_WRITE_PROT) {
  272. printf("ftsdc010: write protected\n");
  273. chip->wprot = 1;
  274. }
  275. return 0;
  276. }
  277. static int ftsdc010_init(struct mmc *mmc)
  278. {
  279. struct ftsdc010_chip *chip = mmc->priv;
  280. struct ftsdc010_mmc __iomem *regs = chip->regs;
  281. uint32_t ts;
  282. chip->fifo = (readl(&regs->feature) & 0xff) << 2;
  283. /* 1. chip reset */
  284. writel(FTSDC010_CMD_SDC_RST, &regs->cmd);
  285. for (ts = get_timer(0); get_timer(ts) < CFG_RST_TIMEOUT; ) {
  286. if (readl(&regs->cmd) & FTSDC010_CMD_SDC_RST)
  287. continue;
  288. break;
  289. }
  290. if (readl(&regs->cmd) & FTSDC010_CMD_SDC_RST) {
  291. printf("ftsdc010: reset failed\n");
  292. return -EOPNOTSUPP;
  293. }
  294. /* 2. enter low speed mode (400k card detection) */
  295. ftsdc010_clkset(mmc, 400000);
  296. /* 3. interrupt disabled */
  297. writel(0, &regs->int_mask);
  298. return 0;
  299. }
  300. static int ftsdc010_probe(struct udevice *dev)
  301. {
  302. struct mmc *mmc = mmc_get_mmc_dev(dev);
  303. return ftsdc010_init(mmc);
  304. }
  305. const struct dm_mmc_ops dm_ftsdc010_mmc_ops = {
  306. .send_cmd = ftsdc010_request,
  307. .set_ios = ftsdc010_set_ios,
  308. .get_cd = ftsdc010_get_cd,
  309. .get_wp = ftsdc010_get_wp,
  310. };
  311. static void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
  312. uint caps, u32 max_clk, u32 min_clk)
  313. {
  314. cfg->name = name;
  315. cfg->f_min = min_clk;
  316. cfg->f_max = max_clk;
  317. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  318. cfg->host_caps = caps;
  319. if (buswidth == 8) {
  320. cfg->host_caps |= MMC_MODE_8BIT;
  321. cfg->host_caps &= ~MMC_MODE_4BIT;
  322. } else {
  323. cfg->host_caps |= MMC_MODE_4BIT;
  324. cfg->host_caps &= ~MMC_MODE_8BIT;
  325. }
  326. cfg->part_type = PART_TYPE_DOS;
  327. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  328. }
  329. static int ftsdc010_mmc_of_to_plat(struct udevice *dev)
  330. {
  331. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  332. struct ftsdc_priv *priv = dev_get_priv(dev);
  333. struct ftsdc010_chip *chip = &priv->chip;
  334. chip->name = dev->name;
  335. chip->ioaddr = dev_read_addr_ptr(dev);
  336. chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  337. "bus-width", 4);
  338. chip->priv = dev;
  339. priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  340. "fifo-depth", 0);
  341. priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
  342. "fifo-mode");
  343. if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
  344. "clock-freq-min-max", priv->minmax, 2)) {
  345. int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  346. "max-frequency", -EINVAL);
  347. if (val < 0)
  348. return val;
  349. priv->minmax[0] = 400000; /* 400 kHz */
  350. priv->minmax[1] = val;
  351. } else {
  352. debug("%s: 'clock-freq-min-max' property was deprecated.\n",
  353. __func__);
  354. }
  355. #endif
  356. chip->sclk = priv->minmax[1];
  357. chip->regs = chip->ioaddr;
  358. return 0;
  359. }
  360. static int ftsdc010_mmc_probe(struct udevice *dev)
  361. {
  362. struct ftsdc010_plat *plat = dev_get_plat(dev);
  363. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  364. struct ftsdc_priv *priv = dev_get_priv(dev);
  365. struct ftsdc010_chip *chip = &priv->chip;
  366. struct udevice *pwr_dev __maybe_unused;
  367. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  368. int ret;
  369. struct ftsdc010 *dtplat = &plat->dtplat;
  370. chip->name = dev->name;
  371. chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
  372. chip->buswidth = dtplat->bus_width;
  373. chip->priv = dev;
  374. chip->dev_index = 1;
  375. memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
  376. ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk);
  377. if (ret < 0)
  378. return ret;
  379. #endif
  380. if (dev_read_bool(dev, "cap-mmc-highspeed") || \
  381. dev_read_bool(dev, "cap-sd-highspeed"))
  382. chip->caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
  383. ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps,
  384. priv->minmax[1] , priv->minmax[0]);
  385. chip->mmc = &plat->mmc;
  386. chip->mmc->priv = &priv->chip;
  387. chip->mmc->dev = dev;
  388. upriv->mmc = chip->mmc;
  389. return ftsdc010_probe(dev);
  390. }
  391. int ftsdc010_mmc_bind(struct udevice *dev)
  392. {
  393. struct ftsdc010_plat *plat = dev_get_plat(dev);
  394. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  395. }
  396. static const struct udevice_id ftsdc010_mmc_ids[] = {
  397. { .compatible = "andestech,atfsdc010" },
  398. { }
  399. };
  400. U_BOOT_DRIVER(ftsdc010_mmc) = {
  401. .name = "ftsdc010_mmc",
  402. .id = UCLASS_MMC,
  403. .of_match = ftsdc010_mmc_ids,
  404. .of_to_plat = ftsdc010_mmc_of_to_plat,
  405. .ops = &dm_ftsdc010_mmc_ops,
  406. .bind = ftsdc010_mmc_bind,
  407. .probe = ftsdc010_mmc_probe,
  408. .priv_auto = sizeof(struct ftsdc_priv),
  409. .plat_auto = sizeof(struct ftsdc010_plat),
  410. };