exynos_dw_mmc.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012 SAMSUNG Electronics
  4. * Jaehoon Chung <jh80.chung@samsung.com>
  5. */
  6. #include <common.h>
  7. #include <dwmmc.h>
  8. #include <fdtdec.h>
  9. #include <asm/global_data.h>
  10. #include <linux/libfdt.h>
  11. #include <malloc.h>
  12. #include <errno.h>
  13. #include <asm/arch/dwmmc.h>
  14. #include <asm/arch/clk.h>
  15. #include <asm/arch/pinmux.h>
  16. #include <asm/arch/power.h>
  17. #include <asm/gpio.h>
  18. #define DWMMC_MAX_CH_NUM 4
  19. #define DWMMC_MAX_FREQ 52000000
  20. #define DWMMC_MIN_FREQ 400000
  21. #define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001
  22. #define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001
  23. #ifdef CONFIG_DM_MMC
  24. #include <dm.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. struct exynos_mmc_plat {
  27. struct mmc_config cfg;
  28. struct mmc mmc;
  29. };
  30. #endif
  31. /* Exynos implmentation specific drver private data */
  32. struct dwmci_exynos_priv_data {
  33. #ifdef CONFIG_DM_MMC
  34. struct dwmci_host host;
  35. #endif
  36. u32 sdr_timing;
  37. };
  38. /*
  39. * Function used as callback function to initialise the
  40. * CLKSEL register for every mmc channel.
  41. */
  42. static int exynos_dwmci_clksel(struct dwmci_host *host)
  43. {
  44. #ifdef CONFIG_DM_MMC
  45. struct dwmci_exynos_priv_data *priv =
  46. container_of(host, struct dwmci_exynos_priv_data, host);
  47. #else
  48. struct dwmci_exynos_priv_data *priv = host->priv;
  49. #endif
  50. dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
  51. return 0;
  52. }
  53. unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
  54. {
  55. unsigned long sclk;
  56. int8_t clk_div;
  57. /*
  58. * Since SDCLKIN is divided inside controller by the DIVRATIO
  59. * value set in the CLKSEL register, we need to use the same output
  60. * clock value to calculate the CLKDIV value.
  61. * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
  62. */
  63. clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
  64. & DWMCI_DIVRATIO_MASK) + 1;
  65. sclk = get_mmc_clk(host->dev_index);
  66. /*
  67. * Assume to know divider value.
  68. * When clock unit is broken, need to set "host->div"
  69. */
  70. return sclk / clk_div / (host->div + 1);
  71. }
  72. static void exynos_dwmci_board_init(struct dwmci_host *host)
  73. {
  74. struct dwmci_exynos_priv_data *priv = host->priv;
  75. if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
  76. dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
  77. dwmci_writel(host, EMMCP_SEND0, 0);
  78. dwmci_writel(host, EMMCP_CTRL0,
  79. MPSCTRL_SECURE_READ_BIT |
  80. MPSCTRL_SECURE_WRITE_BIT |
  81. MPSCTRL_NON_SECURE_READ_BIT |
  82. MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
  83. }
  84. /* Set to timing value at initial time */
  85. if (priv->sdr_timing)
  86. exynos_dwmci_clksel(host);
  87. }
  88. static int exynos_dwmci_core_init(struct dwmci_host *host)
  89. {
  90. unsigned int div;
  91. unsigned long freq, sclk;
  92. if (host->bus_hz)
  93. freq = host->bus_hz;
  94. else
  95. freq = DWMMC_MAX_FREQ;
  96. /* request mmc clock vlaue of 52MHz. */
  97. sclk = get_mmc_clk(host->dev_index);
  98. div = DIV_ROUND_UP(sclk, freq);
  99. /* set the clock divisor for mmc */
  100. set_mmc_clk(host->dev_index, div);
  101. host->name = "EXYNOS DWMMC";
  102. #ifdef CONFIG_EXYNOS5420
  103. host->quirks = DWMCI_QUIRK_DISABLE_SMU;
  104. #endif
  105. host->board_init = exynos_dwmci_board_init;
  106. host->caps = MMC_MODE_DDR_52MHz;
  107. host->clksel = exynos_dwmci_clksel;
  108. host->get_mmc_clk = exynos_dwmci_get_clk;
  109. #ifndef CONFIG_DM_MMC
  110. /* Add the mmc channel to be registered with mmc core */
  111. if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
  112. printf("DWMMC%d registration failed\n", host->dev_index);
  113. return -1;
  114. }
  115. #endif
  116. return 0;
  117. }
  118. static int do_dwmci_init(struct dwmci_host *host)
  119. {
  120. int flag, err;
  121. flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
  122. err = exynos_pinmux_config(host->dev_id, flag);
  123. if (err) {
  124. printf("DWMMC%d not configure\n", host->dev_index);
  125. return err;
  126. }
  127. return exynos_dwmci_core_init(host);
  128. }
  129. static int exynos_dwmci_get_config(const void *blob, int node,
  130. struct dwmci_host *host,
  131. struct dwmci_exynos_priv_data *priv)
  132. {
  133. int err = 0;
  134. u32 base, timing[3];
  135. /* Extract device id for each mmc channel */
  136. host->dev_id = pinmux_decode_periph_id(blob, node);
  137. host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
  138. if (host->dev_index == host->dev_id)
  139. host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
  140. if (host->dev_index > 4) {
  141. printf("DWMMC%d: Can't get the dev index\n", host->dev_index);
  142. return -EINVAL;
  143. }
  144. /* Get the bus width from the device node (Default is 4bit buswidth) */
  145. host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4);
  146. /* Set the base address from the device node */
  147. base = fdtdec_get_addr(blob, node, "reg");
  148. if (!base) {
  149. printf("DWMMC%d: Can't get base address\n", host->dev_index);
  150. return -EINVAL;
  151. }
  152. host->ioaddr = (void *)base;
  153. /* Extract the timing info from the node */
  154. err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
  155. if (err) {
  156. printf("DWMMC%d: Can't get sdr-timings for devider\n",
  157. host->dev_index);
  158. return -EINVAL;
  159. }
  160. priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
  161. DWMCI_SET_DRV_CLK(timing[1]) |
  162. DWMCI_SET_DIV_RATIO(timing[2]));
  163. /* sdr_timing didn't assigned anything, use the default value */
  164. if (!priv->sdr_timing) {
  165. if (host->dev_index == 0)
  166. priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
  167. else if (host->dev_index == 2)
  168. priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
  169. }
  170. host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
  171. host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
  172. host->div = fdtdec_get_int(blob, node, "div", 0);
  173. return 0;
  174. }
  175. #ifdef CONFIG_DM_MMC
  176. static int exynos_dwmmc_probe(struct udevice *dev)
  177. {
  178. struct exynos_mmc_plat *plat = dev_get_plat(dev);
  179. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  180. struct dwmci_exynos_priv_data *priv = dev_get_priv(dev);
  181. struct dwmci_host *host = &priv->host;
  182. int err;
  183. err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host,
  184. priv);
  185. if (err)
  186. return err;
  187. err = do_dwmci_init(host);
  188. if (err)
  189. return err;
  190. dwmci_setup_cfg(&plat->cfg, host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ);
  191. host->mmc = &plat->mmc;
  192. host->mmc->priv = &priv->host;
  193. host->priv = dev;
  194. upriv->mmc = host->mmc;
  195. return dwmci_probe(dev);
  196. }
  197. static int exynos_dwmmc_bind(struct udevice *dev)
  198. {
  199. struct exynos_mmc_plat *plat = dev_get_plat(dev);
  200. return dwmci_bind(dev, &plat->mmc, &plat->cfg);
  201. }
  202. static const struct udevice_id exynos_dwmmc_ids[] = {
  203. { .compatible = "samsung,exynos4412-dw-mshc" },
  204. { .compatible = "samsung,exynos-dwmmc" },
  205. { }
  206. };
  207. U_BOOT_DRIVER(exynos_dwmmc_drv) = {
  208. .name = "exynos_dwmmc",
  209. .id = UCLASS_MMC,
  210. .of_match = exynos_dwmmc_ids,
  211. .bind = exynos_dwmmc_bind,
  212. .ops = &dm_dwmci_ops,
  213. .probe = exynos_dwmmc_probe,
  214. .priv_auto = sizeof(struct dwmci_exynos_priv_data),
  215. .plat_auto = sizeof(struct exynos_mmc_plat),
  216. };
  217. #endif