ca_dw_mmc.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2019 Cortina Access
  4. * Arthur Li <arthur.li@cortina-access.com>
  5. */
  6. #include <common.h>
  7. #include <dwmmc.h>
  8. #include <fdtdec.h>
  9. #include <asm/global_data.h>
  10. #include <linux/libfdt.h>
  11. #include <malloc.h>
  12. #include <errno.h>
  13. #include <dm.h>
  14. #include <mapmem.h>
  15. #define SD_CLK_SEL_MASK (0x3)
  16. #define SD_DLL_DEFAULT (0x143000)
  17. #define SD_SCLK_MAX (200000000)
  18. #define SD_CLK_SEL_200MHZ (0x2)
  19. #define SD_CLK_SEL_100MHZ (0x1)
  20. #define SD_CLK_SEL_50MHZ (0x0)
  21. #define IO_DRV_SD_DS_OFFSET (16)
  22. #define IO_DRV_SD_DS_MASK (0xff << IO_DRV_SD_DS_OFFSET)
  23. #define MIN_FREQ (400000)
  24. DECLARE_GLOBAL_DATA_PTR;
  25. struct ca_mmc_plat {
  26. struct mmc_config cfg;
  27. struct mmc mmc;
  28. };
  29. struct ca_dwmmc_priv_data {
  30. struct dwmci_host host;
  31. void __iomem *sd_dll_reg;
  32. void __iomem *io_drv_reg;
  33. u8 ds;
  34. };
  35. static int ca_dwmci_clksel(struct dwmci_host *host)
  36. {
  37. struct ca_dwmmc_priv_data *priv = host->priv;
  38. u32 val = readl(priv->sd_dll_reg);
  39. val &= ~SD_CLK_SEL_MASK;
  40. if (host->bus_hz >= 200000000)
  41. val |= SD_CLK_SEL_200MHZ;
  42. else if (host->bus_hz >= 100000000)
  43. val |= SD_CLK_SEL_100MHZ;
  44. writel(val, priv->sd_dll_reg);
  45. return 0;
  46. }
  47. static void ca_dwmci_board_init(struct dwmci_host *host)
  48. {
  49. struct ca_dwmmc_priv_data *priv = host->priv;
  50. u32 val = readl(priv->io_drv_reg);
  51. writel(SD_DLL_DEFAULT, priv->sd_dll_reg);
  52. val &= ~IO_DRV_SD_DS_MASK;
  53. if (priv && priv->ds)
  54. val |= priv->ds << IO_DRV_SD_DS_OFFSET;
  55. writel(val, priv->io_drv_reg);
  56. }
  57. unsigned int ca_dwmci_get_mmc_clock(struct dwmci_host *host, uint freq)
  58. {
  59. struct ca_dwmmc_priv_data *priv = host->priv;
  60. u8 sd_clk_sel = readl(priv->sd_dll_reg) & SD_CLK_SEL_MASK;
  61. u8 clk_div;
  62. switch (sd_clk_sel) {
  63. case SD_CLK_SEL_50MHZ:
  64. clk_div = 4;
  65. break;
  66. case SD_CLK_SEL_100MHZ:
  67. clk_div = 2;
  68. break;
  69. default:
  70. clk_div = 1;
  71. }
  72. return SD_SCLK_MAX / clk_div / (host->div + 1);
  73. }
  74. static int ca_dwmmc_of_to_plat(struct udevice *dev)
  75. {
  76. struct ca_dwmmc_priv_data *priv = dev_get_priv(dev);
  77. struct dwmci_host *host = &priv->host;
  78. u32 tmp;
  79. host->name = dev->name;
  80. host->dev_index = 0;
  81. host->buswidth = dev_read_u32_default(dev, "bus-width", 1);
  82. host->bus_hz = dev_read_u32_default(dev, "max-frequency", 50000000);
  83. priv->ds = dev_read_u32_default(dev, "io_ds", 0x33);
  84. host->fifo_mode = dev_read_bool(dev, "fifo-mode");
  85. dev_read_u32(dev, "sd_dll_ctrl", &tmp);
  86. priv->sd_dll_reg = map_sysmem((uintptr_t)tmp, sizeof(uintptr_t));
  87. if (!priv->sd_dll_reg)
  88. return -EINVAL;
  89. dev_read_u32(dev, "io_drv_ctrl", &tmp);
  90. priv->io_drv_reg = map_sysmem((uintptr_t)tmp, sizeof(uintptr_t));
  91. if (!priv->io_drv_reg)
  92. return -EINVAL;
  93. host->ioaddr = dev_read_addr_ptr(dev);
  94. if (!host->ioaddr)
  95. return -EINVAL;
  96. host->priv = priv;
  97. return 0;
  98. }
  99. struct dm_mmc_ops ca_dwmci_dm_ops;
  100. static int ca_dwmmc_probe(struct udevice *dev)
  101. {
  102. struct ca_mmc_plat *plat = dev_get_plat(dev);
  103. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  104. struct ca_dwmmc_priv_data *priv = dev_get_priv(dev);
  105. struct dwmci_host *host = &priv->host;
  106. memcpy(&ca_dwmci_dm_ops, &dm_dwmci_ops, sizeof(struct dm_mmc_ops));
  107. dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, MIN_FREQ);
  108. if (host->buswidth == 1)
  109. (&plat->cfg)->host_caps &= ~(MMC_MODE_8BIT | MMC_MODE_4BIT);
  110. host->mmc = &plat->mmc;
  111. host->mmc->priv = &priv->host;
  112. upriv->mmc = host->mmc;
  113. host->mmc->dev = dev;
  114. host->clksel = ca_dwmci_clksel;
  115. host->board_init = ca_dwmci_board_init;
  116. host->get_mmc_clk = ca_dwmci_get_mmc_clock;
  117. return dwmci_probe(dev);
  118. }
  119. static int ca_dwmmc_bind(struct udevice *dev)
  120. {
  121. struct ca_mmc_plat *plat = dev_get_plat(dev);
  122. return dwmci_bind(dev, &plat->mmc, &plat->cfg);
  123. }
  124. static const struct udevice_id ca_dwmmc_ids[] = {
  125. { .compatible = "cortina,ca-mmc" },
  126. { }
  127. };
  128. U_BOOT_DRIVER(ca_dwmmc_drv) = {
  129. .name = "cortina_dwmmc",
  130. .id = UCLASS_MMC,
  131. .of_match = ca_dwmmc_ids,
  132. .of_to_plat = ca_dwmmc_of_to_plat,
  133. .bind = ca_dwmmc_bind,
  134. .ops = &ca_dwmci_dm_ops,
  135. .probe = ca_dwmmc_probe,
  136. .priv_auto = sizeof(struct ca_dwmmc_priv_data),
  137. .plat_auto = sizeof(struct ca_mmc_plat),
  138. };