atmel_sdhci.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Atmel Corporation
  4. * Wenyou.Yang <wenyou.yang@atmel.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <dm.h>
  9. #include <malloc.h>
  10. #include <sdhci.h>
  11. #include <asm/arch/clk.h>
  12. #include <asm/global_data.h>
  13. #define ATMEL_SDHC_MIN_FREQ 400000
  14. #define ATMEL_SDHC_GCK_RATE 240000000
  15. #ifndef CONFIG_DM_MMC
  16. int atmel_sdhci_init(void *regbase, u32 id)
  17. {
  18. struct sdhci_host *host;
  19. u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ;
  20. host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host));
  21. if (!host) {
  22. printf("%s: sdhci_host calloc failed\n", __func__);
  23. return -ENOMEM;
  24. }
  25. host->name = "atmel_sdhci";
  26. host->ioaddr = regbase;
  27. host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
  28. max_clk = at91_get_periph_generated_clk(id);
  29. if (!max_clk) {
  30. printf("%s: Failed to get the proper clock\n", __func__);
  31. free(host);
  32. return -ENODEV;
  33. }
  34. host->max_clk = max_clk;
  35. add_sdhci(host, 0, min_clk);
  36. return 0;
  37. }
  38. #else
  39. DECLARE_GLOBAL_DATA_PTR;
  40. struct atmel_sdhci_plat {
  41. struct mmc_config cfg;
  42. struct mmc mmc;
  43. };
  44. static int atmel_sdhci_probe(struct udevice *dev)
  45. {
  46. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  47. struct atmel_sdhci_plat *plat = dev_get_plat(dev);
  48. struct sdhci_host *host = dev_get_priv(dev);
  49. u32 max_clk;
  50. struct clk clk;
  51. int ret;
  52. ret = clk_get_by_index(dev, 0, &clk);
  53. if (ret)
  54. return ret;
  55. ret = clk_enable(&clk);
  56. if (ret)
  57. return ret;
  58. host->name = dev->name;
  59. host->ioaddr = dev_read_addr_ptr(dev);
  60. host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
  61. host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  62. "bus-width", 4);
  63. ret = clk_get_by_index(dev, 1, &clk);
  64. if (ret)
  65. return ret;
  66. clk_set_rate(&clk, ATMEL_SDHC_GCK_RATE);
  67. max_clk = clk_get_rate(&clk);
  68. if (!max_clk)
  69. return -EINVAL;
  70. ret = clk_enable(&clk);
  71. /* return error only if the clock really has a clock enable func */
  72. if (ret && ret != -ENOSYS)
  73. return ret;
  74. ret = mmc_of_parse(dev, &plat->cfg);
  75. if (ret)
  76. return ret;
  77. host->max_clk = max_clk;
  78. host->mmc = &plat->mmc;
  79. host->mmc->dev = dev;
  80. ret = sdhci_setup_cfg(&plat->cfg, host, 0, ATMEL_SDHC_MIN_FREQ);
  81. if (ret)
  82. return ret;
  83. host->mmc->priv = host;
  84. upriv->mmc = host->mmc;
  85. clk_free(&clk);
  86. return sdhci_probe(dev);
  87. }
  88. static int atmel_sdhci_bind(struct udevice *dev)
  89. {
  90. struct atmel_sdhci_plat *plat = dev_get_plat(dev);
  91. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  92. }
  93. static const struct udevice_id atmel_sdhci_ids[] = {
  94. { .compatible = "atmel,sama5d2-sdhci" },
  95. { .compatible = "microchip,sam9x60-sdhci" },
  96. { .compatible = "microchip,sama7g5-sdhci" },
  97. { }
  98. };
  99. U_BOOT_DRIVER(atmel_sdhci_drv) = {
  100. .name = "atmel_sdhci",
  101. .id = UCLASS_MMC,
  102. .of_match = atmel_sdhci_ids,
  103. .ops = &sdhci_ops,
  104. .bind = atmel_sdhci_bind,
  105. .probe = atmel_sdhci_probe,
  106. .priv_auto = sizeof(struct sdhci_host),
  107. .plat_auto = sizeof(struct atmel_sdhci_plat),
  108. };
  109. #endif