arm_pl180_mmci.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ARM PrimeCell MultiMedia Card Interface - PL180
  4. *
  5. * Copyright (C) ST-Ericsson SA 2010
  6. *
  7. * Author: Ulf Hansson <ulf.hansson@stericsson.com>
  8. * Author: Martin Lundholm <martin.xa.lundholm@stericsson.com>
  9. * Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org>
  10. */
  11. /* #define DEBUG */
  12. #include "common.h"
  13. #include <clk.h>
  14. #include <errno.h>
  15. #include <log.h>
  16. #include <malloc.h>
  17. #include <mmc.h>
  18. #include <dm/device_compat.h>
  19. #include <asm/io.h>
  20. #include <asm-generic/gpio.h>
  21. #include "arm_pl180_mmci.h"
  22. #include <linux/delay.h>
  23. #ifdef CONFIG_DM_MMC
  24. #include <dm.h>
  25. #define MMC_CLOCK_MAX 48000000
  26. #define MMC_CLOCK_MIN 400000
  27. struct arm_pl180_mmc_plat {
  28. struct mmc_config cfg;
  29. struct mmc mmc;
  30. };
  31. #endif
  32. static int wait_for_command_end(struct mmc *dev, struct mmc_cmd *cmd)
  33. {
  34. u32 hoststatus, statusmask;
  35. struct pl180_mmc_host *host = dev->priv;
  36. statusmask = SDI_STA_CTIMEOUT | SDI_STA_CCRCFAIL;
  37. if ((cmd->resp_type & MMC_RSP_PRESENT))
  38. statusmask |= SDI_STA_CMDREND;
  39. else
  40. statusmask |= SDI_STA_CMDSENT;
  41. do
  42. hoststatus = readl(&host->base->status) & statusmask;
  43. while (!hoststatus);
  44. writel(statusmask, &host->base->status_clear);
  45. if (hoststatus & SDI_STA_CTIMEOUT) {
  46. debug("CMD%d time out\n", cmd->cmdidx);
  47. return -ETIMEDOUT;
  48. } else if ((hoststatus & SDI_STA_CCRCFAIL) &&
  49. (cmd->resp_type & MMC_RSP_CRC)) {
  50. printf("CMD%d CRC error\n", cmd->cmdidx);
  51. return -EILSEQ;
  52. }
  53. if (cmd->resp_type & MMC_RSP_PRESENT) {
  54. cmd->response[0] = readl(&host->base->response0);
  55. cmd->response[1] = readl(&host->base->response1);
  56. cmd->response[2] = readl(&host->base->response2);
  57. cmd->response[3] = readl(&host->base->response3);
  58. debug("CMD%d response[0]:0x%08X, response[1]:0x%08X, "
  59. "response[2]:0x%08X, response[3]:0x%08X\n",
  60. cmd->cmdidx, cmd->response[0], cmd->response[1],
  61. cmd->response[2], cmd->response[3]);
  62. }
  63. return 0;
  64. }
  65. /* send command to the mmc card and wait for results */
  66. static int do_command(struct mmc *dev, struct mmc_cmd *cmd)
  67. {
  68. int result;
  69. u32 sdi_cmd = 0;
  70. struct pl180_mmc_host *host = dev->priv;
  71. sdi_cmd = ((cmd->cmdidx & SDI_CMD_CMDINDEX_MASK) | SDI_CMD_CPSMEN);
  72. if (cmd->resp_type) {
  73. sdi_cmd |= SDI_CMD_WAITRESP;
  74. if (cmd->resp_type & MMC_RSP_136)
  75. sdi_cmd |= SDI_CMD_LONGRESP;
  76. }
  77. writel((u32)cmd->cmdarg, &host->base->argument);
  78. udelay(COMMAND_REG_DELAY);
  79. writel(sdi_cmd, &host->base->command);
  80. result = wait_for_command_end(dev, cmd);
  81. /* After CMD2 set RCA to a none zero value. */
  82. if ((result == 0) && (cmd->cmdidx == MMC_CMD_ALL_SEND_CID))
  83. dev->rca = 10;
  84. /* After CMD3 open drain is switched off and push pull is used. */
  85. if ((result == 0) && (cmd->cmdidx == MMC_CMD_SET_RELATIVE_ADDR)) {
  86. u32 sdi_pwr = readl(&host->base->power) & ~SDI_PWR_OPD;
  87. writel(sdi_pwr, &host->base->power);
  88. }
  89. return result;
  90. }
  91. static int read_bytes(struct mmc *dev, u32 *dest, u32 blkcount, u32 blksize)
  92. {
  93. u32 *tempbuff = dest;
  94. u64 xfercount = blkcount * blksize;
  95. struct pl180_mmc_host *host = dev->priv;
  96. u32 status, status_err;
  97. debug("read_bytes: blkcount=%u blksize=%u\n", blkcount, blksize);
  98. status = readl(&host->base->status);
  99. status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT |
  100. SDI_STA_RXOVERR);
  101. while ((!status_err) && (xfercount >= sizeof(u32))) {
  102. if (status & SDI_STA_RXDAVL) {
  103. *(tempbuff) = readl(&host->base->fifo);
  104. tempbuff++;
  105. xfercount -= sizeof(u32);
  106. }
  107. status = readl(&host->base->status);
  108. status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT |
  109. SDI_STA_RXOVERR);
  110. }
  111. status_err = status &
  112. (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND |
  113. SDI_STA_RXOVERR);
  114. while (!status_err) {
  115. status = readl(&host->base->status);
  116. status_err = status &
  117. (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND |
  118. SDI_STA_RXOVERR);
  119. }
  120. if (status & SDI_STA_DTIMEOUT) {
  121. printf("Read data timed out, xfercount: %llu, status: 0x%08X\n",
  122. xfercount, status);
  123. return -ETIMEDOUT;
  124. } else if (status & SDI_STA_DCRCFAIL) {
  125. printf("Read data bytes CRC error: 0x%x\n", status);
  126. return -EILSEQ;
  127. } else if (status & SDI_STA_RXOVERR) {
  128. printf("Read data RX overflow error\n");
  129. return -EIO;
  130. }
  131. writel(SDI_ICR_MASK, &host->base->status_clear);
  132. if (xfercount) {
  133. printf("Read data error, xfercount: %llu\n", xfercount);
  134. return -ENOBUFS;
  135. }
  136. return 0;
  137. }
  138. static int write_bytes(struct mmc *dev, u32 *src, u32 blkcount, u32 blksize)
  139. {
  140. u32 *tempbuff = src;
  141. int i;
  142. u64 xfercount = blkcount * blksize;
  143. struct pl180_mmc_host *host = dev->priv;
  144. u32 status, status_err;
  145. debug("write_bytes: blkcount=%u blksize=%u\n", blkcount, blksize);
  146. status = readl(&host->base->status);
  147. status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT);
  148. while (!status_err && xfercount) {
  149. if (status & SDI_STA_TXFIFOBW) {
  150. if (xfercount >= SDI_FIFO_BURST_SIZE * sizeof(u32)) {
  151. for (i = 0; i < SDI_FIFO_BURST_SIZE; i++)
  152. writel(*(tempbuff + i),
  153. &host->base->fifo);
  154. tempbuff += SDI_FIFO_BURST_SIZE;
  155. xfercount -= SDI_FIFO_BURST_SIZE * sizeof(u32);
  156. } else {
  157. while (xfercount >= sizeof(u32)) {
  158. writel(*(tempbuff), &host->base->fifo);
  159. tempbuff++;
  160. xfercount -= sizeof(u32);
  161. }
  162. }
  163. }
  164. status = readl(&host->base->status);
  165. status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT);
  166. }
  167. status_err = status &
  168. (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND);
  169. while (!status_err) {
  170. status = readl(&host->base->status);
  171. status_err = status &
  172. (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND);
  173. }
  174. if (status & SDI_STA_DTIMEOUT) {
  175. printf("Write data timed out, xfercount:%llu,status:0x%08X\n",
  176. xfercount, status);
  177. return -ETIMEDOUT;
  178. } else if (status & SDI_STA_DCRCFAIL) {
  179. printf("Write data CRC error\n");
  180. return -EILSEQ;
  181. }
  182. writel(SDI_ICR_MASK, &host->base->status_clear);
  183. if (xfercount) {
  184. printf("Write data error, xfercount:%llu", xfercount);
  185. return -ENOBUFS;
  186. }
  187. return 0;
  188. }
  189. static int do_data_transfer(struct mmc *dev,
  190. struct mmc_cmd *cmd,
  191. struct mmc_data *data)
  192. {
  193. int error = -ETIMEDOUT;
  194. struct pl180_mmc_host *host = dev->priv;
  195. u32 blksz = 0;
  196. u32 data_ctrl = 0;
  197. u32 data_len = (u32) (data->blocks * data->blocksize);
  198. if (!host->version2) {
  199. blksz = (ffs(data->blocksize) - 1);
  200. data_ctrl |= ((blksz << 4) & SDI_DCTRL_DBLKSIZE_MASK);
  201. } else {
  202. blksz = data->blocksize;
  203. data_ctrl |= (blksz << SDI_DCTRL_DBLOCKSIZE_V2_SHIFT);
  204. }
  205. data_ctrl |= SDI_DCTRL_DTEN | SDI_DCTRL_BUSYMODE;
  206. writel(SDI_DTIMER_DEFAULT, &host->base->datatimer);
  207. writel(data_len, &host->base->datalength);
  208. udelay(DATA_REG_DELAY);
  209. if (data->flags & MMC_DATA_READ) {
  210. data_ctrl |= SDI_DCTRL_DTDIR_IN;
  211. writel(data_ctrl, &host->base->datactrl);
  212. error = do_command(dev, cmd);
  213. if (error)
  214. return error;
  215. error = read_bytes(dev, (u32 *)data->dest, (u32)data->blocks,
  216. (u32)data->blocksize);
  217. } else if (data->flags & MMC_DATA_WRITE) {
  218. error = do_command(dev, cmd);
  219. if (error)
  220. return error;
  221. writel(data_ctrl, &host->base->datactrl);
  222. error = write_bytes(dev, (u32 *)data->src, (u32)data->blocks,
  223. (u32)data->blocksize);
  224. }
  225. return error;
  226. }
  227. static int host_request(struct mmc *dev,
  228. struct mmc_cmd *cmd,
  229. struct mmc_data *data)
  230. {
  231. int result;
  232. if (data)
  233. result = do_data_transfer(dev, cmd, data);
  234. else
  235. result = do_command(dev, cmd);
  236. return result;
  237. }
  238. static int host_set_ios(struct mmc *dev)
  239. {
  240. struct pl180_mmc_host *host = dev->priv;
  241. u32 sdi_clkcr;
  242. sdi_clkcr = readl(&host->base->clock);
  243. /* Ramp up the clock rate */
  244. if (dev->clock) {
  245. u32 clkdiv = 0;
  246. u32 tmp_clock;
  247. if (dev->clock >= dev->cfg->f_max) {
  248. clkdiv = 0;
  249. dev->clock = dev->cfg->f_max;
  250. } else {
  251. clkdiv = (host->clock_in / dev->clock) - 2;
  252. }
  253. tmp_clock = host->clock_in / (clkdiv + 2);
  254. while (tmp_clock > dev->clock) {
  255. clkdiv++;
  256. tmp_clock = host->clock_in / (clkdiv + 2);
  257. }
  258. if (clkdiv > SDI_CLKCR_CLKDIV_MASK)
  259. clkdiv = SDI_CLKCR_CLKDIV_MASK;
  260. tmp_clock = host->clock_in / (clkdiv + 2);
  261. dev->clock = tmp_clock;
  262. sdi_clkcr &= ~(SDI_CLKCR_CLKDIV_MASK);
  263. sdi_clkcr |= clkdiv;
  264. }
  265. /* Set the bus width */
  266. if (dev->bus_width) {
  267. u32 buswidth = 0;
  268. switch (dev->bus_width) {
  269. case 1:
  270. buswidth |= SDI_CLKCR_WIDBUS_1;
  271. break;
  272. case 4:
  273. buswidth |= SDI_CLKCR_WIDBUS_4;
  274. break;
  275. case 8:
  276. buswidth |= SDI_CLKCR_WIDBUS_8;
  277. break;
  278. default:
  279. printf("Invalid bus width: %d\n", dev->bus_width);
  280. break;
  281. }
  282. sdi_clkcr &= ~(SDI_CLKCR_WIDBUS_MASK);
  283. sdi_clkcr |= buswidth;
  284. }
  285. writel(sdi_clkcr, &host->base->clock);
  286. udelay(CLK_CHANGE_DELAY);
  287. return 0;
  288. }
  289. #ifndef CONFIG_DM_MMC
  290. /* MMC uses open drain drivers in the enumeration phase */
  291. static int mmc_host_reset(struct mmc *dev)
  292. {
  293. struct pl180_mmc_host *host = dev->priv;
  294. writel(host->pwr_init, &host->base->power);
  295. return 0;
  296. }
  297. static const struct mmc_ops arm_pl180_mmci_ops = {
  298. .send_cmd = host_request,
  299. .set_ios = host_set_ios,
  300. .init = mmc_host_reset,
  301. };
  302. /*
  303. * mmc_host_init - initialize the mmc controller.
  304. * Set initial clock and power for mmc slot.
  305. * Initialize mmc struct and register with mmc framework.
  306. */
  307. int arm_pl180_mmci_init(struct pl180_mmc_host *host, struct mmc **mmc)
  308. {
  309. u32 sdi_u32;
  310. writel(host->pwr_init, &host->base->power);
  311. writel(host->clkdiv_init, &host->base->clock);
  312. udelay(CLK_CHANGE_DELAY);
  313. /* Disable mmc interrupts */
  314. sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK;
  315. writel(sdi_u32, &host->base->mask0);
  316. host->cfg.name = host->name;
  317. host->cfg.ops = &arm_pl180_mmci_ops;
  318. /* TODO remove the duplicates */
  319. host->cfg.host_caps = host->caps;
  320. host->cfg.voltages = host->voltages;
  321. host->cfg.f_min = host->clock_min;
  322. host->cfg.f_max = host->clock_max;
  323. if (host->b_max != 0)
  324. host->cfg.b_max = host->b_max;
  325. else
  326. host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  327. *mmc = mmc_create(&host->cfg, host);
  328. if (!*mmc)
  329. return -1;
  330. debug("registered mmc interface number is:%d\n",
  331. (*mmc)->block_dev.devnum);
  332. return 0;
  333. }
  334. #endif
  335. #ifdef CONFIG_DM_MMC
  336. static void arm_pl180_mmc_init(struct pl180_mmc_host *host)
  337. {
  338. u32 sdi_u32;
  339. writel(host->pwr_init, &host->base->power);
  340. writel(host->clkdiv_init, &host->base->clock);
  341. udelay(CLK_CHANGE_DELAY);
  342. /* Disable mmc interrupts */
  343. sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK;
  344. writel(sdi_u32, &host->base->mask0);
  345. }
  346. static int arm_pl180_mmc_probe(struct udevice *dev)
  347. {
  348. struct arm_pl180_mmc_plat *pdata = dev_get_plat(dev);
  349. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  350. struct mmc *mmc = &pdata->mmc;
  351. struct pl180_mmc_host *host = dev_get_priv(dev);
  352. struct mmc_config *cfg = &pdata->cfg;
  353. struct clk clk;
  354. u32 periphid;
  355. int ret;
  356. ret = clk_get_by_index(dev, 0, &clk);
  357. if (ret < 0)
  358. return ret;
  359. ret = clk_enable(&clk);
  360. if (ret) {
  361. clk_free(&clk);
  362. dev_err(dev, "failed to enable clock\n");
  363. return ret;
  364. }
  365. host->pwr_init = INIT_PWR;
  366. host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN |
  367. SDI_CLKCR_HWFC_EN;
  368. host->clock_in = clk_get_rate(&clk);
  369. cfg->name = dev->name;
  370. cfg->voltages = VOLTAGE_WINDOW_SD;
  371. cfg->host_caps = 0;
  372. cfg->f_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
  373. cfg->f_max = MMC_CLOCK_MAX;
  374. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  375. periphid = dev_read_u32_default(dev, "arm,primecell-periphid", 0);
  376. switch (periphid) {
  377. case STM32_MMCI_ID: /* stm32 variant */
  378. host->version2 = false;
  379. break;
  380. case UX500V2_MMCI_ID:
  381. host->pwr_init = SDI_PWR_OPD | SDI_PWR_PWRCTRL_ON;
  382. host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 | SDI_CLKCR_CLKEN |
  383. SDI_CLKCR_HWFC_EN;
  384. cfg->voltages = VOLTAGE_WINDOW_MMC;
  385. cfg->f_min = host->clock_in / (2 + SDI_CLKCR_CLKDIV_INIT_V2);
  386. host->version2 = true;
  387. break;
  388. default:
  389. host->version2 = true;
  390. }
  391. gpio_request_by_name(dev, "cd-gpios", 0, &host->cd_gpio, GPIOD_IS_IN);
  392. ret = mmc_of_parse(dev, cfg);
  393. if (ret)
  394. return ret;
  395. arm_pl180_mmc_init(host);
  396. mmc->priv = host;
  397. mmc->dev = dev;
  398. upriv->mmc = mmc;
  399. return 0;
  400. }
  401. int arm_pl180_mmc_bind(struct udevice *dev)
  402. {
  403. struct arm_pl180_mmc_plat *plat = dev_get_plat(dev);
  404. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  405. }
  406. static int dm_host_request(struct udevice *dev, struct mmc_cmd *cmd,
  407. struct mmc_data *data)
  408. {
  409. struct mmc *mmc = mmc_get_mmc_dev(dev);
  410. return host_request(mmc, cmd, data);
  411. }
  412. static int dm_host_set_ios(struct udevice *dev)
  413. {
  414. struct mmc *mmc = mmc_get_mmc_dev(dev);
  415. return host_set_ios(mmc);
  416. }
  417. static int dm_mmc_getcd(struct udevice *dev)
  418. {
  419. struct pl180_mmc_host *host = dev_get_priv(dev);
  420. int value = 1;
  421. if (dm_gpio_is_valid(&host->cd_gpio))
  422. value = dm_gpio_get_value(&host->cd_gpio);
  423. return value;
  424. }
  425. static const struct dm_mmc_ops arm_pl180_dm_mmc_ops = {
  426. .send_cmd = dm_host_request,
  427. .set_ios = dm_host_set_ios,
  428. .get_cd = dm_mmc_getcd,
  429. };
  430. static int arm_pl180_mmc_of_to_plat(struct udevice *dev)
  431. {
  432. struct pl180_mmc_host *host = dev_get_priv(dev);
  433. host->base = dev_read_addr_ptr(dev);
  434. if (!host->base)
  435. return -EINVAL;
  436. return 0;
  437. }
  438. static const struct udevice_id arm_pl180_mmc_match[] = {
  439. { .compatible = "arm,pl180" },
  440. { .compatible = "arm,pl18x" },
  441. { /* sentinel */ }
  442. };
  443. U_BOOT_DRIVER(arm_pl180_mmc) = {
  444. .name = "arm_pl180_mmc",
  445. .id = UCLASS_MMC,
  446. .of_match = arm_pl180_mmc_match,
  447. .ops = &arm_pl180_dm_mmc_ops,
  448. .probe = arm_pl180_mmc_probe,
  449. .of_to_plat = arm_pl180_mmc_of_to_plat,
  450. .bind = arm_pl180_mmc_bind,
  451. .priv_auto = sizeof(struct pl180_mmc_host),
  452. .plat_auto = sizeof(struct arm_pl180_mmc_plat),
  453. };
  454. #endif