mpc83xx_serdes.h 8.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2018
  4. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  5. */
  6. /**
  7. * enum srdscr0_mask - Bit masks for SRDSCR0 (SerDes Control Register 0)
  8. * @SRDSCR0_DPPA: Bitmask for the DPPA (diff pk-pk swing for lane A)
  9. * field of the SRCSCR0
  10. * @SRDSCR0_DPPE: Bitmask for the DPPE (diff pk-pk swing for lane E)
  11. * field of the SRCSCR0
  12. * @SRDSCR0_DPP_1V2: Combined bitmask to set diff pk-pk swing for both lanes
  13. * @SRDSCR0_TXEQA_MASK: Bitmask for the TXEQA (transmit equalization for
  14. * lane A) field of the SRCSCR0
  15. * @SRDSCR0_TXEQA_SATA: Bitmask to set the TXEQA to the value used for SATA
  16. * @SRDSCR0_TXEQE_MASK: Bitmask for the TXEQE (transmit equalization for
  17. * lane E) field of the SRCSCR0
  18. * @SRDSCR0_TXEQE_SATA: Bitmask to set the TXEQE to the value used for SATA
  19. */
  20. #include <linux/bitops.h>
  21. enum srdscr0_mask {
  22. SRDSCR0_DPPA = BIT(31 - 16),
  23. SRDSCR0_DPPE = BIT(31 - 20),
  24. SRDSCR0_DPP_1V2 = SRDSCR0_DPPE | SRDSCR0_DPPA,
  25. SRDSCR0_TXEQA_MASK = 0x00007000,
  26. SRDSCR0_TXEQA_SATA = 0x00001000,
  27. SRDSCR0_TXEQE_MASK = 0x00000700,
  28. SRDSCR0_TXEQE_SATA = 0x00000100,
  29. };
  30. /**
  31. * enum srdscr1_mask - Bit masks for SRDSCR1 (SerDes Control Register 1)
  32. * @SRDSCR1_PLLBW: Bitmask for the PLLBW (PLL bandwidth) field of SRDSCR1
  33. */
  34. enum srdscr1_mask {
  35. SRDSCR1_PLLBW = BIT(31 - 25),
  36. };
  37. /**
  38. * enum srdscr2_mask - Bit masks for SRDSCR2 (SerDes Control Register 2)
  39. * @SRDSCR2_VDD_1V2: Bit mask to to set the VDD field of the SCRSCR2
  40. * @SRDSCR2_SEICA_MASK: Bitmask for the SEICA (Receiver electrical idle
  41. * detection control for lane A) field of the SRCSCR2
  42. * @SRDSCR2_SEICE_MASK: Bitmask for the SEICE (Receiver electrical idle
  43. * detection control for lane E) field of the SRCSCR2
  44. * @SRDSCR2_SEIC_MASK: Combined bitmask to set the receiver electrical idle
  45. * detection control for both lanes
  46. * @SRDSCR2_SEICA_SATA: Bitmask to set the SEICA field to the value used for
  47. * SATA
  48. * @SRDSCR2_SEICE_SATA: Bitmask to set the SEICE field to the value used for
  49. * SATA
  50. * @SRDSCR2_SEIC_SATA: Combined bitmask to set the value of both SEIC fields
  51. * to the value used for SATA
  52. * @SRDSCR2_SEICA_PEX: Bitmask to set the SEICA field to the value used for
  53. * PCI Express
  54. * @SRDSCR2_SEICE_PEX: Bitmask to set the SEICE field to the value used for
  55. * PCI Express
  56. * @SRDSCR2_SEIC_PEX: Combined bitmask to set the value of both SEIC fields
  57. * to the value used for PCI Express
  58. * @SRDSCR2_SEICA_SGMII: Bitmask to set the SEICA field to the value used for
  59. * SGMII
  60. * @SRDSCR2_SEICE_SGMII: Bitmask to set the SEICE field to the value used for
  61. * SGMII
  62. * @SRDSCR2_SEIC_SGMII: Combined bitmask to set the value of both SEIC fields
  63. * to the value used for SGMII
  64. */
  65. enum srdscr2_mask {
  66. SRDSCR2_VDD_1V2 = 0x00800000,
  67. SRDSCR2_SEICA_MASK = 0x00001c00,
  68. SRDSCR2_SEICE_MASK = 0x0000001c,
  69. SRDSCR2_SEIC_MASK = SRDSCR2_SEICA_MASK | SRDSCR2_SEICE_MASK,
  70. SRDSCR2_SEICA_SATA = 0x00001400,
  71. SRDSCR2_SEICE_SATA = 0x00000014,
  72. SRDSCR2_SEIC_SATA = SRDSCR2_SEICA_SATA | SRDSCR2_SEICE_SATA,
  73. SRDSCR2_SEICA_PEX = 0x00001000,
  74. SRDSCR2_SEICE_PEX = 0x00000010,
  75. SRDSCR2_SEIC_PEX = SRDSCR2_SEICA_PEX | SRDSCR2_SEICE_PEX,
  76. SRDSCR2_SEICA_SGMII = 0x00000100,
  77. SRDSCR2_SEICE_SGMII = 0x00000001,
  78. SRDSCR2_SEIC_SGMII = SRDSCR2_SEICA_SGMII | SRDSCR2_SEICE_SGMII,
  79. };
  80. /**
  81. * enum srdscr3_mask - Bit masks for SRDSCR3 (SerDes Control Register 3)
  82. * @SRDSCR3_KFRA_SATA: Bitmask to set the KFRA field of SRDSCR3 to the
  83. * value used by SATA
  84. * @SRDSCR3_KFRE_SATA: Bitmask to set the KFRE field of SRDSCR3 to the
  85. * value used by SATA
  86. * @SRDSCR3_KFR_SATA: Combined bitmask to set both KFR fields to the
  87. * value used by SATA
  88. * @SRDSCR3_KPHA_SATA: Bitmask to set the KPHA field of SRDSCR3 to the
  89. * value used by SATA
  90. * @SRDSCR3_KPHE_SATA: Bitmask to set the KPHE field of SRDSCR3 to the
  91. * value used by SATA
  92. * @SRDSCR3_KPH_SATA: Combined bitmask to set both KPH fields to the
  93. * value used by SATA
  94. * @SRDSCR3_SDFMA_SATA_PEX: Bitmask to set the SDFMA field of SRDSCR3 to the
  95. * value used by SATA and PCI Express
  96. * @SRDSCR3_SDFME_SATA_PEX: Bitmask to set the SDFME field of SRDSCR3 to the
  97. * value used by SATA and PCI Express
  98. * @SRDSCR3_SDFM_SATA_PEX: Combined bitmask to set both SDFM fields to the
  99. * value used by SATA and PCI Express
  100. * @SRDSCR3_SDTXLA_SATA: Bitmask to set the SDTXLA field of SRDSCR3 to the
  101. * value used by SATA
  102. * @SRDSCR3_SDTXLE_SATA: Bitmask to set the SDTXLE field of SRDSCR3 to the
  103. * value used by SATA
  104. * @SRDSCR3_SDTXL_SATA: Combined bitmask to set both SDTXL fields to the
  105. * value used by SATA
  106. *
  107. * KFRA = 'Kfr' gain selection in the CDR for lane A
  108. * KFRE = 'Kfr' gain selection in the CDR for lane E
  109. * SDFMA = Bandwidth of digital filter for lane A
  110. * SDFME = Bandwidth of digital filter for lane E
  111. * SDTXLA = Lane A transmitter amplitude levels
  112. * SDTXLE = Lane E transmitter amplitude levels
  113. */
  114. enum srdscr3_mask {
  115. SRDSCR3_KFRA_SATA = 0x10000000,
  116. SRDSCR3_KFRE_SATA = 0x00100000,
  117. SRDSCR3_KFR_SATA = SRDSCR3_KFRA_SATA | SRDSCR3_KFRE_SATA,
  118. SRDSCR3_KPHA_SATA = 0x04000000,
  119. SRDSCR3_KPHE_SATA = 0x00040000,
  120. SRDSCR3_KPH_SATA = SRDSCR3_KPHA_SATA | SRDSCR3_KPHE_SATA,
  121. SRDSCR3_SDFMA_SATA_PEX = 0x01000000,
  122. SRDSCR3_SDFME_SATA_PEX = 0x00010000,
  123. SRDSCR3_SDFM_SATA_PEX = SRDSCR3_SDFMA_SATA_PEX | SRDSCR3_SDFME_SATA_PEX,
  124. SRDSCR3_SDTXLA_SATA = 0x00000500,
  125. SRDSCR3_SDTXLE_SATA = 0x00000005,
  126. SRDSCR3_SDTXL_SATA = SRDSCR3_SDTXLA_SATA | SRDSCR3_SDTXLE_SATA,
  127. };
  128. /**
  129. * enum srdscr4_mask - Bit masks for SRDSCR4 (SerDes Control Register 4)
  130. * @SRDSCR4_PROTA_SATA: Bitmask to set the PROTA field of SRDSCR4 to the
  131. * value used by SATA
  132. * @SRDSCR4_PROTE_SATA: Bitmask to set the PROTE field of SRDSCR4 to the
  133. * value used by SATA
  134. * @SRDSCR4_PROT_SATA: Combined bitmask to set both PROT fields to the
  135. * value used by SATA
  136. * @SRDSCR4_PROTA_PEX: Bitmask to set the PROTA field of SRDSCR4 to the
  137. * value used by PCI Express
  138. * @SRDSCR4_PROTE_PEX: Bitmask to set the PROTE field of SRDSCR4 to the
  139. * value used by PCI Express
  140. * @SRDSCR4_PROT_PEX: Combined bitmask to set both PROT fields to the
  141. * value used by PCI Express
  142. * @SRDSCR4_PROTA_SGMII: Bitmask to set the PROTA field of SRDSCR4 to the
  143. * value used by SGMII
  144. * @SRDSCR4_PROTE_SGMII: Bitmask to set the PROTE field of SRDSCR4 to the
  145. * value used by SGMII
  146. * @SRDSCR4_PROT_SGMII: Combined bitmask to set both PROT fields to the
  147. * value used by SGMII
  148. * @SRDSCR4_PLANE_X2: Bitmask to set the PLANE field of SRDSCR4
  149. * @SRDSCR4_RFCKS_100: Bitmask to set the RFCKS field of SRDSCR4 to the
  150. * value 100Mhz
  151. * @SRDSCR4_RFCKS_125: Bitmask to set the RFCKS field of SRDSCR4 to the
  152. * value 125Mhz
  153. * @SRDSCR4_RFCKS_150: Bitmask to set the RFCKS field of SRDSCR4 to the
  154. * value 150Mhz
  155. *
  156. * PROTA = Lane A protocol select
  157. * PROTE = Lane E protocol select
  158. * PLAME = Number of PCI Express lanes
  159. */
  160. enum srdscr4_mask {
  161. SRDSCR4_PROTA_SATA = 0x00000800,
  162. SRDSCR4_PROTE_SATA = 0x00000008,
  163. SRDSCR4_PROT_SATA = SRDSCR4_PROTA_SATA | SRDSCR4_PROTE_SATA,
  164. SRDSCR4_PROTA_PEX = 0x00000100,
  165. SRDSCR4_PROTE_PEX = 0x00000001,
  166. SRDSCR4_PROT_PEX = SRDSCR4_PROTA_PEX | SRDSCR4_PROTE_PEX,
  167. SRDSCR4_PROTA_SGMII = 0x00000500,
  168. SRDSCR4_PROTE_SGMII = 0x00000005,
  169. SRDSCR4_PROT_SGMII = SRDSCR4_PROTA_SGMII | SRDSCR4_PROTE_SGMII,
  170. SRDSCR4_PLANE_X2 = 0x01000000,
  171. SRDSCR4_RFCKS_100 = (0 << 28),
  172. SRDSCR4_RFCKS_125 = (1 << 28),
  173. SRDSCR4_RFCKS_150 = (3 << 28),
  174. };
  175. /**
  176. * enum srdsrstctl_mask - Bit masks for SRDSRSTCTL (SerDes Reset Control Register)
  177. * @SRDSRSTCTL_RST: Bitmask for the RST (Software reset) field of the
  178. * SRDSRSTCTL
  179. * @SRDSRSTCTL_SATA_RESET: Bitmask for the SATA_RESET (SATA reset) field of the
  180. * SRDSRSTCTL
  181. */
  182. enum srdsrstctl_mask {
  183. SRDSRSTCTL_RST = 0x80000000,
  184. SRDSRSTCTL_SATA_RESET = 0xf,
  185. };
  186. /**
  187. * struct mpc83xx_serdes_regs - Register map of the SerDes controller
  188. * @srdscr0: SerDes Control Register 0
  189. * @srdscr1: SerDes Control Register 1
  190. * @srdscr2: SerDes Control Register 2
  191. * @srdscr3: SerDes Control Register 3
  192. * @srdscr4: SerDes Control Register 4
  193. * @fill0: Reserved space in the register map
  194. * @srdsrstctl: SerDes Reset Control Register
  195. */
  196. struct mpc83xx_serdes_regs {
  197. u32 srdscr0;
  198. u32 srdscr1;
  199. u32 srdscr2;
  200. u32 srdscr3;
  201. u32 srdscr4;
  202. u8 fill0[12];
  203. u32 srdsrstctl;
  204. };
  205. /**
  206. * enum pex_type - Types of PCI Express
  207. * @PEX_X1: PCI Express in x1 mode
  208. * @PEX_X2: PCI Express in x2 mode
  209. */
  210. enum pex_type {
  211. PEX_X1,
  212. PEX_X2,
  213. };