mpc83xx_serdes.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018
  4. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  5. *
  6. * base on the MPC83xx serdes initialization, which is
  7. *
  8. * Copyright 2007,2011 Freescale Semiconductor, Inc.
  9. * Copyright (C) 2008 MontaVista Software, Inc.
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <log.h>
  14. #include <mapmem.h>
  15. #include <misc.h>
  16. #include <linux/delay.h>
  17. #include "mpc83xx_serdes.h"
  18. /**
  19. * struct mpc83xx_serdes_priv - Private structure for MPC83xx serdes
  20. * @regs: The device's register map
  21. * @rfcks: Variable to keep the serdes reference clock selection set during
  22. * initialization in (is or'd to every value written to SRDSCR4)
  23. */
  24. struct mpc83xx_serdes_priv {
  25. struct mpc83xx_serdes_regs *regs;
  26. u32 rfcks;
  27. };
  28. /**
  29. * setup_sata() - Configure the SerDes device to SATA mode
  30. * @dev: The device to configure
  31. */
  32. static void setup_sata(struct udevice *dev)
  33. {
  34. struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);
  35. /* Set and clear reset bits */
  36. setbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_SATA_RESET);
  37. udelay(1000);
  38. clrbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_SATA_RESET);
  39. /* Configure SRDSCR0 */
  40. clrsetbits_be32(&priv->regs->srdscr0,
  41. SRDSCR0_TXEQA_MASK | SRDSCR0_TXEQE_MASK,
  42. SRDSCR0_TXEQA_SATA | SRDSCR0_TXEQE_SATA);
  43. /* Configure SRDSCR1 */
  44. clrbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);
  45. /* Configure SRDSCR2 */
  46. clrsetbits_be32(&priv->regs->srdscr2,
  47. SRDSCR2_SEIC_MASK,
  48. SRDSCR2_SEIC_SATA);
  49. /* Configure SRDSCR3 */
  50. out_be32(&priv->regs->srdscr3,
  51. SRDSCR3_KFR_SATA | SRDSCR3_KPH_SATA |
  52. SRDSCR3_SDFM_SATA_PEX | SRDSCR3_SDTXL_SATA);
  53. /* Configure SRDSCR4 */
  54. out_be32(&priv->regs->srdscr4, priv->rfcks | SRDSCR4_PROT_SATA);
  55. }
  56. /**
  57. * setup_pex() - Configure the SerDes device to PCI Express mode
  58. * @dev: The device to configure
  59. * @type: The PCI Express type to configure for (x1 or x2)
  60. */
  61. static void setup_pex(struct udevice *dev, enum pex_type type)
  62. {
  63. struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);
  64. /* Configure SRDSCR1 */
  65. setbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);
  66. /* Configure SRDSCR2 */
  67. clrsetbits_be32(&priv->regs->srdscr2,
  68. SRDSCR2_SEIC_MASK,
  69. SRDSCR2_SEIC_PEX);
  70. /* Configure SRDSCR3 */
  71. out_be32(&priv->regs->srdscr3, SRDSCR3_SDFM_SATA_PEX);
  72. /* Configure SRDSCR4 */
  73. if (type == PEX_X2)
  74. out_be32(&priv->regs->srdscr4,
  75. priv->rfcks | SRDSCR4_PROT_PEX | SRDSCR4_PLANE_X2);
  76. else
  77. out_be32(&priv->regs->srdscr4,
  78. priv->rfcks | SRDSCR4_PROT_PEX);
  79. }
  80. /**
  81. * setup_sgmii() - Configure the SerDes device to SGMII mode
  82. * @dev: The device to configure
  83. */
  84. static void setup_sgmii(struct udevice *dev)
  85. {
  86. struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);
  87. /* Configure SRDSCR1 */
  88. clrbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);
  89. /* Configure SRDSCR2 */
  90. clrsetbits_be32(&priv->regs->srdscr2,
  91. SRDSCR2_SEIC_MASK,
  92. SRDSCR2_SEIC_SGMII);
  93. /* Configure SRDSCR3 */
  94. out_be32(&priv->regs->srdscr3, 0);
  95. /* Configure SRDSCR4 */
  96. out_be32(&priv->regs->srdscr4, priv->rfcks | SRDSCR4_PROT_SGMII);
  97. }
  98. static int mpc83xx_serdes_probe(struct udevice *dev)
  99. {
  100. struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);
  101. bool vdd;
  102. const char *proto;
  103. priv->regs = map_sysmem(dev_read_addr(dev),
  104. sizeof(struct mpc83xx_serdes_regs));
  105. switch (dev_read_u32_default(dev, "serdes-clk", -1)) {
  106. case 100:
  107. priv->rfcks = SRDSCR4_RFCKS_100;
  108. break;
  109. case 125:
  110. priv->rfcks = SRDSCR4_RFCKS_125;
  111. break;
  112. case 150:
  113. priv->rfcks = SRDSCR4_RFCKS_150;
  114. break;
  115. default:
  116. debug("%s: Could not read serdes clock value\n", dev->name);
  117. return -EINVAL;
  118. }
  119. vdd = dev_read_bool(dev, "vdd");
  120. /* 1.0V corevdd */
  121. if (vdd) {
  122. /* DPPE/DPPA = 0 */
  123. clrbits_be32(&priv->regs->srdscr0, SRDSCR0_DPP_1V2);
  124. /* VDD = 0 */
  125. clrbits_be32(&priv->regs->srdscr0, SRDSCR2_VDD_1V2);
  126. }
  127. proto = dev_read_string(dev, "proto");
  128. /* protocol specific configuration */
  129. if (!strcmp(proto, "sata")) {
  130. setup_sata(dev);
  131. } else if (!strcmp(proto, "pex")) {
  132. setup_pex(dev, PEX_X1);
  133. } else if (!strcmp(proto, "pex-x2")) {
  134. setup_pex(dev, PEX_X2);
  135. } else if (!strcmp(proto, "sgmii")) {
  136. setup_sgmii(dev);
  137. } else {
  138. debug("%s: Invalid protocol value %s\n", dev->name, proto);
  139. return -EINVAL;
  140. }
  141. /* Do a software reset */
  142. setbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_RST);
  143. return 0;
  144. }
  145. static const struct udevice_id mpc83xx_serdes_ids[] = {
  146. { .compatible = "fsl,mpc83xx-serdes" },
  147. { }
  148. };
  149. U_BOOT_DRIVER(mpc83xx_serdes) = {
  150. .name = "mpc83xx_serdes",
  151. .id = UCLASS_MISC,
  152. .of_match = mpc83xx_serdes_ids,
  153. .probe = mpc83xx_serdes_probe,
  154. .priv_auto = sizeof(struct mpc83xx_serdes_priv),
  155. };