gdsys_ioep.h 4.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2018
  4. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  5. */
  6. #ifndef __GDSYS_IOEP_H_
  7. #define __GDSYS_IOEP_H_
  8. /**
  9. * struct io_generic_packet - header structure for GDSYS IOEP packets
  10. * @target_address: Target protocol address of the packet.
  11. * @source_address: Source protocol address of the packet.
  12. * @packet_type: Packet type.
  13. * @bc: Block counter (filled in by FPGA).
  14. * @packet_length: Length of the packet's payload bytes.
  15. */
  16. #include <linux/bitops.h>
  17. struct io_generic_packet {
  18. u16 target_address;
  19. u16 source_address;
  20. u8 packet_type;
  21. u8 bc;
  22. u16 packet_length;
  23. } __attribute__((__packed__));
  24. /**
  25. * struct gdsys_ioep_regs - Registers of a IOEP device
  26. * @transmit_data: Register that receives data to be sent
  27. * @tx_control: TX control register
  28. * @receive_data: Register filled with the received data
  29. * @rx_tx_status: RX/TX status register
  30. * @device_address: Register for setting/reading the device's address
  31. * @target_address: Register for setting/reading the remote endpoint's address
  32. * @int_enable: Interrupt/Interrupt enable register
  33. */
  34. struct gdsys_ioep_regs {
  35. u16 transmit_data;
  36. u16 tx_control;
  37. u16 receive_data;
  38. u16 rx_tx_status;
  39. u16 device_address;
  40. u16 target_address;
  41. u16 int_enable;
  42. };
  43. /**
  44. * gdsys_ioep_set() - Convenience macro to write registers of a IOEP device
  45. * @map: Register map to write the value in
  46. * @member: Name of the member in the gdsys_ioep_regs structure to write
  47. * @val: Value to write to the register
  48. */
  49. #define gdsys_ioep_set(map, member, val) \
  50. regmap_set(map, struct gdsys_ioep_regs, member, val)
  51. /**
  52. * gdsys_ioep_get() - Convenience macro to read registers of a IOEP device
  53. * @map: Register map to read the value from
  54. * @member: Name of the member in the gdsys_ioep_regs structure to read
  55. * @valp: Pointer to buffer to read the register value into
  56. */
  57. #define gdsys_ioep_get(map, member, valp) \
  58. regmap_get(map, struct gdsys_ioep_regs, member, valp)
  59. /**
  60. * enum rx_tx_status_values - Enum to describe the fields of the rx_tx_status
  61. * register
  62. * @STATE_TX_PACKET_BUILDING: The device is currently building a packet
  63. * (and accepting data for it)
  64. * @STATE_TX_TRANSMITTING: A packet is currenly being transmitted
  65. * @STATE_TX_BUFFER_FULL: The TX buffer is full
  66. * @STATE_TX_ERR: A TX error occurred
  67. * @STATE_RECEIVE_TIMEOUT: A receive timeout occurred
  68. * @STATE_PROC_RX_STORE_TIMEOUT: A RX store timeout for a processor packet
  69. * occurred
  70. * @STATE_PROC_RX_RECEIVE_TIMEOUT: A RX receive timeout for a processor packet
  71. * occurred
  72. * @STATE_RX_DIST_ERR: A error occurred in the distribution block
  73. * @STATE_RX_LENGTH_ERR: A length invalid error occurred
  74. * @STATE_RX_FRAME_CTR_ERR: A frame count error occurred (two
  75. * non-increasing frame count numbers
  76. * encountered)
  77. * @STATE_RX_FCS_ERR: A CRC error occurred
  78. * @STATE_RX_PACKET_DROPPED: A RX packet has been dropped
  79. * @STATE_RX_DATA_LAST: The data to be read is the final data of the
  80. * current packet
  81. * @STATE_RX_DATA_FIRST: The data to be read is the first data of the
  82. * current packet
  83. * @STATE_RX_DATA_AVAILABLE: RX data is available to be read
  84. */
  85. enum rx_tx_status_values {
  86. STATE_TX_PACKET_BUILDING = BIT(0),
  87. STATE_TX_TRANSMITTING = BIT(1),
  88. STATE_TX_BUFFER_FULL = BIT(2),
  89. STATE_TX_ERR = BIT(3),
  90. STATE_RECEIVE_TIMEOUT = BIT(4),
  91. STATE_PROC_RX_STORE_TIMEOUT = BIT(5),
  92. STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6),
  93. STATE_RX_DIST_ERR = BIT(7),
  94. STATE_RX_LENGTH_ERR = BIT(8),
  95. STATE_RX_FRAME_CTR_ERR = BIT(9),
  96. STATE_RX_FCS_ERR = BIT(10),
  97. STATE_RX_PACKET_DROPPED = BIT(11),
  98. STATE_RX_DATA_LAST = BIT(12),
  99. STATE_RX_DATA_FIRST = BIT(13),
  100. STATE_RX_DATA_AVAILABLE = BIT(15),
  101. };
  102. /**
  103. * enum tx_control_values - Enum to describe the fields of the tx_control
  104. * register
  105. * @CTRL_PROC_RECEIVE_ENABLE: Enable packet reception for the processor
  106. * @CTRL_FLUSH_TRANSMIT_BUFFER: Flush the transmit buffer (and send packet data)
  107. */
  108. enum tx_control_values {
  109. CTRL_PROC_RECEIVE_ENABLE = BIT(12),
  110. CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15),
  111. };
  112. /**
  113. * enum int_enable_values - Enum to describe the fields of the int_enable
  114. * register
  115. * @IRQ_CPU_TRANSMITBUFFER_FREE_STATUS: The transmit buffer is free (packet
  116. * data can be transmitted to the
  117. * device)
  118. * @IRQ_CPU_PACKET_TRANSMITTED_EVENT: A packet has been transmitted
  119. * @IRQ_NEW_CPU_PACKET_RECEIVED_EVENT: A new packet has been received
  120. * @IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS: RX packet data are available to be
  121. * read
  122. */
  123. enum int_enable_values {
  124. IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5),
  125. IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6),
  126. IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7),
  127. IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8),
  128. };
  129. #endif /* __GDSYS_IOEP_H_ */