Kconfig 17 KB

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  1. #
  2. # Multifunction miscellaneous devices
  3. #
  4. menu "Multifunction device drivers"
  5. config MISC
  6. bool "Enable Driver Model for Misc drivers"
  7. depends on DM
  8. help
  9. Enable driver model for miscellaneous devices. This class is
  10. used only for those do not fit other more general classes. A
  11. set of generic read, write and ioctl methods may be used to
  12. access the device.
  13. config SPL_MISC
  14. bool "Enable Driver Model for Misc drivers in SPL"
  15. depends on SPL_DM
  16. help
  17. Enable driver model for miscellaneous devices. This class is
  18. used only for those do not fit other more general classes. A
  19. set of generic read, write and ioctl methods may be used to
  20. access the device.
  21. config TPL_MISC
  22. bool "Enable Driver Model for Misc drivers in TPL"
  23. depends on TPL_DM
  24. help
  25. Enable driver model for miscellaneous devices. This class is
  26. used only for those do not fit other more general classes. A
  27. set of generic read, write and ioctl methods may be used to
  28. access the device.
  29. config ALTERA_SYSID
  30. bool "Altera Sysid support"
  31. depends on MISC
  32. help
  33. Select this to enable a sysid for Altera devices. Please find
  34. details on the "Embedded Peripherals IP User Guide" of Altera.
  35. config ATSHA204A
  36. bool "Support for Atmel ATSHA204A module"
  37. depends on MISC
  38. help
  39. Enable support for I2C connected Atmel's ATSHA204A
  40. CryptoAuthentication module found for example on the Turris Omnia
  41. board.
  42. config ROCKCHIP_EFUSE
  43. bool "Rockchip e-fuse support"
  44. depends on MISC
  45. help
  46. Enable (read-only) access for the e-fuse block found in Rockchip
  47. SoCs: accesses can either be made using byte addressing and a length
  48. or through child-nodes that are generated based on the e-fuse map
  49. retrieved from the DTS.
  50. This driver currently supports the RK3399 only, but can easily be
  51. extended (by porting the read function from the Linux kernel sources)
  52. to support other recent Rockchip devices.
  53. config ROCKCHIP_OTP
  54. bool "Rockchip OTP Support"
  55. depends on MISC
  56. help
  57. Enable (read-only) access for the one-time-programmable memory block
  58. found in Rockchip SoCs: accesses can either be made using byte
  59. addressing and a length or through child-nodes that are generated
  60. based on the e-fuse map retrieved from the DTS.
  61. config SIFIVE_OTP
  62. bool "SiFive eMemory OTP driver"
  63. depends on MISC
  64. help
  65. Enable support for reading and writing the eMemory OTP on the
  66. SiFive SoCs.
  67. config STARFIVE_OTP
  68. bool "StarFive eFuse OTP driver"
  69. depends on MISC
  70. help
  71. Enable support for reading and writing the eFuse OTP on the
  72. StarFive SoCs.
  73. config VEXPRESS_CONFIG
  74. bool "Enable support for Arm Versatile Express config bus"
  75. depends on MISC
  76. help
  77. If you say Y here, you will get support for accessing the
  78. configuration bus on the Arm Versatile Express boards via
  79. a sysreg driver.
  80. config CMD_CROS_EC
  81. bool "Enable crosec command"
  82. depends on CROS_EC
  83. help
  84. Enable command-line access to the Chrome OS EC (Embedded
  85. Controller). This provides the 'crosec' command which has
  86. a number of sub-commands for performing EC tasks such as
  87. updating its flash, accessing a small saved context area
  88. and talking to the I2C bus behind the EC (if there is one).
  89. config CROS_EC
  90. bool "Enable Chrome OS EC"
  91. help
  92. Enable access to the Chrome OS EC. This is a separate
  93. microcontroller typically available on a SPI bus on Chromebooks. It
  94. provides access to the keyboard, some internal storage and may
  95. control access to the battery and main PMIC depending on the
  96. device. You can use the 'crosec' command to access it.
  97. config SPL_CROS_EC
  98. bool "Enable Chrome OS EC in SPL"
  99. depends on SPL
  100. help
  101. Enable access to the Chrome OS EC in SPL. This is a separate
  102. microcontroller typically available on a SPI bus on Chromebooks. It
  103. provides access to the keyboard, some internal storage and may
  104. control access to the battery and main PMIC depending on the
  105. device. You can use the 'crosec' command to access it.
  106. config TPL_CROS_EC
  107. bool "Enable Chrome OS EC in TPL"
  108. depends on TPL
  109. help
  110. Enable access to the Chrome OS EC in TPL. This is a separate
  111. microcontroller typically available on a SPI bus on Chromebooks. It
  112. provides access to the keyboard, some internal storage and may
  113. control access to the battery and main PMIC depending on the
  114. device. You can use the 'crosec' command to access it.
  115. config CROS_EC_I2C
  116. bool "Enable Chrome OS EC I2C driver"
  117. depends on CROS_EC
  118. help
  119. Enable I2C access to the Chrome OS EC. This is used on older
  120. ARM Chromebooks such as snow and spring before the standard bus
  121. changed to SPI. The EC will accept commands across the I2C using
  122. a special message protocol, and provide responses.
  123. config CROS_EC_LPC
  124. bool "Enable Chrome OS EC LPC driver"
  125. depends on CROS_EC
  126. help
  127. Enable I2C access to the Chrome OS EC. This is used on x86
  128. Chromebooks such as link and falco. The keyboard is provided
  129. through a legacy port interface, so on x86 machines the main
  130. function of the EC is power and thermal management.
  131. config SPL_CROS_EC_LPC
  132. bool "Enable Chrome OS EC LPC driver in SPL"
  133. depends on CROS_EC
  134. help
  135. Enable I2C access to the Chrome OS EC. This is used on x86
  136. Chromebooks such as link and falco. The keyboard is provided
  137. through a legacy port interface, so on x86 machines the main
  138. function of the EC is power and thermal management.
  139. config TPL_CROS_EC_LPC
  140. bool "Enable Chrome OS EC LPC driver in TPL"
  141. depends on CROS_EC
  142. help
  143. Enable I2C access to the Chrome OS EC. This is used on x86
  144. Chromebooks such as link and falco. The keyboard is provided
  145. through a legacy port interface, so on x86 machines the main
  146. function of the EC is power and thermal management.
  147. config CROS_EC_SANDBOX
  148. bool "Enable Chrome OS EC sandbox driver"
  149. depends on CROS_EC && SANDBOX
  150. help
  151. Enable a sandbox emulation of the Chrome OS EC. This supports
  152. keyboard (use the -l flag to enable the LCD), verified boot context,
  153. EC flash read/write/erase support and a few other things. It is
  154. enough to perform a Chrome OS verified boot on sandbox.
  155. config SPL_CROS_EC_SANDBOX
  156. bool "Enable Chrome OS EC sandbox driver in SPL"
  157. depends on SPL_CROS_EC && SANDBOX
  158. help
  159. Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
  160. keyboard (use the -l flag to enable the LCD), verified boot context,
  161. EC flash read/write/erase support and a few other things. It is
  162. enough to perform a Chrome OS verified boot on sandbox.
  163. config TPL_CROS_EC_SANDBOX
  164. bool "Enable Chrome OS EC sandbox driver in TPL"
  165. depends on TPL_CROS_EC && SANDBOX
  166. help
  167. Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
  168. keyboard (use the -l flag to enable the LCD), verified boot context,
  169. EC flash read/write/erase support and a few other things. It is
  170. enough to perform a Chrome OS verified boot on sandbox.
  171. config CROS_EC_SPI
  172. bool "Enable Chrome OS EC SPI driver"
  173. depends on CROS_EC
  174. help
  175. Enable SPI access to the Chrome OS EC. This is used on newer
  176. ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
  177. provides a faster and more robust interface than I2C but the bugs
  178. are less interesting.
  179. config DS4510
  180. bool "Enable support for DS4510 CPU supervisor"
  181. help
  182. Enable support for the Maxim DS4510 CPU supervisor. It has an
  183. integrated 64-byte EEPROM, four programmable non-volatile I/O pins
  184. and a configurable timer for the supervisor function. The device is
  185. connected over I2C.
  186. config FSL_SEC_MON
  187. bool "Enable FSL SEC_MON Driver"
  188. help
  189. Freescale Security Monitor block is responsible for monitoring
  190. system states.
  191. Security Monitor can be transitioned on any security failures,
  192. like software violations or hardware security violations.
  193. config IRQ
  194. bool "Interrupt controller"
  195. help
  196. This enables support for interrupt controllers, including ITSS.
  197. Some devices have extra features, such as Apollo Lake. The
  198. device has its own uclass since there are several operations
  199. involved.
  200. config JZ4780_EFUSE
  201. bool "Ingenic JZ4780 eFUSE support"
  202. depends on ARCH_JZ47XX
  203. help
  204. This selects support for the eFUSE on Ingenic JZ4780 SoCs.
  205. config MXC_OCOTP
  206. bool "Enable MXC OCOTP Driver"
  207. depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
  208. default y
  209. help
  210. If you say Y here, you will get support for the One Time
  211. Programmable memory pages that are stored on the some
  212. Freescale i.MX processors.
  213. config NUVOTON_NCT6102D
  214. bool "Enable Nuvoton NCT6102D Super I/O driver"
  215. help
  216. If you say Y here, you will get support for the Nuvoton
  217. NCT6102D Super I/O driver. This can be used to enable or
  218. disable the legacy UART, the watchdog or other devices
  219. in the Nuvoton Super IO chips on X86 platforms.
  220. config P2SB
  221. bool "Intel Primary to Sideband Bridge"
  222. depends on X86 || SANDBOX
  223. help
  224. This enables support for the Intel Primary to Sideband Bridge,
  225. abbreviated to P2SB. The P2SB is used to access various peripherals
  226. such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
  227. space. The space is segmented into different channels and peripherals
  228. are accessed by device-specific means within those channels. Devices
  229. should be added in the device tree as subnodes of the P2SB. A
  230. Peripheral Channel Register? (PCR) API is provided to access those
  231. devices - see pcr_readl(), etc.
  232. config SPL_P2SB
  233. bool "Intel Primary to Sideband Bridge in SPL"
  234. depends on SPL && (X86 || SANDBOX)
  235. help
  236. The Primary to Sideband Bridge is used to access various peripherals
  237. through memory-mapped I/O in a large chunk of PCI space. The space is
  238. segmented into different channels and peripherals are accessed by
  239. device-specific means within those channels. Devices should be added
  240. in the device tree as subnodes of the p2sb.
  241. config TPL_P2SB
  242. bool "Intel Primary to Sideband Bridge in TPL"
  243. depends on TPL && (X86 || SANDBOX)
  244. help
  245. The Primary to Sideband Bridge is used to access various peripherals
  246. through memory-mapped I/O in a large chunk of PCI space. The space is
  247. segmented into different channels and peripherals are accessed by
  248. device-specific means within those channels. Devices should be added
  249. in the device tree as subnodes of the p2sb.
  250. config PWRSEQ
  251. bool "Enable power-sequencing drivers"
  252. depends on DM
  253. help
  254. Power-sequencing drivers provide support for controlling power for
  255. devices. They are typically referenced by a phandle from another
  256. device. When the device is started up, its power sequence can be
  257. initiated.
  258. config SPL_PWRSEQ
  259. bool "Enable power-sequencing drivers for SPL"
  260. depends on PWRSEQ
  261. help
  262. Power-sequencing drivers provide support for controlling power for
  263. devices. They are typically referenced by a phandle from another
  264. device. When the device is started up, its power sequence can be
  265. initiated.
  266. config PCA9551_LED
  267. bool "Enable PCA9551 LED driver"
  268. help
  269. Enable driver for PCA9551 LED controller. This controller
  270. is connected via I2C. So I2C needs to be enabled.
  271. config PCA9551_I2C_ADDR
  272. hex "I2C address of PCA9551 LED controller"
  273. depends on PCA9551_LED
  274. default 0x60
  275. help
  276. The I2C address of the PCA9551 LED controller.
  277. config STM32MP_FUSE
  278. bool "Enable STM32MP fuse wrapper providing the fuse API"
  279. depends on ARCH_STM32MP && MISC
  280. default y if CMD_FUSE
  281. help
  282. If you say Y here, you will get support for the fuse API (OTP)
  283. for STM32MP architecture.
  284. This API is needed for CMD_FUSE.
  285. config STM32_RCC
  286. bool "Enable RCC driver for the STM32 SoC's family"
  287. depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
  288. help
  289. Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
  290. block) is responsible of the management of the clock and reset
  291. generation.
  292. This driver is similar to an MFD driver in the Linux kernel.
  293. config TEGRA_CAR
  294. bool "Enable support for the Tegra CAR driver"
  295. depends on TEGRA_NO_BPMP
  296. help
  297. The Tegra CAR (Clock and Reset Controller) is a HW module that
  298. controls almost all clocks and resets in a Tegra SoC.
  299. config TEGRA186_BPMP
  300. bool "Enable support for the Tegra186 BPMP driver"
  301. depends on TEGRA186
  302. help
  303. The Tegra BPMP (Boot and Power Management Processor) is a separate
  304. auxiliary CPU embedded into Tegra to perform power management work,
  305. and controls related features such as clocks, resets, power domains,
  306. PMIC I2C bus, etc. This driver provides the core low-level
  307. communication path by which feature-specific drivers (such as clock)
  308. can make requests to the BPMP. This driver is similar to an MFD
  309. driver in the Linux kernel.
  310. config TEST_DRV
  311. bool "Enable support for test drivers"
  312. default y if SANDBOX
  313. help
  314. This enables drivers and uclasses that provides a way of testing the
  315. operations of memory allocation and driver/uclass methods in driver
  316. model. This should only be enabled for testing as it is not useful for
  317. anything else.
  318. config TWL4030_LED
  319. bool "Enable TWL4030 LED controller"
  320. help
  321. Enable this to add support for the TWL4030 LED controller.
  322. config WINBOND_W83627
  323. bool "Enable Winbond Super I/O driver"
  324. help
  325. If you say Y here, you will get support for the Winbond
  326. W83627 Super I/O driver. This can be used to enable the
  327. legacy UART or other devices in the Winbond Super IO chips
  328. on X86 platforms.
  329. config QFW
  330. bool
  331. help
  332. Hidden option to enable QEMU fw_cfg interface and uclass. This will
  333. be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
  334. config QFW_PIO
  335. bool
  336. depends on QFW
  337. help
  338. Hidden option to enable PIO QEMU fw_cfg interface. This will be
  339. selected by the appropriate QEMU board.
  340. config QFW_MMIO
  341. bool
  342. depends on QFW
  343. help
  344. Hidden option to enable MMIO QEMU fw_cfg interface. This will be
  345. selected by the appropriate QEMU board.
  346. config I2C_EEPROM
  347. bool "Enable driver for generic I2C-attached EEPROMs"
  348. depends on MISC
  349. help
  350. Enable a generic driver for EEPROMs attached via I2C.
  351. config SPL_I2C_EEPROM
  352. bool "Enable driver for generic I2C-attached EEPROMs for SPL"
  353. depends on MISC && SPL && SPL_DM
  354. help
  355. This option is an SPL-variant of the I2C_EEPROM option.
  356. See the help of I2C_EEPROM for details.
  357. if I2C_EEPROM
  358. config SYS_I2C_EEPROM_ADDR
  359. hex "Chip address of the EEPROM device"
  360. default 0
  361. config SYS_I2C_EEPROM_BUS
  362. int "I2C bus of the EEPROM device."
  363. default 0
  364. config SYS_EEPROM_SIZE
  365. int "Size in bytes of the EEPROM device"
  366. default 256
  367. config SYS_EEPROM_PAGE_WRITE_BITS
  368. int "Number of bits used to address bytes in a single page"
  369. default 0
  370. help
  371. The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
  372. A 64 byte page, for example would require six bits.
  373. config SYS_EEPROM_PAGE_WRITE_DELAY_MS
  374. int "Number of milliseconds to delay between page writes"
  375. default 0
  376. config SYS_I2C_EEPROM_ADDR_LEN
  377. int "Length in bytes of the EEPROM memory array address"
  378. default 1
  379. help
  380. Note: This is NOT the chip address length!
  381. config SYS_I2C_EEPROM_ADDR_OVERFLOW
  382. hex "EEPROM Address Overflow"
  383. default 0
  384. help
  385. EEPROM chips that implement "address overflow" are ones
  386. like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  387. address and the extra bits end up in the "chip address" bit
  388. slots. This makes a 24WC08 (1Kbyte) chip look like four 256
  389. byte chips.
  390. endif
  391. config GDSYS_RXAUI_CTRL
  392. bool "Enable gdsys RXAUI control driver"
  393. depends on MISC
  394. help
  395. Support gdsys FPGA's RXAUI control.
  396. config GDSYS_IOEP
  397. bool "Enable gdsys IOEP driver"
  398. depends on MISC
  399. help
  400. Support gdsys FPGA's IO endpoint driver.
  401. config MPC83XX_SERDES
  402. bool "Enable MPC83xx serdes driver"
  403. depends on MISC
  404. help
  405. Support for serdes found on MPC83xx SoCs.
  406. config FS_LOADER
  407. bool "Enable loader driver for file system"
  408. help
  409. This is file system generic loader which can be used to load
  410. the file image from the storage into target such as memory.
  411. The consumer driver would then use this loader to program whatever,
  412. ie. the FPGA device.
  413. config GDSYS_SOC
  414. bool "Enable gdsys SOC driver"
  415. depends on MISC
  416. help
  417. Support for gdsys IHS SOC, a simple bus associated with each gdsys
  418. IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
  419. register maps are contained within the FPGA's register map.
  420. config IHS_FPGA
  421. bool "Enable IHS FPGA driver"
  422. depends on MISC
  423. help
  424. Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
  425. gdsys devices, which supply the majority of the functionality offered
  426. by the devices. This driver supports both CON and CPU variants of the
  427. devices, depending on the device tree entry.
  428. config ESM_K3
  429. bool "Enable K3 ESM driver"
  430. depends on ARCH_K3
  431. help
  432. Support ESM (Error Signaling Module) on TI K3 SoCs.
  433. config MICROCHIP_FLEXCOM
  434. bool "Enable Microchip Flexcom driver"
  435. depends on MISC
  436. help
  437. The Atmel Flexcom is just a wrapper which embeds a SPI controller,
  438. an I2C controller and an USART.
  439. Only one function can be used at a time and is chosen at boot time
  440. according to the device tree.
  441. config K3_AVS0
  442. depends on ARCH_K3 && SPL_DM_REGULATOR
  443. bool "AVS class 0 support for K3 devices"
  444. help
  445. K3 devices have the optimized voltage values for the main voltage
  446. domains stored in efuse within the VTM IP. This driver reads the
  447. optimized voltage from the efuse, so that it can be programmed
  448. to the PMIC on board.
  449. config ESM_PMIC
  450. bool "Enable PMIC ESM driver"
  451. depends on DM_PMIC
  452. help
  453. Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
  454. typically to reboot the board in error condition.
  455. endmenu