xilinx_xiic.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Xilinx AXI I2C driver
  4. *
  5. * Copyright (C) 2018 Marek Vasut <marex@denx.de>
  6. *
  7. * Based on Linux 4.14.y i2c-xiic.c
  8. * Copyright (c) 2002-2007 Xilinx Inc.
  9. * Copyright (c) 2009-2010 Intel Corporation
  10. */
  11. #include <common.h>
  12. #include <clk.h>
  13. #include <dm.h>
  14. #include <i2c.h>
  15. #include <wait_bit.h>
  16. #include <asm/io.h>
  17. #include <dm/device_compat.h>
  18. struct xilinx_xiic_priv {
  19. void __iomem *base;
  20. struct clk clk;
  21. };
  22. #define XIIC_MSB_OFFSET 0
  23. #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
  24. /*
  25. * Register offsets in bytes from RegisterBase. Three is added to the
  26. * base offset to access LSB (IBM style) of the word
  27. */
  28. #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
  29. #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
  30. #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
  31. #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
  32. #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
  33. #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
  34. #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
  35. #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
  36. #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
  37. #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
  38. /* Control Register masks */
  39. #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
  40. #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
  41. #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
  42. #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
  43. #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
  44. #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
  45. #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
  46. /* Status Register masks */
  47. #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
  48. #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
  49. #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
  50. #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
  51. #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
  52. #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
  53. #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
  54. #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
  55. /* Interrupt Status Register masks Interrupt occurs when... */
  56. #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
  57. #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
  58. #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
  59. #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
  60. #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
  61. #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
  62. #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
  63. #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
  64. /* The following constants specify the depth of the FIFOs */
  65. #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
  66. #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
  67. /*
  68. * Tx Fifo upper bit masks.
  69. */
  70. #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
  71. #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
  72. /*
  73. * The following constants define the register offsets for the Interrupt
  74. * registers. There are some holes in the memory map for reserved addresses
  75. * to allow other registers to be added and still match the memory map of the
  76. * interrupt controller registers
  77. */
  78. #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
  79. #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
  80. #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
  81. #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
  82. #define XIIC_RESET_MASK 0xAUL
  83. static u8 i2c_8bit_addr_from_flags(uint addr, u16 flags)
  84. {
  85. return (addr << 1) | (flags & I2C_M_RD ? 1 : 0);
  86. }
  87. static void xiic_irq_clr(struct xilinx_xiic_priv *priv, u32 mask)
  88. {
  89. u32 isr = readl(priv->base + XIIC_IISR_OFFSET);
  90. writel(isr & mask, priv->base + XIIC_IISR_OFFSET);
  91. }
  92. static int xiic_read_rx(struct xilinx_xiic_priv *priv,
  93. struct i2c_msg *msg, int nmsgs)
  94. {
  95. u8 bytes_in_fifo;
  96. u32 pos = 0;
  97. int i, ret;
  98. while (pos < msg->len) {
  99. ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,
  100. XIIC_SR_RX_FIFO_EMPTY_MASK, false,
  101. 1000, true);
  102. if (ret)
  103. return ret;
  104. bytes_in_fifo = readb(priv->base + XIIC_RFO_REG_OFFSET) + 1;
  105. if (bytes_in_fifo > msg->len)
  106. bytes_in_fifo = msg->len;
  107. for (i = 0; i < bytes_in_fifo; i++) {
  108. msg->buf[pos++] = readb(priv->base +
  109. XIIC_DRR_REG_OFFSET);
  110. }
  111. }
  112. return 0;
  113. }
  114. static int xiic_tx_fifo_space(struct xilinx_xiic_priv *priv)
  115. {
  116. /* return the actual space left in the FIFO */
  117. return IIC_TX_FIFO_DEPTH - readb(priv->base + XIIC_TFO_REG_OFFSET) - 1;
  118. }
  119. static void xiic_fill_tx_fifo(struct xilinx_xiic_priv *priv,
  120. struct i2c_msg *msg, int nmsgs)
  121. {
  122. u8 fifo_space = xiic_tx_fifo_space(priv);
  123. int len = msg->len;
  124. u32 pos = 0;
  125. len = (len > fifo_space) ? fifo_space : len;
  126. while (len--) {
  127. u16 data = msg->buf[pos++];
  128. if ((msg->len - pos == 0) && nmsgs == 1) {
  129. /* last message in transfer -> STOP */
  130. data |= XIIC_TX_DYN_STOP_MASK;
  131. }
  132. writew(data, priv->base + XIIC_DTR_REG_OFFSET);
  133. }
  134. }
  135. static void xilinx_xiic_set_addr(struct udevice *dev, u8 addr,
  136. u16 flags, u32 len, u32 nmsgs)
  137. {
  138. struct xilinx_xiic_priv *priv = dev_get_priv(dev);
  139. xiic_irq_clr(priv, XIIC_INTR_TX_ERROR_MASK);
  140. if (!(flags & I2C_M_NOSTART)) {
  141. /* write the address */
  142. u16 data = i2c_8bit_addr_from_flags(addr, flags) |
  143. XIIC_TX_DYN_START_MASK;
  144. if (nmsgs == 1 && len == 0)
  145. /* no data and last message -> add STOP */
  146. data |= XIIC_TX_DYN_STOP_MASK;
  147. writew(data, priv->base + XIIC_DTR_REG_OFFSET);
  148. }
  149. }
  150. static int xilinx_xiic_read_common(struct udevice *dev, struct i2c_msg *msg,
  151. u32 nmsgs)
  152. {
  153. struct xilinx_xiic_priv *priv = dev_get_priv(dev);
  154. u8 rx_watermark;
  155. /* Clear and enable Rx full interrupt. */
  156. xiic_irq_clr(priv, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
  157. /* we want to get all but last byte, because the TX_ERROR IRQ is used
  158. * to inidicate error ACK on the address, and negative ack on the last
  159. * received byte, so to not mix them receive all but last.
  160. * In the case where there is only one byte to receive
  161. * we can check if ERROR and RX full is set at the same time
  162. */
  163. rx_watermark = msg->len;
  164. if (rx_watermark > IIC_RX_FIFO_DEPTH)
  165. rx_watermark = IIC_RX_FIFO_DEPTH;
  166. writeb(rx_watermark - 1, priv->base + XIIC_RFD_REG_OFFSET);
  167. xilinx_xiic_set_addr(dev, msg->addr, msg->flags, msg->len, nmsgs);
  168. xiic_irq_clr(priv, XIIC_INTR_BNB_MASK);
  169. writew((msg->len & 0xff) | ((nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0),
  170. priv->base + XIIC_DTR_REG_OFFSET);
  171. if (nmsgs == 1)
  172. /* very last, enable bus not busy as well */
  173. xiic_irq_clr(priv, XIIC_INTR_BNB_MASK);
  174. return xiic_read_rx(priv, msg, nmsgs);
  175. }
  176. static int xilinx_xiic_write_common(struct udevice *dev, struct i2c_msg *msg,
  177. int nmsgs)
  178. {
  179. struct xilinx_xiic_priv *priv = dev_get_priv(dev);
  180. int ret;
  181. xilinx_xiic_set_addr(dev, msg->addr, msg->flags, msg->len, nmsgs);
  182. xiic_fill_tx_fifo(priv, msg, nmsgs);
  183. ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,
  184. XIIC_SR_TX_FIFO_EMPTY_MASK, false, 1000, true);
  185. if (ret)
  186. return ret;
  187. /* Clear any pending Tx empty, Tx Error and then enable them. */
  188. xiic_irq_clr(priv, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
  189. XIIC_INTR_BNB_MASK);
  190. return 0;
  191. }
  192. static void xiic_clear_rx_fifo(struct xilinx_xiic_priv *priv)
  193. {
  194. u8 sr;
  195. for (sr = readb(priv->base + XIIC_SR_REG_OFFSET);
  196. !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
  197. sr = readb(priv->base + XIIC_SR_REG_OFFSET))
  198. readb(priv->base + XIIC_DRR_REG_OFFSET);
  199. }
  200. static void xiic_reinit(struct xilinx_xiic_priv *priv)
  201. {
  202. writel(XIIC_RESET_MASK, priv->base + XIIC_RESETR_OFFSET);
  203. /* Set receive Fifo depth to maximum (zero based). */
  204. writeb(IIC_RX_FIFO_DEPTH - 1, priv->base + XIIC_RFD_REG_OFFSET);
  205. /* Reset Tx Fifo. */
  206. writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET);
  207. /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
  208. writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET);
  209. /* make sure RX fifo is empty */
  210. xiic_clear_rx_fifo(priv);
  211. /* Disable interrupts */
  212. writel(0, priv->base + XIIC_DGIER_OFFSET);
  213. xiic_irq_clr(priv, XIIC_INTR_ARB_LOST_MASK);
  214. }
  215. static int xilinx_xiic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
  216. {
  217. struct xilinx_xiic_priv *priv = dev_get_priv(dev);
  218. int ret = 0;
  219. ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,
  220. XIIC_SR_BUS_BUSY_MASK, false, 1000, true);
  221. if (ret == -ETIMEDOUT)
  222. dev_err(dev, "timeout waiting for bus not busy condition\n");
  223. if (ret)
  224. return ret;
  225. xiic_reinit(priv);
  226. for (; nmsgs > 0; nmsgs--, msg++) {
  227. if (msg->flags & I2C_M_RD)
  228. ret = xilinx_xiic_read_common(dev, msg, nmsgs);
  229. else
  230. ret = xilinx_xiic_write_common(dev, msg, nmsgs);
  231. if (ret)
  232. return -EREMOTEIO;
  233. }
  234. return ret;
  235. }
  236. static int xilinx_xiic_probe_chip(struct udevice *dev, uint addr, uint flags)
  237. {
  238. struct xilinx_xiic_priv *priv = dev_get_priv(dev);
  239. u32 reg;
  240. int ret;
  241. xiic_reinit(priv);
  242. xilinx_xiic_set_addr(dev, addr, 0, 0, 1);
  243. ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,
  244. XIIC_SR_BUS_BUSY_MASK, false, 1000, true);
  245. if (ret)
  246. return ret;
  247. reg = readl(priv->base + XIIC_IISR_OFFSET);
  248. if (reg & XIIC_INTR_TX_ERROR_MASK)
  249. return -ENODEV;
  250. return 0;
  251. }
  252. static int xilinx_xiic_set_speed(struct udevice *dev, uint speed)
  253. {
  254. return 0;
  255. }
  256. static int xilinx_xiic_probe(struct udevice *dev)
  257. {
  258. struct xilinx_xiic_priv *priv = dev_get_priv(dev);
  259. priv->base = dev_read_addr_ptr(dev);
  260. writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET);
  261. xiic_reinit(priv);
  262. return 0;
  263. }
  264. static const struct dm_i2c_ops xilinx_xiic_ops = {
  265. .xfer = xilinx_xiic_xfer,
  266. .probe_chip = xilinx_xiic_probe_chip,
  267. .set_bus_speed = xilinx_xiic_set_speed,
  268. };
  269. static const struct udevice_id xilinx_xiic_ids[] = {
  270. { .compatible = "xlnx,xps-iic-2.00.a" },
  271. { }
  272. };
  273. U_BOOT_DRIVER(xilinx_xiic) = {
  274. .name = "xilinx_axi_i2c",
  275. .id = UCLASS_I2C,
  276. .of_match = xilinx_xiic_ids,
  277. .probe = xilinx_xiic_probe,
  278. .priv_auto = sizeof(struct xilinx_xiic_priv),
  279. .ops = &xilinx_xiic_ops,
  280. };