synquacer_i2c.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. */
  4. #include <dm/device_compat.h>
  5. #include <linux/delay.h>
  6. #include <linux/errno.h>
  7. #include <linux/io.h>
  8. #include <linux/sizes.h>
  9. #include <linux/types.h>
  10. #include <dm.h>
  11. #include <fdtdec.h>
  12. #include <i2c.h>
  13. #include <clk.h>
  14. #define REG_BSR 0x0
  15. #define REG_BCR 0x4
  16. #define REG_CCR 0x8
  17. #define REG_ADR 0xc
  18. #define REG_DAR 0x10
  19. #define REG_CSR 0x14
  20. #define REG_FSR 0x18
  21. #define REG_BC2R 0x1c
  22. /* I2C register bit definitions */
  23. #define BSR_FBT BIT(0) // First Byte Transfer
  24. #define BSR_GCA BIT(1) // General Call Address
  25. #define BSR_AAS BIT(2) // Address as Slave
  26. #define BSR_TRX BIT(3) // Transfer/Receive
  27. #define BSR_LRB BIT(4) // Last Received Bit
  28. #define BSR_AL BIT(5) // Arbitration Lost
  29. #define BSR_RSC BIT(6) // Repeated Start Cond.
  30. #define BSR_BB BIT(7) // Bus Busy
  31. #define BCR_INT BIT(0) // Interrupt
  32. #define BCR_INTE BIT(1) // Interrupt Enable
  33. #define BCR_GCAA BIT(2) // Gen. Call Access Ack.
  34. #define BCR_ACK BIT(3) // Acknowledge
  35. #define BCR_MSS BIT(4) // Master Slave Select
  36. #define BCR_SCC BIT(5) // Start Condition Cont.
  37. #define BCR_BEIE BIT(6) // Bus Error Int Enable
  38. #define BCR_BER BIT(7) // Bus Error
  39. #define CCR_CS_MASK (0x1f) // CCR Clock Period Sel.
  40. #define CCR_EN BIT(5) // Enable
  41. #define CCR_FM BIT(6) // Speed Mode Select
  42. #define CSR_CS_MASK (0x3f) // CSR Clock Period Sel.
  43. #define BC2R_SCLL BIT(0) // SCL Low Drive
  44. #define BC2R_SDAL BIT(1) // SDA Low Drive
  45. #define BC2R_SCLS BIT(4) // SCL Status
  46. #define BC2R_SDAS BIT(5) // SDA Status
  47. /* PCLK frequency */
  48. #define BUS_CLK_FR(rate) (((rate) / 20000000) + 1)
  49. #define I2C_CLK_DEF 62500000
  50. /* STANDARD MODE frequency */
  51. #define CLK_MASTER_STD(rate) \
  52. DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_SPEED_STANDARD_RATE) - 2, 2)
  53. /* FAST MODE frequency */
  54. #define CLK_MASTER_FAST(rate) \
  55. DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_SPEED_FAST_RATE) - 2) * 2, 3)
  56. /* (clkrate <= 18000000) */
  57. /* calculate the value of CS bits in CCR register on standard mode */
  58. #define CCR_CS_STD_MAX_18M(rate) \
  59. ((CLK_MASTER_STD(rate) - 65) \
  60. & CCR_CS_MASK)
  61. /* calculate the value of CS bits in CSR register on standard mode */
  62. #define CSR_CS_STD_MAX_18M(rate) 0x00
  63. /* calculate the value of CS bits in CCR register on fast mode */
  64. #define CCR_CS_FAST_MAX_18M(rate) \
  65. ((CLK_MASTER_FAST(rate) - 1) \
  66. & CCR_CS_MASK)
  67. /* calculate the value of CS bits in CSR register on fast mode */
  68. #define CSR_CS_FAST_MAX_18M(rate) 0x00
  69. /* (clkrate > 18000000) */
  70. /* calculate the value of CS bits in CCR register on standard mode */
  71. #define CCR_CS_STD_MIN_18M(rate) \
  72. ((CLK_MASTER_STD(rate) - 1) \
  73. & CCR_CS_MASK)
  74. /* calculate the value of CS bits in CSR register on standard mode */
  75. #define CSR_CS_STD_MIN_18M(rate) \
  76. (((CLK_MASTER_STD(rate) - 1) >> 5) \
  77. & CSR_CS_MASK)
  78. /* calculate the value of CS bits in CCR register on fast mode */
  79. #define CCR_CS_FAST_MIN_18M(rate) \
  80. ((CLK_MASTER_FAST(rate) - 1) \
  81. & CCR_CS_MASK)
  82. /* calculate the value of CS bits in CSR register on fast mode */
  83. #define CSR_CS_FAST_MIN_18M(rate) \
  84. (((CLK_MASTER_FAST(rate) - 1) >> 5) \
  85. & CSR_CS_MASK)
  86. /* min I2C clock frequency 14M */
  87. #define MIN_CLK_RATE (14 * 1000000)
  88. /* max I2C clock frequency 200M */
  89. #define MAX_CLK_RATE (200 * 1000000)
  90. /* I2C clock frequency 18M */
  91. #define CLK_RATE_18M (18 * 1000000)
  92. #define SPEED_FM 400 // Fast Mode
  93. #define SPEED_SM 100 // Standard Mode
  94. DECLARE_GLOBAL_DATA_PTR;
  95. struct synquacer_i2c {
  96. void __iomem *base;
  97. unsigned long pclkrate;
  98. unsigned long speed_khz;
  99. };
  100. static int wait_irq(struct udevice *dev)
  101. {
  102. struct synquacer_i2c *i2c = dev_get_priv(dev);
  103. int timeout = 500000;
  104. do {
  105. if (readb(i2c->base + REG_BCR) & BCR_INT)
  106. return 0;
  107. } while (timeout--);
  108. pr_err("%s: timeout\n", __func__);
  109. return -1;
  110. }
  111. static int synquacer_i2c_xfer_start(struct synquacer_i2c *i2c,
  112. int addr, int read)
  113. {
  114. u8 bsr, bcr;
  115. writeb((addr << 1) | (read ? 1 : 0), i2c->base + REG_DAR);
  116. bsr = readb(i2c->base + REG_BSR);
  117. bcr = readb(i2c->base + REG_BCR);
  118. if ((bsr & BSR_BB) && !(bcr & BCR_MSS))
  119. return -EBUSY;
  120. if (bsr & BSR_BB) {
  121. writeb(bcr | BCR_SCC, i2c->base + REG_BCR);
  122. } else {
  123. if (bcr & BCR_MSS)
  124. return -EAGAIN;
  125. /* Start Condition + Enable Interrupts */
  126. writeb(bcr | BCR_MSS | BCR_INTE | BCR_BEIE, i2c->base + REG_BCR);
  127. }
  128. udelay(100);
  129. return 0;
  130. }
  131. static int synquacer_i2c_xfer(struct udevice *bus,
  132. struct i2c_msg *msg, int nmsgs)
  133. {
  134. struct synquacer_i2c *i2c = dev_get_priv(bus);
  135. u8 bsr, bcr;
  136. int idx;
  137. for (; nmsgs > 0; nmsgs--, msg++) {
  138. synquacer_i2c_xfer_start(i2c, msg->addr, msg->flags & I2C_M_RD);
  139. if (wait_irq(bus))
  140. return -EREMOTEIO;
  141. bsr = readb(i2c->base + REG_BSR);
  142. if (bsr & BSR_LRB) {
  143. debug("%s: No ack received\n", __func__);
  144. return -EREMOTEIO;
  145. }
  146. idx = 0;
  147. do {
  148. bsr = readb(i2c->base + REG_BSR);
  149. bcr = readb(i2c->base + REG_BCR);
  150. if (bcr & BCR_BER) {
  151. debug("%s: Bus error detected\n", __func__);
  152. return -EREMOTEIO;
  153. }
  154. if ((bsr & BSR_AL) || !(bcr & BCR_MSS)) {
  155. debug("%s: Arbitration lost\n", __func__);
  156. return -EREMOTEIO;
  157. }
  158. if (msg->flags & I2C_M_RD) {
  159. bcr = BCR_MSS | BCR_INTE | BCR_BEIE;
  160. if (idx < msg->len - 1)
  161. bcr |= BCR_ACK;
  162. writeb(bcr, i2c->base + REG_BCR);
  163. if (wait_irq(bus))
  164. return -EREMOTEIO;
  165. bsr = readb(i2c->base + REG_BSR);
  166. if (!(bsr & BSR_FBT))
  167. msg->buf[idx++] = readb(i2c->base + REG_DAR);
  168. } else {
  169. writeb(msg->buf[idx++], i2c->base + REG_DAR);
  170. bcr = BCR_MSS | BCR_INTE | BCR_BEIE;
  171. writeb(bcr, i2c->base + REG_BCR);
  172. if (wait_irq(bus))
  173. return -EREMOTEIO;
  174. bsr = readb(i2c->base + REG_BSR);
  175. if (bsr & BSR_LRB) {
  176. debug("%s: no ack\n", __func__);
  177. return -EREMOTEIO;
  178. }
  179. }
  180. } while (idx < msg->len);
  181. }
  182. /* Force bus state to idle, terminating any ongoing transfer */
  183. writeb(0, i2c->base + REG_BCR);
  184. udelay(100);
  185. return 0;
  186. }
  187. static void synquacer_i2c_hw_reset(struct synquacer_i2c *i2c)
  188. {
  189. /* Disable clock */
  190. writeb(0, i2c->base + REG_CCR);
  191. writeb(0, i2c->base + REG_CSR);
  192. /* Set own Address */
  193. writeb(0, i2c->base + REG_ADR);
  194. /* Set PCLK frequency */
  195. writeb(BUS_CLK_FR(i2c->pclkrate), i2c->base + REG_FSR);
  196. /* clear IRQ (INT=0, BER=0), Interrupt Disable */
  197. writeb(0, i2c->base + REG_BCR);
  198. writeb(0, i2c->base + REG_BC2R);
  199. }
  200. static int synquacer_i2c_get_bus_speed(struct udevice *bus)
  201. {
  202. struct synquacer_i2c *i2c = dev_get_priv(bus);
  203. return i2c->speed_khz * 1000;
  204. }
  205. static int synquacer_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  206. {
  207. struct synquacer_i2c *i2c = dev_get_priv(bus);
  208. u32 rt = i2c->pclkrate;
  209. u8 ccr_cs, csr_cs;
  210. /* Set PCLK frequency */
  211. writeb(BUS_CLK_FR(i2c->pclkrate), i2c->base + REG_FSR);
  212. if (speed >= SPEED_FM * 1000) {
  213. i2c->speed_khz = SPEED_FM;
  214. if (i2c->pclkrate <= CLK_RATE_18M) {
  215. ccr_cs = CCR_CS_FAST_MAX_18M(rt);
  216. csr_cs = CSR_CS_FAST_MAX_18M(rt);
  217. } else {
  218. ccr_cs = CCR_CS_FAST_MIN_18M(rt);
  219. csr_cs = CSR_CS_FAST_MIN_18M(rt);
  220. }
  221. /* Set Clock and enable, Set fast mode */
  222. writeb(ccr_cs | CCR_FM | CCR_EN, i2c->base + REG_CCR);
  223. writeb(csr_cs, i2c->base + REG_CSR);
  224. } else {
  225. i2c->speed_khz = SPEED_SM;
  226. if (i2c->pclkrate <= CLK_RATE_18M) {
  227. ccr_cs = CCR_CS_STD_MAX_18M(rt);
  228. csr_cs = CSR_CS_STD_MAX_18M(rt);
  229. } else {
  230. ccr_cs = CCR_CS_STD_MIN_18M(rt);
  231. csr_cs = CSR_CS_STD_MIN_18M(rt);
  232. }
  233. /* Set Clock and enable, Set standard mode */
  234. writeb(ccr_cs | CCR_EN, i2c->base + REG_CCR);
  235. writeb(csr_cs, i2c->base + REG_CSR);
  236. }
  237. return 0;
  238. }
  239. static int synquacer_i2c_of_to_plat(struct udevice *bus)
  240. {
  241. struct synquacer_i2c *priv = dev_get_priv(bus);
  242. struct clk ck;
  243. int ret;
  244. ret = clk_get_by_index(bus, 0, &ck);
  245. if (ret < 0) {
  246. priv->pclkrate = I2C_CLK_DEF;
  247. } else {
  248. clk_enable(&ck);
  249. priv->pclkrate = clk_get_rate(&ck);
  250. }
  251. return 0;
  252. }
  253. static int synquacer_i2c_probe(struct udevice *bus)
  254. {
  255. struct synquacer_i2c *i2c = dev_get_priv(bus);
  256. i2c->base = dev_read_addr_ptr(bus);
  257. synquacer_i2c_hw_reset(i2c);
  258. synquacer_i2c_set_bus_speed(bus, 400000); /* set default speed */
  259. return 0;
  260. }
  261. static const struct dm_i2c_ops synquacer_i2c_ops = {
  262. .xfer = synquacer_i2c_xfer,
  263. .set_bus_speed = synquacer_i2c_set_bus_speed,
  264. .get_bus_speed = synquacer_i2c_get_bus_speed,
  265. };
  266. static const struct udevice_id synquacer_i2c_ids[] = {
  267. {
  268. .compatible = "socionext,synquacer-i2c",
  269. },
  270. { }
  271. };
  272. U_BOOT_DRIVER(sni_synquacer_i2c) = {
  273. .name = "sni_synquacer_i2c",
  274. .id = UCLASS_I2C,
  275. .of_match = synquacer_i2c_ids,
  276. .of_to_plat = synquacer_i2c_of_to_plat,
  277. .probe = synquacer_i2c_probe,
  278. .priv_auto = sizeof(struct synquacer_i2c),
  279. .ops = &synquacer_i2c_ops,
  280. };