sh_i2c.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011, 2013 Renesas Solutions Corp.
  4. * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  5. *
  6. * NOTE: This driver should be converted to driver model before June 2017.
  7. * Please see doc/driver-model/i2c-howto.rst for instructions.
  8. */
  9. #include <common.h>
  10. #include <i2c.h>
  11. #include <log.h>
  12. #include <asm/global_data.h>
  13. #include <asm/io.h>
  14. #include <linux/delay.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. /* Every register is 32bit aligned, but only 8bits in size */
  17. #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
  18. struct sh_i2c {
  19. ureg(icdr);
  20. ureg(iccr);
  21. ureg(icsr);
  22. ureg(icic);
  23. ureg(iccl);
  24. ureg(icch);
  25. };
  26. #undef ureg
  27. /* ICCR */
  28. #define SH_I2C_ICCR_ICE (1 << 7)
  29. #define SH_I2C_ICCR_RACK (1 << 6)
  30. #define SH_I2C_ICCR_RTS (1 << 4)
  31. #define SH_I2C_ICCR_BUSY (1 << 2)
  32. #define SH_I2C_ICCR_SCP (1 << 0)
  33. /* ICSR / ICIC */
  34. #define SH_IC_BUSY (1 << 4)
  35. #define SH_IC_TACK (1 << 2)
  36. #define SH_IC_WAIT (1 << 1)
  37. #define SH_IC_DTE (1 << 0)
  38. #ifdef CONFIG_SH_I2C_8BIT
  39. /* store 8th bit of iccl and icch in ICIC register */
  40. #define SH_I2C_ICIC_ICCLB8 (1 << 7)
  41. #define SH_I2C_ICIC_ICCHB8 (1 << 6)
  42. #endif
  43. static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
  44. (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
  45. #ifdef CONFIG_SYS_I2C_SH_BASE1
  46. (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
  47. #endif
  48. #ifdef CONFIG_SYS_I2C_SH_BASE2
  49. (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
  50. #endif
  51. #ifdef CONFIG_SYS_I2C_SH_BASE3
  52. (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
  53. #endif
  54. #ifdef CONFIG_SYS_I2C_SH_BASE4
  55. (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
  56. #endif
  57. };
  58. static u16 iccl, icch;
  59. #define IRQ_WAIT 1000
  60. static void sh_irq_dte(struct sh_i2c *dev)
  61. {
  62. int i;
  63. for (i = 0; i < IRQ_WAIT; i++) {
  64. if (SH_IC_DTE & readb(&dev->icsr))
  65. break;
  66. udelay(10);
  67. }
  68. }
  69. static int sh_irq_dte_with_tack(struct sh_i2c *dev)
  70. {
  71. int i;
  72. for (i = 0; i < IRQ_WAIT; i++) {
  73. if (SH_IC_DTE & readb(&dev->icsr))
  74. break;
  75. if (SH_IC_TACK & readb(&dev->icsr))
  76. return -1;
  77. udelay(10);
  78. }
  79. return 0;
  80. }
  81. static void sh_irq_busy(struct sh_i2c *dev)
  82. {
  83. int i;
  84. for (i = 0; i < IRQ_WAIT; i++) {
  85. if (!(SH_IC_BUSY & readb(&dev->icsr)))
  86. break;
  87. udelay(10);
  88. }
  89. }
  90. static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
  91. {
  92. u8 icic = SH_IC_TACK;
  93. debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
  94. __func__, chip, addr, iccl, icch);
  95. clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
  96. setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
  97. writeb(iccl & 0xff, &dev->iccl);
  98. writeb(icch & 0xff, &dev->icch);
  99. #ifdef CONFIG_SH_I2C_8BIT
  100. if (iccl > 0xff)
  101. icic |= SH_I2C_ICIC_ICCLB8;
  102. if (icch > 0xff)
  103. icic |= SH_I2C_ICIC_ICCHB8;
  104. #endif
  105. writeb(icic, &dev->icic);
  106. writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
  107. sh_irq_dte(dev);
  108. clrbits_8(&dev->icsr, SH_IC_TACK);
  109. writeb(chip << 1, &dev->icdr);
  110. if (sh_irq_dte_with_tack(dev) != 0)
  111. return -1;
  112. writeb(addr, &dev->icdr);
  113. if (stop)
  114. writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);
  115. if (sh_irq_dte_with_tack(dev) != 0)
  116. return -1;
  117. return 0;
  118. }
  119. static void sh_i2c_finish(struct sh_i2c *dev)
  120. {
  121. writeb(0, &dev->icsr);
  122. clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
  123. }
  124. static int
  125. sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
  126. {
  127. int ret = -1;
  128. if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
  129. goto exit0;
  130. udelay(10);
  131. writeb(val, &dev->icdr);
  132. if (sh_irq_dte_with_tack(dev) != 0)
  133. goto exit0;
  134. writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr);
  135. if (sh_irq_dte_with_tack(dev) != 0)
  136. goto exit0;
  137. sh_irq_busy(dev);
  138. ret = 0;
  139. exit0:
  140. sh_i2c_finish(dev);
  141. return ret;
  142. }
  143. static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
  144. {
  145. int ret = -1;
  146. #if defined(CONFIG_SH73A0)
  147. if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
  148. goto exit0;
  149. #else
  150. if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
  151. goto exit0;
  152. udelay(100);
  153. #endif
  154. writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
  155. sh_irq_dte(dev);
  156. writeb(chip << 1 | 0x01, &dev->icdr);
  157. if (sh_irq_dte_with_tack(dev) != 0)
  158. goto exit0;
  159. writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr);
  160. if (sh_irq_dte_with_tack(dev) != 0)
  161. goto exit0;
  162. ret = readb(&dev->icdr) & 0xff;
  163. writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr);
  164. readb(&dev->icdr); /* Dummy read */
  165. sh_irq_busy(dev);
  166. exit0:
  167. sh_i2c_finish(dev);
  168. return ret;
  169. }
  170. static void
  171. sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
  172. {
  173. int num, denom, tmp;
  174. /* No i2c support prior to relocation */
  175. if (!(gd->flags & GD_FLG_RELOC))
  176. return;
  177. /*
  178. * Calculate the value for iccl. From the data sheet:
  179. * iccl = (p-clock / transfer-rate) * (L / (L + H))
  180. * where L and H are the SCL low and high ratio.
  181. */
  182. num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
  183. denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
  184. tmp = num * 10 / denom;
  185. if (tmp % 10 >= 5)
  186. iccl = (u16)((num/denom) + 1);
  187. else
  188. iccl = (u16)(num/denom);
  189. /* Calculate the value for icch. From the data sheet:
  190. icch = (p clock / transfer rate) * (H / (L + H)) */
  191. num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
  192. tmp = num * 10 / denom;
  193. if (tmp % 10 >= 5)
  194. icch = (u16)((num/denom) + 1);
  195. else
  196. icch = (u16)(num/denom);
  197. debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
  198. CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
  199. }
  200. static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
  201. uint addr, int alen, u8 *data, int len)
  202. {
  203. int ret, i;
  204. struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
  205. for (i = 0; i < len; i++) {
  206. ret = sh_i2c_raw_read(dev, chip, addr + i);
  207. if (ret < 0)
  208. return -1;
  209. data[i] = ret & 0xff;
  210. debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
  211. }
  212. return 0;
  213. }
  214. static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
  215. int alen, u8 *data, int len)
  216. {
  217. struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
  218. int i;
  219. for (i = 0; i < len; i++) {
  220. debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
  221. if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
  222. return -1;
  223. }
  224. return 0;
  225. }
  226. static int
  227. sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
  228. {
  229. u8 dummy[1];
  230. return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy);
  231. }
  232. static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
  233. unsigned int speed)
  234. {
  235. struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
  236. sh_i2c_finish(dev);
  237. sh_i2c_init(adap, speed, 0);
  238. return 0;
  239. }
  240. /*
  241. * Register RCAR i2c adapters
  242. */
  243. U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
  244. sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
  245. #ifdef CONFIG_SYS_I2C_SH_BASE1
  246. U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
  247. sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
  248. #endif
  249. #ifdef CONFIG_SYS_I2C_SH_BASE2
  250. U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
  251. sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
  252. #endif
  253. #ifdef CONFIG_SYS_I2C_SH_BASE3
  254. U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
  255. sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
  256. #endif
  257. #ifdef CONFIG_SYS_I2C_SH_BASE4
  258. U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
  259. sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)
  260. #endif